[linux-2.6-block.git] / arch / arm / boot / dts / armada-xp-gp.dts

/*
 * Device Tree file for Marvell Armada XP development board
 * (DB-MV784MP-GP)
 *
 * Copyright (C) 2013-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/*
                 * 8 GB of plug-in RAM modules by default.The amount
                 * of memory available can be changed by the
                 * bootloader according the size of the module
                 * actually plugged. However, memory between
                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
                 * the address range used for I/O (internal registers,
                 * MBus windows).
		 */
		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
		      <0x00000001 0x00000000 0x00000001 0x00000000>;
	};

	cpus {
		pm_pic {
			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
				     <&gpio0 17 GPIO_ACTIVE_LOW>,
				     <&gpio0 18 GPIO_ACTIVE_LOW>;
		};
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		devbus-bootcs {
			status = "okay";

			/* Device Bus parameters are required */

			/* Read parameters */
			devbus,bus-width    = <16>;
			devbus,turn-off-ps  = <60000>;
			devbus,badr-skew-ps = <0>;
			devbus,acc-first-ps = <124000>;
			devbus,acc-next-ps  = <248000>;
			devbus,rd-setup-ps  = <0>;
			devbus,rd-hold-ps   = <0>;

			/* Write parameters */
			devbus,sync-enable = <0>;
			devbus,wr-high-ps  = <60000>;
			devbus,wr-low-ps   = <60000>;
			devbus,ale-wr-ps   = <60000>;

			/* NOR 16 MiB */
			nor@0 {
				compatible = "cfi-flash";
				reg = <0 0x1000000>;
				bank-width = <2>;
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};
			pinctrl {
				pinctrl-0 = <&pic_pins>;
				pinctrl-names = "default";
				pic_pins: pic-pins-0 {
					marvell,pins = "mpp16", "mpp17",
						       "mpp18";
					marvell,function = "gpio";
				};
			};
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
			};

			/* Front-side USB slot */
			usb@50000 {
				status = "okay";
			};

			/* Back-side USB slot */
			usb@51000 {
				status = "okay";
			};

			bm@c0000 {
				status = "okay";
			};

			nand@d0000 {
				status = "okay";
				num-cs = <1>;
				marvell,nand-keep-config;
				marvell,nand-enable-arbiter;
				nand-on-flash-bbt;
			};
		};

		bm-bppi {
			status = "okay";
		};
	};
};

&pciec {
	status = "okay";

	/*
	 * The 3 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@10,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <16>;
	};

	phy1: ethernet-phy@1 {
		reg = <17>;
	};

	phy2: ethernet-phy@2 {
		reg = <18>;
	};

	phy3: ethernet-phy@3 {
		reg = <19>;
	};
};

&spi0 {
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
	};
};
Commit	Line	Data
568fc0a3 GC	1	/*
	2	* Device Tree file for Marvell Armada XP development board
	3	* (DB-MV784MP-GP)
	4	*
91ed3220	5	* Copyright (C) 2013-2014 Marvell
568fc0a3 GC	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
a0f22f8e GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
24f0b6fe	21	* This file is distributed in the hope that it will be useful,
a0f22f8e GC	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
24f0b6fe	26	* Or, alternatively,
a0f22f8e GC	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
24f0b6fe	31	* restriction, including without limitation the rights to use,
a0f22f8e GC	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
24f0b6fe	40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
a0f22f8e GC	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
24f0b6fe	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
a0f22f8e GC	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
91ed3220 TP	48	*
	49	* Note: this Device Tree assumes that the bootloader has remapped the
	50	* internal registers to 0xf1000000 (instead of the default
	51	* 0xd0000000). The 0xf1000000 is the default used by the recent,
	52	* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
	53	* boards were delivered with an older version of the bootloader that
	54	* left internal registers mapped at 0xd0000000. If you are in this
	55	* situation, you should either update your bootloader (preferred
	56	* solution) or the below Device Tree should be adjusted.
568fc0a3 GC	57	*/
	58
	59	/dts-v1/;
389a367a	60	#include <dt-bindings/gpio/gpio.h>
38149887	61	#include "armada-xp-mv78460.dtsi"
568fc0a3 GC	62
	63	/ {
	64	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
	65	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
	66
	67	chosen {
9552203c	68	stdout-path = "serial0:115200n8";
568fc0a3 GC	69	};
568fc0a3 GC	70
6f477f43	71	memory@0 {
568fc0a3	72	device_type = "memory";
568fc0a3	73	/*
74898364 GC	74	* 8 GB of plug-in RAM modules by default.The amount
	75	* of memory available can be changed by the
	76	* bootloader according the size of the module
91ed3220 TP	77	* actually plugged. However, memory between
	78	* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
	79	* the address range used for I/O (internal registers,
	80	* MBus windows).
568fc0a3	81	*/
91ed3220	82	reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
74898364	83	<0x00000001 0x00000000 0x00000001 0x00000000>;
568fc0a3 GC	84	};
568fc0a3 GC	85
389a367a TP	86	cpus {
	87	pm_pic {
	88	ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
	89	<&gpio0 17 GPIO_ACTIVE_LOW>,
	90	<&gpio0 18 GPIO_ACTIVE_LOW>;
	91	};
	92	};
	93
568fc0a3	94	soc {
91ed3220	95	ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
de1af8d4	96	MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
c466d997	97	MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
d7d5a43c	98	MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
1200b680	99	MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
9dd7a57e	100	MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
de1af8d4 EG	101
	102	devbus-bootcs {
	103	status = "okay";
	104
	105	/* Device Bus parameters are required */
	106
	107	/* Read parameters */
1a88f809	108	devbus,bus-width = <16>;
de1af8d4 EG	109	devbus,turn-off-ps = <60000>;
	110	devbus,badr-skew-ps = <0>;
	111	devbus,acc-first-ps = <124000>;
	112	devbus,acc-next-ps = <248000>;
	113	devbus,rd-setup-ps = <0>;
	114	devbus,rd-hold-ps = <0>;
	115
	116	/* Write parameters */
	117	devbus,sync-enable = <0>;
	118	devbus,wr-high-ps = <60000>;
	119	devbus,wr-low-ps = <60000>;
	120	devbus,ale-wr-ps = <60000>;
	121
	122	/* NOR 16 MiB */
	123	nor@0 {
	124	compatible = "cfi-flash";
	125	reg = <0 0x1000000>;
	126	bank-width = <2>;
	127	};
	128	};
c6c003af	129
467f54b2 GC	130	internal-regs {
467f54b2 GC	131	serial@12000 {
467f54b2	132	status = "okay";
568fc0a3	133	};
467f54b2	134	serial@12100 {
467f54b2	135	status = "okay";
568fc0a3	136	};
467f54b2	137	serial@12200 {
467f54b2 GC	138	status = "okay";
	139	};
	140	serial@12300 {
467f54b2	141	status = "okay";
568fc0a3	142	};
389a367a TP	143	pinctrl {
	144	pinctrl-0 = <&pic_pins>;
	145	pinctrl-names = "default";
	146	pic_pins: pic-pins-0 {
	147	marvell,pins = "mpp16", "mpp17",
	148	"mpp18";
	149	marvell,function = "gpio";
	150	};
	151	};
467f54b2 GC	152	sata@a0000 {
	153	nr-ports = <2>;
	154	status = "okay";
568fc0a3	155	};
568fc0a3	156
467f54b2 GC	157	ethernet@70000 {
	158	status = "okay";
	159	phy = <&phy0>;
80fa10f4	160	phy-mode = "qsgmii";
9dd7a57e MW	161	buffer-manager = <&bm>;
9dd7a57e MW	162	bm,pool-long = <0>;
467f54b2 GC	163	};
	164	ethernet@74000 {
	165	status = "okay";
	166	phy = <&phy1>;
80fa10f4	167	phy-mode = "qsgmii";
9dd7a57e MW	168	buffer-manager = <&bm>;
9dd7a57e MW	169	bm,pool-long = <1>;
467f54b2 GC	170	};
	171	ethernet@30000 {
	172	status = "okay";
	173	phy = <&phy2>;
80fa10f4	174	phy-mode = "qsgmii";
9dd7a57e MW	175	buffer-manager = <&bm>;
9dd7a57e MW	176	bm,pool-long = <2>;
467f54b2 GC	177	};
	178	ethernet@34000 {
	179	status = "okay";
	180	phy = <&phy3>;
80fa10f4	181	phy-mode = "qsgmii";
9dd7a57e MW	182	buffer-manager = <&bm>;
9dd7a57e MW	183	bm,pool-long = <3>;
467f54b2	184	};
513a7917	185
0e99b153 TP	186	/* Front-side USB slot */
	187	usb@50000 {
	188	status = "okay";
	189	};
	190
	191	/* Back-side USB slot */
	192	usb@51000 {
	193	status = "okay";
	194	};
	195
9dd7a57e MW	196	bm@c0000 {
	197	status = "okay";
	198	};
	199
2be2bc39 EG	200	nand@d0000 {
	201	status = "okay";
	202	num-cs = <1>;
	203	marvell,nand-keep-config;
	204	marvell,nand-enable-arbiter;
	205	nand-on-flash-bbt;
	206	};
513a7917	207	};
9dd7a57e MW	208
	209	bm-bppi {
	210	status = "okay";
	211	};
568fc0a3 GC	212	};
568fc0a3 GC	213	};
0160a4b6	214
007d05d8 GC	215	&pciec {
	216	status = "okay";
	217
	218	/*
	219	* The 3 slots are physically present as
	220	* standard PCIe slots on the board.
	221	*/
	222	pcie@1,0 {
	223	/* Port 0, Lane 0 */
	224	status = "okay";
	225	};
	226	pcie@9,0 {
	227	/* Port 2, Lane 0 */
	228	status = "okay";
	229	};
	230	pcie@10,0 {
	231	/* Port 3, Lane 0 */
	232	status = "okay";
	233	};
	234	};
	235
1fc21295 GC	236	&mdio {
	237	phy0: ethernet-phy@0 {
	238	reg = <16>;
	239	};
	240
	241	phy1: ethernet-phy@1 {
	242	reg = <17>;
	243	};
	244
	245	phy2: ethernet-phy@2 {
	246	reg = <18>;
	247	};
	248
	249	phy3: ethernet-phy@3 {
	250	reg = <19>;
	251	};
	252	};
	253
0160a4b6 SR	254	&spi0 {
	255	status = "okay";
	256
	257	spi-flash@0 {
	258	#address-cells = <1>;
	259	#size-cells = <1>;
	260	compatible = "n25q128a13", "jedec,spi-nor";
	261	reg = <0>; /* Chip select 0 */
	262	spi-max-frequency = <108000000>;
	263	};
	264	};