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9ae6f740 TP |
1 | /* |
2 | * Device Tree file for Marvell Armada XP evaluation board | |
3 | * (DB-78460-BP) | |
4 | * | |
5 | * Copyright (C) 2012 Marvell | |
6 | * | |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | /dts-v1/; | |
0bec30a7 | 17 | /include/ "armada-xp-mv78460.dtsi" |
9ae6f740 TP |
18 | |
19 | / { | |
20 | model = "Marvell Armada XP Evaluation Board"; | |
0bec30a7 | 21 | compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; |
9ae6f740 TP |
22 | |
23 | chosen { | |
24 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
25 | }; | |
26 | ||
27 | memory { | |
28 | device_type = "memory"; | |
74898364 | 29 | reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ |
9ae6f740 TP |
30 | }; |
31 | ||
32 | soc { | |
467f54b2 GC |
33 | internal-regs { |
34 | serial@12000 { | |
35 | clock-frequency = <250000000>; | |
36 | status = "okay"; | |
f01959a9 | 37 | }; |
467f54b2 GC |
38 | serial@12100 { |
39 | clock-frequency = <250000000>; | |
40 | status = "okay"; | |
f01959a9 | 41 | }; |
467f54b2 GC |
42 | serial@12200 { |
43 | clock-frequency = <250000000>; | |
44 | status = "okay"; | |
f01959a9 | 45 | }; |
467f54b2 GC |
46 | serial@12300 { |
47 | clock-frequency = <250000000>; | |
48 | status = "okay"; | |
f01959a9 | 49 | }; |
200506b1 | 50 | |
467f54b2 GC |
51 | sata@a0000 { |
52 | nr-ports = <2>; | |
53 | status = "okay"; | |
54 | }; | |
200506b1 | 55 | |
467f54b2 GC |
56 | mdio { |
57 | phy0: ethernet-phy@0 { | |
58 | reg = <0>; | |
59 | }; | |
200506b1 | 60 | |
467f54b2 GC |
61 | phy1: ethernet-phy@1 { |
62 | reg = <1>; | |
63 | }; | |
1f24a21f | 64 | |
467f54b2 GC |
65 | phy2: ethernet-phy@2 { |
66 | reg = <25>; | |
67 | }; | |
1f24a21f | 68 | |
467f54b2 GC |
69 | phy3: ethernet-phy@3 { |
70 | reg = <27>; | |
71 | }; | |
1f24a21f | 72 | }; |
bf4f9c63 | 73 | |
467f54b2 GC |
74 | ethernet@70000 { |
75 | status = "okay"; | |
76 | phy = <&phy0>; | |
77 | phy-mode = "rgmii-id"; | |
78 | }; | |
79 | ethernet@74000 { | |
80 | status = "okay"; | |
81 | phy = <&phy1>; | |
82 | phy-mode = "rgmii-id"; | |
83 | }; | |
84 | ethernet@30000 { | |
85 | status = "okay"; | |
86 | phy = <&phy2>; | |
87 | phy-mode = "sgmii"; | |
88 | }; | |
89 | ethernet@34000 { | |
90 | status = "okay"; | |
91 | phy = <&phy3>; | |
92 | phy-mode = "sgmii"; | |
93 | }; | |
bf4f9c63 | 94 | |
467f54b2 GC |
95 | mvsdio@d4000 { |
96 | pinctrl-0 = <&sdio_pins>; | |
97 | pinctrl-names = "default"; | |
bf4f9c63 | 98 | status = "okay"; |
467f54b2 | 99 | /* No CD or WP GPIOs */ |
d87b5fbb | 100 | broken-cd; |
bf4f9c63 | 101 | }; |
467f54b2 GC |
102 | |
103 | usb@50000 { | |
bf4f9c63 TP |
104 | status = "okay"; |
105 | }; | |
467f54b2 GC |
106 | |
107 | usb@51000 { | |
bf4f9c63 TP |
108 | status = "okay"; |
109 | }; | |
467f54b2 GC |
110 | |
111 | usb@52000 { | |
bf4f9c63 TP |
112 | status = "okay"; |
113 | }; | |
467f54b2 GC |
114 | |
115 | spi0: spi@10600 { | |
bf4f9c63 | 116 | status = "okay"; |
467f54b2 GC |
117 | |
118 | spi-flash@0 { | |
119 | #address-cells = <1>; | |
120 | #size-cells = <1>; | |
121 | compatible = "m25p64"; | |
122 | reg = <0>; /* Chip select 0 */ | |
123 | spi-max-frequency = <20000000>; | |
124 | }; | |
bf4f9c63 | 125 | }; |
467f54b2 GC |
126 | |
127 | pcie-controller { | |
bf4f9c63 | 128 | status = "okay"; |
467f54b2 GC |
129 | |
130 | /* | |
131 | * All 6 slots are physically present as | |
132 | * standard PCIe slots on the board. | |
133 | */ | |
134 | pcie@1,0 { | |
135 | /* Port 0, Lane 0 */ | |
136 | status = "okay"; | |
137 | }; | |
138 | pcie@2,0 { | |
139 | /* Port 0, Lane 1 */ | |
140 | status = "okay"; | |
141 | }; | |
142 | pcie@3,0 { | |
143 | /* Port 0, Lane 2 */ | |
144 | status = "okay"; | |
145 | }; | |
146 | pcie@4,0 { | |
147 | /* Port 0, Lane 3 */ | |
148 | status = "okay"; | |
149 | }; | |
150 | pcie@9,0 { | |
151 | /* Port 2, Lane 0 */ | |
152 | status = "okay"; | |
153 | }; | |
154 | pcie@10,0 { | |
155 | /* Port 3, Lane 0 */ | |
156 | status = "okay"; | |
157 | }; | |
bf4f9c63 TP |
158 | }; |
159 | }; | |
9ae6f740 TP |
160 | }; |
161 | }; |