Commit | Line | Data |
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9ae6f740 TP |
1 | /* |
2 | * Device Tree file for Marvell Armada XP evaluation board | |
3 | * (DB-78460-BP) | |
4 | * | |
5 | * Copyright (C) 2012 Marvell | |
6 | * | |
7 | * Lior Amsalem <alior@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | /dts-v1/; | |
0bec30a7 | 17 | /include/ "armada-xp-mv78460.dtsi" |
9ae6f740 TP |
18 | |
19 | / { | |
20 | model = "Marvell Armada XP Evaluation Board"; | |
0bec30a7 | 21 | compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; |
9ae6f740 TP |
22 | |
23 | chosen { | |
24 | bootargs = "console=ttyS0,115200 earlyprintk"; | |
25 | }; | |
26 | ||
27 | memory { | |
28 | device_type = "memory"; | |
29 | reg = <0x00000000 0x80000000>; /* 2 GB */ | |
30 | }; | |
31 | ||
32 | soc { | |
82a68267 | 33 | serial@12000 { |
9ae6f740 TP |
34 | clock-frequency = <250000000>; |
35 | status = "okay"; | |
36 | }; | |
82a68267 | 37 | serial@12100 { |
9ae6f740 TP |
38 | clock-frequency = <250000000>; |
39 | status = "okay"; | |
40 | }; | |
82a68267 | 41 | serial@12200 { |
9ae6f740 TP |
42 | clock-frequency = <250000000>; |
43 | status = "okay"; | |
44 | }; | |
82a68267 | 45 | serial@12300 { |
9ae6f740 TP |
46 | clock-frequency = <250000000>; |
47 | status = "okay"; | |
48 | }; | |
f01959a9 | 49 | |
82a68267 | 50 | sata@a0000 { |
3d82daaa GC |
51 | nr-ports = <2>; |
52 | status = "okay"; | |
53 | }; | |
089c38e7 | 54 | |
f01959a9 TP |
55 | mdio { |
56 | phy0: ethernet-phy@0 { | |
57 | reg = <0>; | |
58 | }; | |
59 | ||
60 | phy1: ethernet-phy@1 { | |
61 | reg = <1>; | |
62 | }; | |
63 | ||
64 | phy2: ethernet-phy@2 { | |
65 | reg = <25>; | |
66 | }; | |
67 | ||
68 | phy3: ethernet-phy@3 { | |
69 | reg = <27>; | |
70 | }; | |
71 | }; | |
72 | ||
82a68267 | 73 | ethernet@70000 { |
f01959a9 TP |
74 | status = "okay"; |
75 | phy = <&phy0>; | |
76 | phy-mode = "rgmii-id"; | |
77 | }; | |
82a68267 | 78 | ethernet@74000 { |
f01959a9 TP |
79 | status = "okay"; |
80 | phy = <&phy1>; | |
81 | phy-mode = "rgmii-id"; | |
82 | }; | |
82a68267 | 83 | ethernet@30000 { |
f01959a9 TP |
84 | status = "okay"; |
85 | phy = <&phy2>; | |
86 | phy-mode = "sgmii"; | |
87 | }; | |
82a68267 | 88 | ethernet@34000 { |
f01959a9 TP |
89 | status = "okay"; |
90 | phy = <&phy3>; | |
91 | phy-mode = "sgmii"; | |
92 | }; | |
d64c129b | 93 | |
82a68267 | 94 | mvsdio@d4000 { |
d64c129b TP |
95 | pinctrl-0 = <&sdio_pins>; |
96 | pinctrl-names = "default"; | |
97 | status = "okay"; | |
98 | /* No CD or WP GPIOs */ | |
99 | }; | |
200506b1 | 100 | |
82a68267 | 101 | usb@50000 { |
200506b1 EG |
102 | status = "okay"; |
103 | }; | |
104 | ||
82a68267 | 105 | usb@51000 { |
200506b1 EG |
106 | status = "okay"; |
107 | }; | |
108 | ||
82a68267 | 109 | usb@52000 { |
200506b1 EG |
110 | status = "okay"; |
111 | }; | |
1f24a21f | 112 | |
82a68267 | 113 | spi0: spi@10600 { |
1f24a21f GC |
114 | status = "okay"; |
115 | ||
116 | spi-flash@0 { | |
117 | #address-cells = <1>; | |
118 | #size-cells = <1>; | |
119 | compatible = "m25p64"; | |
120 | reg = <0>; /* Chip select 0 */ | |
121 | spi-max-frequency = <20000000>; | |
122 | }; | |
123 | }; | |
bf4f9c63 TP |
124 | |
125 | pcie-controller { | |
126 | status = "okay"; | |
127 | ||
128 | /* | |
129 | * All 6 slots are physically present as | |
130 | * standard PCIe slots on the board. | |
131 | */ | |
132 | pcie@1,0 { | |
133 | /* Port 0, Lane 0 */ | |
134 | status = "okay"; | |
135 | }; | |
136 | pcie@2,0 { | |
137 | /* Port 0, Lane 1 */ | |
138 | status = "okay"; | |
139 | }; | |
140 | pcie@3,0 { | |
141 | /* Port 0, Lane 2 */ | |
142 | status = "okay"; | |
143 | }; | |
144 | pcie@4,0 { | |
145 | /* Port 0, Lane 3 */ | |
146 | status = "okay"; | |
147 | }; | |
148 | pcie@9,0 { | |
149 | /* Port 2, Lane 0 */ | |
150 | status = "okay"; | |
151 | }; | |
152 | pcie@10,0 { | |
153 | /* Port 3, Lane 0 */ | |
154 | status = "okay"; | |
155 | }; | |
156 | }; | |
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157 | }; |
158 | }; |