[linux-2.6-block.git] / arch / arm / boot / dts / armada-xp-98dx3236.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell 98dx3236 family SoC
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Contains definitions specific to the 98dx3236 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	model = "Marvell 98DX3236 SoC";
	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,98dx3236-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		/*
		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};
		};

		internal-regs {
			sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache@8000 {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			/* does not exist */
			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				status = "disabled";
			};

			gpio2: gpio@18180 { /* rework some properties */
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <1>; /* only gpio #32 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,mv98dx3236-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,mv98dx3236-cpu-clock";
				reg = <0x18700 0x24>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			corediv-clock@18740 {
				status = "disabled";
			};

			cpu-config@21000 {
				compatible = "marvell,armada-xp-cpu-config";
				reg = <0x21000 0x8>;
			};

			ethernet@70000 {
				compatible = "marvell,armada-xp-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-xp-neta";
			};

			xor1: xor@f0800 {
				compatible = "marvell,orion-xor";
				reg = <0xf0800 0x100
				       0xf0a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			nand: nand@d0000 {
				clocks = <&dfx_coredivclk 0>;
			};

			xor0: xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};

		dfx: dfx-server@ac000000 {
			compatible = "marvell,dfx-server", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;

			coreclk: mvebu-sar@f8204 {
				compatible = "marvell,mv98dx3236-core-clock";
				reg = <0xf8204 0x4>;
				#clock-cells = <1>;
			};

			dfx_coredivclk: corediv-clock@f8268 {
				compatible = "marvell,mv98dx3236-corediv-clock";
				reg = <0xf8268 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		switch: switch@a8000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;

			pp0: packet-processor@0 {
				compatible = "marvell,prestera-98dx3236";
				reg = <0 0x4000000>;
				interrupts = <33>, <34>, <35>;
				dfx = <&dfx>;
			};
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&i2c0 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11000 0x100>;
};

&i2c1 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11100 0x100>;
};

&mpic {
	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};

&rtc {
	status = "disabled";
};

&timer {
	compatible = "marvell,armada-xp-timer";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&watchdog {
	compatible = "marvell,armada-xp-wdt";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&cpurst {
	reg = <0x20800 0x20>;
};

&usb0 {
	clocks = <&gateclk 18>;
};

&usb1 {
	clocks = <&gateclk 19>;
};

&pinctrl {
	compatible = "marvell,98dx3236-pinctrl";

	nand_pins: nand-pins {
		marvell,pins = "mpp20", "mpp21", "mpp22",
			       "mpp23", "mpp24", "mpp25",
			       "mpp26", "mpp27", "mpp28",
			       "mpp29", "mpp30";
		marvell,function = "dev";
	};

	nand_rb: nand-rb {
		marvell,pins = "mpp19";
		marvell,function = "nand";
	};

	spi0_pins: spi0-pins {
		marvell,pins = "mpp0", "mpp1",
			       "mpp2", "mpp3";
		marvell,function = "spi0";
	};
};

&spi0 {
	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
};

&sdio {
	status = "disabled";
};
Commit	Line	Data
d816b3cc	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3f81df55 CP	2	/*
	3	* Device Tree Include file for Marvell 98dx3236 family SoC
	4	*
	5	* Copyright (C) 2016 Allied Telesis Labs
	6	*
3f81df55 CP	7	* Contains definitions specific to the 98dx3236 SoC that are not
	8	* common to all Armada XP SoCs.
	9	*/
	10
43e28ba8	11	#include "armada-370-xp.dtsi"
3f81df55 CP	12
3f81df55 CP	13	/ {
43e28ba8 CP	14	#address-cells = <2>;
	15	#size-cells = <2>;
	16
3f81df55	17	model = "Marvell 98DX3236 SoC";
43e28ba8	18	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
3f81df55 CP	19
	20	aliases {
	21	gpio0 = &gpio0;
	22	gpio1 = &gpio1;
	23	gpio2 = &gpio2;
	24	};
	25
	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29	enable-method = "marvell,98dx3236-smp";
	30
	31	cpu@0 {
	32	device_type = "cpu";
	33	compatible = "marvell,sheeva-v7";
	34	reg = <0>;
	35	clocks = <&cpuclk 0>;
	36	clock-latency = <1000000>;
	37	};
	38	};
	39
	40	soc {
43e28ba8 CP	41	compatible = "marvell,armadaxp-mbus", "simple-bus";
43e28ba8 CP	42
3f81df55 CP	43	ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
	44	MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
	45	MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
	46	MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
	47	MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
	48
43e28ba8 CP	49	bootrom {
	50	compatible = "marvell,bootrom";
	51	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	52	};
	53
3f81df55 CP	54	/*
	55	* 98DX3236 has 1 x1 PCIe unit Gen2.0
	56	*/
28fbb9c5	57	pciec: pcie@82000000 {
3f81df55 CP	58	compatible = "marvell,armada-xp-pcie";
	59	status = "disabled";
	60	device_type = "pci";
	61
	62	#address-cells = <3>;
	63	#size-cells = <2>;
	64
	65	msi-parent = <&mpic>;
	66	bus-range = <0x00 0xff>;
	67
	68	ranges =
	69	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	70	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
23988bab	71	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
3f81df55 CP	72
	73	pcie1: pcie@1,0 {
	74	device_type = "pci";
	75	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	76	reg = <0x0800 0 0 0 0>;
	77	#address-cells = <3>;
	78	#size-cells = <2>;
	79	#interrupt-cells = <1>;
	80	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	81	0x81000000 0 0 0x81000000 0x1 0 1 0>;
28fbb9c5	82	bus-range = <0x00 0xff>;
3f81df55 CP	83	interrupt-map-mask = <0 0 0 0>;
	84	interrupt-map = <0 0 0 0 &mpic 58>;
	85	marvell,pcie-port = <0>;
	86	marvell,pcie-lane = <0>;
	87	clocks = <&gateclk 5>;
	88	status = "disabled";
	89	};
	90	};
	91
	92	internal-regs {
43e28ba8 CP	93	sdramc@1400 {
	94	compatible = "marvell,armada-xp-sdram-controller";
	95	reg = <0x1400 0x500>;
	96	};
	97
	98	L2: l2-cache@8000 {
	99	compatible = "marvell,aurora-system-cache";
	100	reg = <0x08000 0x1000>;
	101	cache-id-part = <0x100>;
	102	cache-level = <2>;
	103	cache-unified;
	104	wt-override;
	105	};
	106
	107	gpio0: gpio@18100 {
	108	compatible = "marvell,orion-gpio";
	109	reg = <0x18100 0x40>;
	110	ngpios = <32>;
	111	gpio-controller;
	112	#gpio-cells = <2>;
	113	interrupt-controller;
	114	#interrupt-cells = <2>;
	115	interrupts = <82>, <83>, <84>, <85>;
	116	};
	117
	118	/* does not exist */
	119	gpio1: gpio@18140 {
	120	compatible = "marvell,orion-gpio";
	121	reg = <0x18140 0x40>;
	122	status = "disabled";
	123	};
	124
	125	gpio2: gpio@18180 { /* rework some properties */
	126	compatible = "marvell,orion-gpio";
	127	reg = <0x18180 0x40>;
	128	ngpios = <1>; /* only gpio #32 */
	129	gpio-controller;
	130	#gpio-cells = <2>;
	131	interrupt-controller;
	132	#interrupt-cells = <2>;
	133	interrupts = <87>;
	134	};
	135
	136	systemc: system-controller@18200 {
	137	compatible = "marvell,armada-370-xp-system-controller";
	138	reg = <0x18200 0x500>;
	139	};
	140
	141	gateclk: clock-gating-control@18220 {
b4bcfccb	142	compatible = "marvell,mv98dx3236-gating-clock";
43e28ba8 CP	143	reg = <0x18220 0x4>;
	144	clocks = <&coreclk 0>;
	145	#clock-cells = <1>;
	146	};
	147
3f81df55	148	cpuclk: clock-complex@18700 {
43e28ba8	149	#clock-cells = <1>;
3f81df55	150	compatible = "marvell,mv98dx3236-cpu-clock";
43e28ba8 CP	151	reg = <0x18700 0x24>, <0x1c054 0x10>;
43e28ba8 CP	152	clocks = <&coreclk 1>;
3f81df55 CP	153	};
	154
	155	corediv-clock@18740 {
	156	status = "disabled";
	157	};
	158
43e28ba8 CP	159	cpu-config@21000 {
	160	compatible = "marvell,armada-xp-cpu-config";
	161	reg = <0x21000 0x8>;
3f81df55 CP	162	};
3f81df55 CP	163
43e28ba8 CP	164	ethernet@70000 {
43e28ba8 CP	165	compatible = "marvell,armada-xp-neta";
3f81df55 CP	166	};
3f81df55 CP	167
43e28ba8 CP	168	ethernet@74000 {
43e28ba8 CP	169	compatible = "marvell,armada-xp-neta";
3f81df55 CP	170	};
3f81df55 CP	171
43e28ba8	172	xor1: xor@f0800 {
3f81df55 CP	173	compatible = "marvell,orion-xor";
	174	reg = <0xf0800 0x100
	175	0xf0a00 0x100>;
	176	clocks = <&gateclk 22>;
	177	status = "okay";
	178
	179	xor10 {
	180	interrupts = <51>;
	181	dmacap,memcpy;
	182	dmacap,xor;
	183	};
	184	xor11 {
	185	interrupts = <52>;
	186	dmacap,memcpy;
	187	dmacap,xor;
	188	dmacap,memset;
	189	};
	190	};
	191
43e28ba8 CP	192	nand: nand@d0000 {
43e28ba8 CP	193	clocks = <&dfx_coredivclk 0>;
3f81df55 CP	194	};
3f81df55 CP	195
43e28ba8 CP	196	xor0: xor@f0900 {
	197	compatible = "marvell,orion-xor";
	198	reg = <0xF0900 0x100
	199	0xF0B00 0x100>;
	200	clocks = <&gateclk 28>;
	201	status = "okay";
3f81df55	202
43e28ba8 CP	203	xor00 {
	204	interrupts = <94>;
	205	dmacap,memcpy;
	206	dmacap,xor;
	207	};
	208	xor01 {
	209	interrupts = <95>;
	210	dmacap,memcpy;
	211	dmacap,xor;
	212	dmacap,memset;
	213	};
3f81df55 CP	214	};
	215	};
	216
35a647f1 CP	217	dfx: dfx-server@ac000000 {
35a647f1 CP	218	compatible = "marvell,dfx-server", "simple-bus";
3f81df55 CP	219	#address-cells = <1>;
	220	#size-cells = <1>;
	221	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
35a647f1	222	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
3f81df55	223
b4bcfccb CP	224	coreclk: mvebu-sar@f8204 {
	225	compatible = "marvell,mv98dx3236-core-clock";
	226	reg = <0xf8204 0x4>;
	227	#clock-cells = <1>;
	228	};
	229
3f81df55 CP	230	dfx_coredivclk: corediv-clock@f8268 {
	231	compatible = "marvell,mv98dx3236-corediv-clock";
	232	reg = <0xf8268 0xc>;
	233	#clock-cells = <1>;
	234	clocks = <&mainpll>;
	235	clock-output-names = "nand";
	236	};
3f81df55 CP	237	};
	238
	239	switch: switch@a8000000 {
	240	compatible = "simple-bus";
	241	#address-cells = <1>;
	242	#size-cells = <1>;
	243	ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
	244
	245	pp0: packet-processor@0 {
	246	compatible = "marvell,prestera-98dx3236";
	247	reg = <0 0x4000000>;
	248	interrupts = <33>, <34>, <35>;
	249	dfx = <&dfx>;
	250	};
	251	};
	252	};
43e28ba8 CP	253
	254	clocks {
	255	/* 25 MHz reference crystal */
	256	refclk: oscillator {
	257	compatible = "fixed-clock";
	258	#clock-cells = <0>;
	259	clock-frequency = <25000000>;
	260	};
	261	};
	262	};
	263
	264	&i2c0 {
	265	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	266	reg = <0x11000 0x100>;
	267	};
	268
	269	&i2c1 {
	270	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	271	reg = <0x11100 0x100>;
	272	};
	273
	274	&mpic {
	275	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	276	};
	277
3bef2ac4 CP	278	&rtc {
	279	status = "disabled";
	280	};
	281
43e28ba8 CP	282	&timer {
	283	compatible = "marvell,armada-xp-timer";
	284	clocks = <&coreclk 2>, <&refclk>;
	285	clock-names = "nbclk", "fixed";
	286	};
	287
	288	&watchdog {
	289	compatible = "marvell,armada-xp-wdt";
	290	clocks = <&coreclk 2>, <&refclk>;
	291	clock-names = "nbclk", "fixed";
	292	};
	293
	294	&cpurst {
	295	reg = <0x20800 0x20>;
	296	};
	297
	298	&usb0 {
	299	clocks = <&gateclk 18>;
	300	};
	301
	302	&usb1 {
	303	clocks = <&gateclk 19>;
3f81df55 CP	304	};
	305
	306	&pinctrl {
	307	compatible = "marvell,98dx3236-pinctrl";
	308
163043ab CP	309	nand_pins: nand-pins {
	310	marvell,pins = "mpp20", "mpp21", "mpp22",
	311	"mpp23", "mpp24", "mpp25",
	312	"mpp26", "mpp27", "mpp28",
	313	"mpp29", "mpp30";
	314	marvell,function = "dev";
	315	};
	316
	317	nand_rb: nand-rb {
	318	marvell,pins = "mpp19";
	319	marvell,function = "nand";
	320	};
	321
3f81df55 CP	322	spi0_pins: spi0-pins {
	323	marvell,pins = "mpp0", "mpp1",
	324	"mpp2", "mpp3";
	325	marvell,function = "spi0";
	326	};
	327	};
	328
43e28ba8 CP	329	&spi0 {
	330	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	331	pinctrl-0 = <&spi0_pins>;
	332	pinctrl-names = "default";
3f81df55 CP	333	};
3f81df55 CP	334
43e28ba8	335	&sdio {
3f81df55 CP	336	status = "disabled";
	337	};
	338