[linux-2.6-block.git] / arch / arm / boot / dts / armada-38x.dtsi

/*
 * Device Tree Include file for Marvell Armada 38x family of SoCs.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 38x family SoC";
	compatible = "marvell,armada380";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
		ethernet2 = &eth2;
	};

	soc {
		compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
			     "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl@18000 {
				reg = <0x18000 0x20>;

				ge0_rgmii_pins: ge-rgmii-pins-0 {
					marvell,pins = "mpp6", "mpp7", "mpp8",
						       "mpp9", "mpp10", "mpp11",
						       "mpp12", "mpp13", "mpp14",
						       "mpp15", "mpp16", "mpp17";
					marvell,function = "ge0";
				};

				i2c0_pins: i2c-pins-0 {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				mdio_pins: mdio-pins {
					marvell,pins = "mpp4", "mpp5";
					marvell,function = "ge";
				};

				ref_clk0_pins: ref-clk-pins-0 {
					marvell,pins = "mpp45";
					marvell,function = "ref";
				};

				spi1_pins: spi-pins-1 {
					marvell,pins = "mpp56", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "spi1";
				};

				uart0_pins: uart-pins-0 {
					marvell,pins = "mpp0", "mpp1";
					marvell,function = "ua0";
				};

				uart1_pins: uart-pins-1 {
					marvell,pins = "mpp19", "mpp20";
					marvell,function = "ua1";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <28>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-380-system-controller",
					     "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-380-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18600 {
				compatible = "marvell,armada-380-core-clock";
				reg = <0x18600 0x04>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-380-timer",
					     "marvell,armada-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-380-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			mpcore-soc-ctrl@20d20 {
				compatible = "marvell,armada-380-mpcore-soc-ctrl";
				reg = <0x20d20 0x6c>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-380-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			pmsu@22000 {
				compatible = "marvell,armada-380-pmsu";
				reg = <0x22000 0x1000>;
			};

			eth1: ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x4000>;
				interrupts-extended = <&mpic 10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			eth2: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts-extended = <&mpic 12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x58000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts-extended = <&mpic 8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			sata@a8000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xa8000 0x2000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 15>;
				status = "disabled";
			};

			sata@e0000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>;
				status = "disabled";
			};

			coredivclk: clock@e4250 {
				compatible = "marvell,armada-380-corediv-clock";
				reg = <0xe4250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			thermal@e8078 {
				compatible = "marvell,armada380-thermal";
				reg = <0xe4078 0x4>, <0xe4074 0x4>;
				status = "okay";
			};

			flash@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdhci@d8000 {
				compatible = "marvell,armada-380-sdhci";
				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
				interrupts = <0 25 0x4>;
				clocks = <&gateclk 17>;
				mrvl,clk-delay-cycles = <0x1F>;
				status = "disabled";
			};

			usb3@f0000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			usb3@f8000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};

		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};
Commit	Line	Data
0d3d96ab TP	1	/*
	2	* Device Tree Include file for Marvell Armada 38x family of SoCs.
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include "skeleton.dtsi"
f327d43d	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	17	#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab TP	18
	19	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	20
	21	/ {
	22	model = "Marvell Armada 38x family SoC";
8dbdb8e7	23	compatible = "marvell,armada380";
0d3d96ab TP	24
	25	aliases {
	26	gpio0 = &gpio0;
	27	gpio1 = &gpio1;
ad6a1b44 MW	28	ethernet0 = &eth0;
	29	ethernet1 = &eth1;
	30	ethernet2 = &eth2;
0d3d96ab TP	31	};
	32
	33	soc {
	34	compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
	35	"simple-bus";
	36	#address-cells = <2>;
	37	#size-cells = <1>;
	38	controller = <&mbusc>;
	39	interrupt-parent = <&gic>;
	40	pcie-mem-aperture = <0xe0000000 0x8000000>;
	41	pcie-io-aperture = <0xe8000000 0x100000>;
	42
	43	bootrom {
	44	compatible = "marvell,bootrom";
	45	reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
	46	};
	47
	48	devbus-bootcs {
	49	compatible = "marvell,mvebu-devbus";
	50	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	51	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	52	#address-cells = <1>;
	53	#size-cells = <1>;
	54	clocks = <&coreclk 0>;
	55	status = "disabled";
	56	};
	57
	58	devbus-cs0 {
	59	compatible = "marvell,mvebu-devbus";
	60	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	61	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	clocks = <&coreclk 0>;
	65	status = "disabled";
	66	};
	67
	68	devbus-cs1 {
	69	compatible = "marvell,mvebu-devbus";
	70	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	71	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	72	#address-cells = <1>;
	73	#size-cells = <1>;
	74	clocks = <&coreclk 0>;
	75	status = "disabled";
	76	};
	77
	78	devbus-cs2 {
	79	compatible = "marvell,mvebu-devbus";
	80	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	81	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	82	#address-cells = <1>;
	83	#size-cells = <1>;
	84	clocks = <&coreclk 0>;
	85	status = "disabled";
	86	};
	87
	88	devbus-cs3 {
	89	compatible = "marvell,mvebu-devbus";
	90	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	91	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	clocks = <&coreclk 0>;
95	status = "disabled";
96	};
97
98	internal-regs {
99	compatible = "simple-bus";
100	#address-cells = <1>;
101	#size-cells = <1>;
102	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103
104	L2: cache-controller@8000 {
105	compatible = "arm,pl310-cache";
106	reg = <0x8000 0x1000>;
107	cache-unified;
108	cache-level = <2>;
109	};
110
964a6156 TP	111	scu@c000 {
	112	compatible = "arm,cortex-a9-scu";
	113	reg = <0xc000 0x58>;
	114	};
	115
0d3d96ab TP	116	timer@c600 {
	117	compatible = "arm,cortex-a9-twd-timer";
	118	reg = <0xc600 0x20>;
d11548e3	119	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab TP	120	clocks = <&coreclk 2>;
	121	};
	122
	123	gic: interrupt-controller@d000 {
	124	compatible = "arm,cortex-a9-gic";
	125	#interrupt-cells = <3>;
	126	#size-cells = <0>;
	127	interrupt-controller;
	128	reg = <0xd000 0x1000>,
	129	<0xc100 0x100>;
	130	};
	131
	132	spi0: spi@10600 {
	133	compatible = "marvell,orion-spi";
	134	reg = <0x10600 0x50>;
	135	#address-cells = <1>;
	136	#size-cells = <0>;
	137	cell-index = <0>;
d11548e3	138	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	139	clocks = <&coreclk 0>;
	140	status = "disabled";
	141	};
	142
	143	spi1: spi@10680 {
	144	compatible = "marvell,orion-spi";
	145	reg = <0x10680 0x50>;
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148	cell-index = <1>;
d11548e3	149	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	150	clocks = <&coreclk 0>;
	151	status = "disabled";
	152	};
	153
	154	i2c0: i2c@11000 {
	155	compatible = "marvell,mv64xxx-i2c";
	156	reg = <0x11000 0x20>;
	157	#address-cells = <1>;
	158	#size-cells = <0>;
d11548e3	159	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	160	timeout-ms = <1000>;
	161	clocks = <&coreclk 0>;
	162	status = "disabled";
	163	};
	164
	165	i2c1: i2c@11100 {
	166	compatible = "marvell,mv64xxx-i2c";
	167	reg = <0x11100 0x20>;
	168	#address-cells = <1>;
	169	#size-cells = <0>;
d11548e3	170	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	171	timeout-ms = <1000>;
	172	clocks = <&coreclk 0>;
	173	status = "disabled";
	174	};
	175
	176	serial@12000 {
	177	compatible = "snps,dw-apb-uart";
	178	reg = <0x12000 0x100>;
	179	reg-shift = <2>;
d11548e3	180	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	181	reg-io-width = <1>;
64939dc5	182	clocks = <&coreclk 0>;
0d3d96ab TP	183	status = "disabled";
	184	};
	185
	186	serial@12100 {
	187	compatible = "snps,dw-apb-uart";
	188	reg = <0x12100 0x100>;
	189	reg-shift = <2>;
d11548e3	190	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	191	reg-io-width = <1>;
64939dc5	192	clocks = <&coreclk 0>;
0d3d96ab TP	193	status = "disabled";
	194	};
	195
4a25432b	196	pinctrl@18000 {
0d3d96ab	197	reg = <0x18000 0x20>;
91b4c91f MR	198
	199	ge0_rgmii_pins: ge-rgmii-pins-0 {
	200	marvell,pins = "mpp6", "mpp7", "mpp8",
	201	"mpp9", "mpp10", "mpp11",
	202	"mpp12", "mpp13", "mpp14",
	203	"mpp15", "mpp16", "mpp17";
	204	marvell,function = "ge0";
	205	};
	206
	207	i2c0_pins: i2c-pins-0 {
	208	marvell,pins = "mpp2", "mpp3";
	209	marvell,function = "i2c0";
	210	};
	211
	212	mdio_pins: mdio-pins {
	213	marvell,pins = "mpp4", "mpp5";
	214	marvell,function = "ge";
	215	};
	216
	217	ref_clk0_pins: ref-clk-pins-0 {
	218	marvell,pins = "mpp45";
	219	marvell,function = "ref";
	220	};
	221
	222	spi1_pins: spi-pins-1 {
	223	marvell,pins = "mpp56", "mpp57", "mpp58",
	224	"mpp59";
	225	marvell,function = "spi1";
	226	};
	227
	228	uart0_pins: uart-pins-0 {
	229	marvell,pins = "mpp0", "mpp1";
	230	marvell,function = "ua0";
	231	};
	232
	233	uart1_pins: uart-pins-1 {
	234	marvell,pins = "mpp19", "mpp20";
	235	marvell,function = "ua1";
	236	};
0d3d96ab TP	237	};
	238
	239	gpio0: gpio@18100 {
	240	compatible = "marvell,orion-gpio";
	241	reg = <0x18100 0x40>;
	242	ngpios = <32>;
	243	gpio-controller;
	244	#gpio-cells = <2>;
	245	interrupt-controller;
	246	#interrupt-cells = <2>;
d11548e3 TP	247	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	248	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	251	};
	252
	253	gpio1: gpio@18140 {
	254	compatible = "marvell,orion-gpio";
	255	reg = <0x18140 0x40>;
	256	ngpios = <28>;
	257	gpio-controller;
	258	#gpio-cells = <2>;
	259	interrupt-controller;
	260	#interrupt-cells = <2>;
d11548e3 TP	261	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	262	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	263	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	264	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	265	};
	266
	267	system-controller@18200 {
	268	compatible = "marvell,armada-380-system-controller",
	269	"marvell,armada-370-xp-system-controller";
	270	reg = <0x18200 0x100>;
	271	};
	272
	273	gateclk: clock-gating-control@18220 {
	274	compatible = "marvell,armada-380-gating-clock";
	275	reg = <0x18220 0x4>;
	276	clocks = <&coreclk 0>;
	277	#clock-cells = <1>;
	278	};
	279
	280	coreclk: mvebu-sar@18600 {
	281	compatible = "marvell,armada-380-core-clock";
	282	reg = <0x18600 0x04>;
	283	#clock-cells = <1>;
	284	};
	285
	286	mbusc: mbus-controller@20000 {
	287	compatible = "marvell,mbus-controller";
	288	reg = <0x20000 0x100>, <0x20180 0x20>;
	289	};
	290
	291	mpic: interrupt-controller@20000 {
	292	compatible = "marvell,mpic";
	293	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	294	#interrupt-cells = <1>;
	295	#size-cells = <1>;
	296	interrupt-controller;
	297	msi-controller;
d11548e3	298	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	299	};
	300
	301	timer@20300 {
	302	compatible = "marvell,armada-380-timer",
	303	"marvell,armada-xp-timer";
	304	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	305	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	306	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	307	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	308	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab TP	309	<&mpic 5>,
	310	<&mpic 6>;
	311	clocks = <&coreclk 2>, <&refclk>;
	312	clock-names = "nbclk", "fixed";
	313	};
	314
153a964a EG	315	watchdog@20300 {
	316	compatible = "marvell,armada-380-wdt";
	317	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
	318	clocks = <&coreclk 2>, <&refclk>;
	319	clock-names = "nbclk", "fixed";
	320	};
	321
19b06d7f TP	322	cpurst@20800 {
	323	compatible = "marvell,armada-370-cpu-reset";
	324	reg = <0x20800 0x10>;
	325	};
	326
d7f3ec2b GC	327	mpcore-soc-ctrl@20d20 {
	328	compatible = "marvell,armada-380-mpcore-soc-ctrl";
	329	reg = <0x20d20 0x6c>;
	330	};
	331
964a6156 TP	332	coherency-fabric@21010 {
	333	compatible = "marvell,armada-380-coherency-fabric";
	334	reg = <0x21010 0x1c>;
	335	};
	336
19b06d7f TP	337	pmsu@22000 {
	338	compatible = "marvell,armada-380-pmsu";
	339	reg = <0x22000 0x1000>;
	340	};
	341
0d3d96ab TP	342	eth1: ethernet@30000 {
	343	compatible = "marvell,armada-370-neta";
	344	reg = <0x30000 0x4000>;
	345	interrupts-extended = <&mpic 10>;
	346	clocks = <&gateclk 3>;
	347	status = "disabled";
	348	};
	349
	350	eth2: ethernet@34000 {
	351	compatible = "marvell,armada-370-neta";
	352	reg = <0x34000 0x4000>;
	353	interrupts-extended = <&mpic 12>;
	354	clocks = <&gateclk 2>;
	355	status = "disabled";
	356	};
	357
9e81775a GC	358	usb@50000 {
	359	compatible = "marvell,orion-ehci";
	360	reg = <0x58000 0x500>;
	361	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	362	clocks = <&gateclk 18>;
	363	status = "disabled";
	364	};
	365
0d3d96ab TP	366	xor@60800 {
	367	compatible = "marvell,orion-xor";
	368	reg = <0x60800 0x100
	369	0x60a00 0x100>;
	370	clocks = <&gateclk 22>;
	371	status = "okay";
	372
	373	xor00 {
d11548e3	374	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	375	dmacap,memcpy;
	376	dmacap,xor;
	377	};
	378	xor01 {
d11548e3	379	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	380	dmacap,memcpy;
	381	dmacap,xor;
	382	dmacap,memset;
	383	};
	384	};
	385
	386	xor@60900 {
	387	compatible = "marvell,orion-xor";
	388	reg = <0x60900 0x100
	389	0x60b00 0x100>;
	390	clocks = <&gateclk 28>;
	391	status = "okay";
	392
	393	xor10 {
d11548e3	394	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	395	dmacap,memcpy;
	396	dmacap,xor;
	397	};
	398	xor11 {
d11548e3	399	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	400	dmacap,memcpy;
	401	dmacap,xor;
	402	dmacap,memset;
	403	};
	404	};
	405
	406	eth0: ethernet@70000 {
	407	compatible = "marvell,armada-370-neta";
	408	reg = <0x70000 0x4000>;
	409	interrupts-extended = <&mpic 8>;
	410	clocks = <&gateclk 4>;
	411	status = "disabled";
	412	};
	413
4a25432b	414	mdio@72004 {
0d3d96ab TP	415	#address-cells = <1>;
	416	#size-cells = <0>;
	417	compatible = "marvell,orion-mdio";
	418	reg = <0x72004 0x4>;
33faf20b	419	clocks = <&gateclk 4>;
0d3d96ab	420	};
d6bd4b4c	421
d175b6e4 TP	422	sata@a8000 {
	423	compatible = "marvell,armada-380-ahci";
	424	reg = <0xa8000 0x2000>;
	425	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	426	clocks = <&gateclk 15>;
	427	status = "disabled";
	428	};
	429
	430	sata@e0000 {
	431	compatible = "marvell,armada-380-ahci";
	432	reg = <0xe0000 0x2000>;
	433	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	434	clocks = <&gateclk 30>;
	435	status = "disabled";
	436	};
	437
d6bd4b4c EG	438	coredivclk: clock@e4250 {
	439	compatible = "marvell,armada-380-corediv-clock";
	440	reg = <0xe4250 0xc>;
	441	#clock-cells = <1>;
	442	clocks = <&mainpll>;
	443	clock-output-names = "nand";
	444	};
93b5577e	445
c630829a EG	446	thermal@e8078 {
	447	compatible = "marvell,armada380-thermal";
	448	reg = <0xe4078 0x4>, <0xe4074 0x4>;
	449	status = "okay";
	450	};
	451
93b5577e EG	452	flash@d0000 {
	453	compatible = "marvell,armada370-nand";
	454	reg = <0xd0000 0x54>;
	455	#address-cells = <1>;
	456	#size-cells = <1>;
	457	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	458	clocks = <&coredivclk 0>;
	459	status = "disabled";
	460	};
6eccc52b TP	461
	462	sdhci@d8000 {
	463	compatible = "marvell,armada-380-sdhci";
	464	reg = <0xd8000 0x1000>, <0xdc000 0x100>;
	465	interrupts = <0 25 0x4>;
	466	clocks = <&gateclk 17>;
	467	mrvl,clk-delay-cycles = <0x1F>;
	468	status = "disabled";
	469	};
87e2fc37 GC	470
	471	usb3@f0000 {
	472	compatible = "marvell,armada-380-xhci";
	473	reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
	474	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	475	clocks = <&gateclk 9>;
	476	status = "disabled";
	477	};
	478
	479	usb3@f8000 {
	480	compatible = "marvell,armada-380-xhci";
	481	reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
	482	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	483	clocks = <&gateclk 10>;
	484	status = "disabled";
	485	};
0d3d96ab TP	486	};
	487	};
	488
	489	clocks {
5bc94c99 EG	490	/* 2 GHz fixed main PLL */
	491	mainpll: mainpll {
	492	compatible = "fixed-clock";
	493	#clock-cells = <0>;
	494	clock-frequency = <2000000000>;
	495	};
	496
0d3d96ab TP	497	/* 25 MHz reference crystal */
	498	refclk: oscillator {
	499	compatible = "fixed-clock";
	500	#clock-cells = <0>;
	501	clock-frequency = <25000000>;
	502	};
	503	};
	504	};