[linux-2.6-block.git] / arch / arm / boot / dts / armada-38x.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 38x family of SoCs.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Marvell Armada 38x family SoC";
	compatible = "marvell,armada380";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada380-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
		};

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <0>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <0>;
				prefetch-data = <1>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c200 {
				compatible = "arm,cortex-a9-global-timer";
				reg = <0xc200 0x20>;
				interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "marvell,armada-38x-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "marvell,armada-38x-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pinctrl@18000 {
				reg = <0x18000 0x20>;

				ge0_rgmii_pins: ge-rgmii-pins-0 {
					marvell,pins = "mpp6", "mpp7", "mpp8",
						       "mpp9", "mpp10", "mpp11",
						       "mpp12", "mpp13", "mpp14",
						       "mpp15", "mpp16", "mpp17";
					marvell,function = "ge0";
				};

				ge1_rgmii_pins: ge-rgmii-pins-1 {
					marvell,pins = "mpp21", "mpp27", "mpp28",
						       "mpp29", "mpp30", "mpp31",
						       "mpp32", "mpp37", "mpp38",
						       "mpp39", "mpp40", "mpp41";
					marvell,function = "ge1";
				};

				i2c0_pins: i2c-pins-0 {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				mdio_pins: mdio-pins {
					marvell,pins = "mpp4", "mpp5";
					marvell,function = "ge";
				};

				ref_clk0_pins: ref-clk-pins-0 {
					marvell,pins = "mpp45";
					marvell,function = "ref";
				};

				ref_clk1_pins: ref-clk-pins-1 {
					marvell,pins = "mpp46";
					marvell,function = "ref";
				};

				spi0_pins: spi-pins-0 {
					marvell,pins = "mpp22", "mpp23", "mpp24",
						       "mpp25";
					marvell,function = "spi0";
				};

				spi1_pins: spi-pins-1 {
					marvell,pins = "mpp56", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "spi1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp22", "mpp34", "mpp23",
						       "mpp33", "mpp38", "mpp28",
						       "mpp40", "mpp42", "mpp35",
						       "mpp36", "mpp25", "mpp30",
						       "mpp32";
					marvell,function = "dev";
				};

				nand_rb: nand-rb {
					marvell,pins = "mpp41";
					marvell,function = "nand";
				};

				uart0_pins: uart-pins-0 {
					marvell,pins = "mpp0", "mpp1";
					marvell,function = "ua0";
				};

				uart1_pins: uart-pins-1 {
					marvell,pins = "mpp19", "mpp20";
					marvell,function = "ua1";
				};

				sdhci_pins: sdhci-pins {
					marvell,pins = "mpp48", "mpp49", "mpp50",
						       "mpp52", "mpp53", "mpp54",
						       "mpp55", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "sd0";
				};

				sata0_pins: sata-pins-0 {
					marvell,pins = "mpp20";
					marvell,function = "sata0";
				};

				sata1_pins: sata-pins-1 {
					marvell,pins = "mpp19";
					marvell,function = "sata1";
				};

				sata2_pins: sata-pins-2 {
					marvell,pins = "mpp47";
					marvell,function = "sata2";
				};

				sata3_pins: sata-pins-3 {
					marvell,pins = "mpp44";
					marvell,function = "sata3";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <28>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-380-system-controller",
					     "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-380-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18600 {
				compatible = "marvell,armada-380-core-clock";
				reg = <0x18600 0x04>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer: timer@20300 {
				compatible = "marvell,armada-380-timer",
					     "marvell,armada-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog: watchdog@20300 {
				compatible = "marvell,armada-380-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			mpcore-soc-ctrl@20d20 {
				compatible = "marvell,armada-380-mpcore-soc-ctrl";
				reg = <0x20d20 0x6c>;
			};

			coherencyfab: coherency-fabric@21010 {
				compatible = "marvell,armada-380-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			pmsu: pmsu@22000 {
				compatible = "marvell,armada-380-pmsu";
				reg = <0x22000 0x1000>;
			};

			/*
			 * As a special exception to the "order by
			 * register address" rule, the eth0 node is
			 * placed here to ensure that it gets
			 * registered as the first interface, since
			 * the network subsystem doesn't allow naming
			 * interfaces using DT aliases. Without this,
			 * the ordering of interfaces is different
			 * from the one used in U-Boot and the
			 * labeling of interfaces on the boards, which
			 * is very confusing for users.
			 */
			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts-extended = <&mpic 8>;
				clocks = <&gateclk 4>;
				tx-csum-limit = <9800>;
				status = "disabled";
			};

			eth1: ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x4000>;
				interrupts-extended = <&mpic 10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			eth2: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts-extended = <&mpic 12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb0: usb@58000 {
				compatible = "marvell,orion-ehci";
				reg = <0x58000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			xor0: xor@60800 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor1: xor@60900 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			cesa: crypto@90000 {
				compatible = "marvell,armada-38x-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 23>, <&gateclk 21>,
					 <&gateclk 14>, <&gateclk 16>;
				clock-names = "cesa0", "cesa1",
					      "cesaz0", "cesaz1";
				marvell,crypto-srams = <&crypto_sram0>,
						       <&crypto_sram1>;
				marvell,crypto-sram-size = <0x800>;
			};

			rtc: rtc@a3800 {
				compatible = "marvell,armada-380-rtc";
				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			ahci0: sata@a8000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xa8000 0x2000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 15>;
				status = "disabled";
			};

			bm: bm@c8000 {
				compatible = "marvell,armada-380-neta-bm";
				reg = <0xc8000 0xac>;
				clocks = <&gateclk 13>;
				internal-mem = <&bm_bppi>;
				status = "disabled";
			};

			ahci1: sata@e0000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>;
				status = "disabled";
			};

			coredivclk: clock@e4250 {
				compatible = "marvell,armada-380-corediv-clock";
				reg = <0xe4250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			thermal: thermal@e8078 {
				compatible = "marvell,armada380-thermal";
				reg = <0xe4078 0x4>, <0xe4070 0x8>;
				status = "okay";
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdhci: sdhci@d8000 {
				compatible = "marvell,armada-380-sdhci";
				reg-names = "sdhci", "mbus", "conf-sdio3";
				reg = <0xd8000 0x1000>,
					<0xdc000 0x100>,
					<0x18454 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				mrvl,clk-delay-cycles = <0x1F>;
				status = "disabled";
			};

			usb3_0: usb3@f0000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			usb3_1: usb3@f8000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};
		};

		crypto_sram0: sa-sram0 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
			clocks = <&gateclk 21>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
		};

		bm_bppi: bm-bppi {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gateclk 13>;
			no-memory-wc;
			status = "disabled";
		};

		spi0: spi@10600 {
			compatible = "marvell,armada-380-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			compatible = "marvell,armada-380-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 1 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};

		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};
Commit	Line	Data
69f5689b	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0d3d96ab TP	2	/*
	3	* Device Tree Include file for Marvell Armada 38x family of SoCs.
	4	*
	5	* Copyright (C) 2014 Marvell
	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0d3d96ab TP	10	*/
0d3d96ab TP	11
f327d43d	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	13	#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab TP	14
	15	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	16
	17	/ {
abe60a3a RH	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20
0d3d96ab	21	model = "Marvell Armada 38x family SoC";
8dbdb8e7	22	compatible = "marvell,armada380";
0d3d96ab TP	23
	24	aliases {
	25	gpio0 = &gpio0;
	26	gpio1 = &gpio1;
bf6acf16 TP	27	serial0 = &uart0;
bf6acf16 TP	28	serial1 = &uart1;
0d3d96ab TP	29	};
0d3d96ab TP	30
754c4b1b EG	31	pmu {
	32	compatible = "arm,cortex-a9-pmu";
	33	interrupts-extended = <&mpic 3>;
	34	};
	35
0d3d96ab	36	soc {
a9e274c4	37	compatible = "marvell,armada380-mbus", "simple-bus";
0d3d96ab TP	38	#address-cells = <2>;
	39	#size-cells = <1>;
	40	controller = <&mbusc>;
	41	interrupt-parent = <&gic>;
	42	pcie-mem-aperture = <0xe0000000 0x8000000>;
	43	pcie-io-aperture = <0xe8000000 0x100000>;
	44
	45	bootrom {
	46	compatible = "marvell,bootrom";
	47	reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
	48	};
	49
a126de75	50	devbus_bootcs: devbus-bootcs {
0d3d96ab TP	51	compatible = "marvell,mvebu-devbus";
	52	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	53	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	clocks = <&coreclk 0>;
	57	status = "disabled";
	58	};
	59
a126de75	60	devbus_cs0: devbus-cs0 {
0d3d96ab TP	61	compatible = "marvell,mvebu-devbus";
	62	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	63	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	clocks = <&coreclk 0>;
	67	status = "disabled";
	68	};
	69
a126de75	70	devbus_cs1: devbus-cs1 {
0d3d96ab TP	71	compatible = "marvell,mvebu-devbus";
	72	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	73	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	clocks = <&coreclk 0>;
	77	status = "disabled";
	78	};
	79
a126de75	80	devbus_cs2: devbus-cs2 {
0d3d96ab TP	81	compatible = "marvell,mvebu-devbus";
	82	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	83	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	clocks = <&coreclk 0>;
	87	status = "disabled";
	88	};
	89
a126de75	90	devbus_cs3: devbus-cs3 {
0d3d96ab TP	91	compatible = "marvell,mvebu-devbus";
	92	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	93	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	clocks = <&coreclk 0>;
	97	status = "disabled";
	98	};
	99
	100	internal-regs {
	101	compatible = "simple-bus";
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
	105
	106	L2: cache-controller@8000 {
	107	compatible = "arm,pl310-cache";
	108	reg = <0x8000 0x1000>;
	109	cache-unified;
	110	cache-level = <2>;
cda80a82	111	arm,double-linefill-incr = <0>;
c8f5a878	112	arm,double-linefill-wrap = <0>;
cda80a82	113	arm,double-linefill = <0>;
c8f5a878	114	prefetch-data = <1>;
0d3d96ab TP	115	};
0d3d96ab TP	116
964a6156 TP	117	scu@c000 {
	118	compatible = "arm,cortex-a9-scu";
	119	reg = <0xc000 0x58>;
	120	};
	121
0f015017 MW	122	timer@c200 {
	123	compatible = "arm,cortex-a9-global-timer";
	124	reg = <0xc200 0x20>;
	125	interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
	126	clocks = <&coreclk 2>;
	127	};
	128
0d3d96ab TP	129	timer@c600 {
	130	compatible = "arm,cortex-a9-twd-timer";
	131	reg = <0xc600 0x20>;
d11548e3	132	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab TP	133	clocks = <&coreclk 2>;
	134	};
	135
	136	gic: interrupt-controller@d000 {
	137	compatible = "arm,cortex-a9-gic";
	138	#interrupt-cells = <3>;
	139	#size-cells = <0>;
	140	interrupt-controller;
	141	reg = <0xd000 0x1000>,
	142	<0xc100 0x100>;
	143	};
	144
0d3d96ab	145	i2c0: i2c@11000 {
fbffee74	146	compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0d3d96ab TP	147	reg = <0x11000 0x20>;
	148	#address-cells = <1>;
	149	#size-cells = <0>;
d11548e3	150	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	151	timeout-ms = <1000>;
	152	clocks = <&coreclk 0>;
	153	status = "disabled";
	154	};
	155
	156	i2c1: i2c@11100 {
fbffee74	157	compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0d3d96ab TP	158	reg = <0x11100 0x20>;
	159	#address-cells = <1>;
	160	#size-cells = <0>;
d11548e3	161	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	162	timeout-ms = <1000>;
	163	clocks = <&coreclk 0>;
	164	status = "disabled";
	165	};
	166
10c5c472	167	uart0: serial@12000 {
b7639b0b	168	compatible = "marvell,armada-38x-uart";
0d3d96ab TP	169	reg = <0x12000 0x100>;
0d3d96ab TP	170	reg-shift = <2>;
d11548e3	171	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	172	reg-io-width = <1>;
64939dc5	173	clocks = <&coreclk 0>;
0d3d96ab TP	174	status = "disabled";
	175	};
	176
8a48dccb	177	uart1: serial@12100 {
b7639b0b	178	compatible = "marvell,armada-38x-uart";
0d3d96ab TP	179	reg = <0x12100 0x100>;
0d3d96ab TP	180	reg-shift = <2>;
d11548e3	181	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	182	reg-io-width = <1>;
64939dc5	183	clocks = <&coreclk 0>;
0d3d96ab TP	184	status = "disabled";
	185	};
	186
10c5c472	187	pinctrl: pinctrl@18000 {
0d3d96ab	188	reg = <0x18000 0x20>;
91b4c91f MR	189
	190	ge0_rgmii_pins: ge-rgmii-pins-0 {
	191	marvell,pins = "mpp6", "mpp7", "mpp8",
	192	"mpp9", "mpp10", "mpp11",
	193	"mpp12", "mpp13", "mpp14",
	194	"mpp15", "mpp16", "mpp17";
	195	marvell,function = "ge0";
	196	};
	197
34598503 GC	198	ge1_rgmii_pins: ge-rgmii-pins-1 {
	199	marvell,pins = "mpp21", "mpp27", "mpp28",
	200	"mpp29", "mpp30", "mpp31",
	201	"mpp32", "mpp37", "mpp38",
	202	"mpp39", "mpp40", "mpp41";
	203	marvell,function = "ge1";
	204	};
	205
91b4c91f MR	206	i2c0_pins: i2c-pins-0 {
	207	marvell,pins = "mpp2", "mpp3";
	208	marvell,function = "i2c0";
	209	};
	210
	211	mdio_pins: mdio-pins {
	212	marvell,pins = "mpp4", "mpp5";
	213	marvell,function = "ge";
	214	};
	215
	216	ref_clk0_pins: ref-clk-pins-0 {
	217	marvell,pins = "mpp45";
	218	marvell,function = "ref";
	219	};
	220
34598503 GC	221	ref_clk1_pins: ref-clk-pins-1 {
	222	marvell,pins = "mpp46";
	223	marvell,function = "ref";
	224	};
	225
	226	spi0_pins: spi-pins-0 {
	227	marvell,pins = "mpp22", "mpp23", "mpp24",
	228	"mpp25";
	229	marvell,function = "spi0";
	230	};
	231
91b4c91f MR	232	spi1_pins: spi-pins-1 {
	233	marvell,pins = "mpp56", "mpp57", "mpp58",
	234	"mpp59";
	235	marvell,function = "spi1";
	236	};
	237
4c0437d0 CP	238	nand_pins: nand-pins {
	239	marvell,pins = "mpp22", "mpp34", "mpp23",
	240	"mpp33", "mpp38", "mpp28",
	241	"mpp40", "mpp42", "mpp35",
	242	"mpp36", "mpp25", "mpp30",
	243	"mpp32";
	244	marvell,function = "dev";
	245	};
	246
ba369daa SN	247	nand_rb: nand-rb {
	248	marvell,pins = "mpp41";
	249	marvell,function = "nand";
	250	};
	251
91b4c91f MR	252	uart0_pins: uart-pins-0 {
	253	marvell,pins = "mpp0", "mpp1";
	254	marvell,function = "ua0";
	255	};
	256
	257	uart1_pins: uart-pins-1 {
	258	marvell,pins = "mpp19", "mpp20";
	259	marvell,function = "ua1";
	260	};
34598503 GC	261
	262	sdhci_pins: sdhci-pins {
	263	marvell,pins = "mpp48", "mpp49", "mpp50",
	264	"mpp52", "mpp53", "mpp54",
	265	"mpp55", "mpp57", "mpp58",
	266	"mpp59";
	267	marvell,function = "sd0";
	268	};
	269
	270	sata0_pins: sata-pins-0 {
	271	marvell,pins = "mpp20";
	272	marvell,function = "sata0";
	273	};
	274
	275	sata1_pins: sata-pins-1 {
	276	marvell,pins = "mpp19";
	277	marvell,function = "sata1";
	278	};
	279
	280	sata2_pins: sata-pins-2 {
	281	marvell,pins = "mpp47";
	282	marvell,function = "sata2";
	283	};
	284
	285	sata3_pins: sata-pins-3 {
	286	marvell,pins = "mpp44";
	287	marvell,function = "sata3";
	288	};
0d3d96ab TP	289	};
	290
	291	gpio0: gpio@18100 {
7cb2acb3 RS	292	compatible = "marvell,armada-370-gpio",
	293	"marvell,orion-gpio";
	294	reg = <0x18100 0x40>, <0x181c0 0x08>;
	295	reg-names = "gpio", "pwm";
0d3d96ab TP	296	ngpios = <32>;
	297	gpio-controller;
	298	#gpio-cells = <2>;
7cb2acb3	299	#pwm-cells = <2>;
0d3d96ab TP	300	interrupt-controller;
0d3d96ab TP	301	#interrupt-cells = <2>;
d11548e3 TP	302	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	303	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	304	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	305	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
7cb2acb3	306	clocks = <&coreclk 0>;
0d3d96ab TP	307	};
	308
	309	gpio1: gpio@18140 {
7cb2acb3 RS	310	compatible = "marvell,armada-370-gpio",
	311	"marvell,orion-gpio";
	312	reg = <0x18140 0x40>, <0x181c8 0x08>;
	313	reg-names = "gpio", "pwm";
0d3d96ab TP	314	ngpios = <28>;
	315	gpio-controller;
	316	#gpio-cells = <2>;
7cb2acb3	317	#pwm-cells = <2>;
0d3d96ab TP	318	interrupt-controller;
0d3d96ab TP	319	#interrupt-cells = <2>;
d11548e3 TP	320	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	321	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	322	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
7cb2acb3	324	clocks = <&coreclk 0>;
0d3d96ab TP	325	};
0d3d96ab TP	326
a126de75	327	systemc: system-controller@18200 {
0d3d96ab TP	328	compatible = "marvell,armada-380-system-controller",
	329	"marvell,armada-370-xp-system-controller";
	330	reg = <0x18200 0x100>;
	331	};
	332
	333	gateclk: clock-gating-control@18220 {
	334	compatible = "marvell,armada-380-gating-clock";
	335	reg = <0x18220 0x4>;
	336	clocks = <&coreclk 0>;
	337	#clock-cells = <1>;
	338	};
	339
	340	coreclk: mvebu-sar@18600 {
	341	compatible = "marvell,armada-380-core-clock";
	342	reg = <0x18600 0x04>;
	343	#clock-cells = <1>;
	344	};
	345
	346	mbusc: mbus-controller@20000 {
	347	compatible = "marvell,mbus-controller";
b69f4697 GC	348	reg = <0x20000 0x100>, <0x20180 0x20>,
b69f4697 GC	349	<0x20250 0x8>;
0d3d96ab TP	350	};
0d3d96ab TP	351
1d7b0839	352	mpic: interrupt-controller@20a00 {
0d3d96ab TP	353	compatible = "marvell,mpic";
	354	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	355	#interrupt-cells = <1>;
	356	#size-cells = <1>;
	357	interrupt-controller;
	358	msi-controller;
d11548e3	359	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	360	};
0d3d96ab TP	361
a126de75	362	timer: timer@20300 {
0d3d96ab TP	363	compatible = "marvell,armada-380-timer",
	364	"marvell,armada-xp-timer";
	365	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	366	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	367	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	368	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	369	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab TP	370	<&mpic 5>,
	371	<&mpic 6>;
	372	clocks = <&coreclk 2>, <&refclk>;
	373	clock-names = "nbclk", "fixed";
	374	};
	375
a126de75	376	watchdog: watchdog@20300 {
153a964a EG	377	compatible = "marvell,armada-380-wdt";
	378	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
	379	clocks = <&coreclk 2>, <&refclk>;
	380	clock-names = "nbclk", "fixed";
	381	};
	382
a126de75	383	cpurst: cpurst@20800 {
19b06d7f TP	384	compatible = "marvell,armada-370-cpu-reset";
	385	reg = <0x20800 0x10>;
	386	};
	387
d7f3ec2b GC	388	mpcore-soc-ctrl@20d20 {
	389	compatible = "marvell,armada-380-mpcore-soc-ctrl";
	390	reg = <0x20d20 0x6c>;
	391	};
	392
a126de75	393	coherencyfab: coherency-fabric@21010 {
964a6156 TP	394	compatible = "marvell,armada-380-coherency-fabric";
	395	reg = <0x21010 0x1c>;
	396	};
	397
a126de75	398	pmsu: pmsu@22000 {
19b06d7f TP	399	compatible = "marvell,armada-380-pmsu";
	400	reg = <0x22000 0x1000>;
	401	};
	402
cb4f71c4 TP	403	/*
	404	* As a special exception to the "order by
	405	* register address" rule, the eth0 node is
	406	* placed here to ensure that it gets
	407	* registered as the first interface, since
	408	* the network subsystem doesn't allow naming
	409	* interfaces using DT aliases. Without this,
	410	* the ordering of interfaces is different
	411	* from the one used in U-Boot and the
	412	* labeling of interfaces on the boards, which
	413	* is very confusing for users.
	414	*/
	415	eth0: ethernet@70000 {
	416	compatible = "marvell,armada-370-neta";
	417	reg = <0x70000 0x4000>;
	418	interrupts-extended = <&mpic 8>;
	419	clocks = <&gateclk 4>;
	420	tx-csum-limit = <9800>;
	421	status = "disabled";
	422	};
	423
0d3d96ab TP	424	eth1: ethernet@30000 {
	425	compatible = "marvell,armada-370-neta";
	426	reg = <0x30000 0x4000>;
	427	interrupts-extended = <&mpic 10>;
	428	clocks = <&gateclk 3>;
	429	status = "disabled";
	430	};
	431
	432	eth2: ethernet@34000 {
	433	compatible = "marvell,armada-370-neta";
	434	reg = <0x34000 0x4000>;
	435	interrupts-extended = <&mpic 12>;
	436	clocks = <&gateclk 2>;
	437	status = "disabled";
	438	};
	439
a126de75	440	usb0: usb@58000 {
9e81775a GC	441	compatible = "marvell,orion-ehci";
	442	reg = <0x58000 0x500>;
	443	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	444	clocks = <&gateclk 18>;
	445	status = "disabled";
	446	};
	447
a126de75	448	xor0: xor@60800 {
449e1d64	449	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	450	reg = <0x60800 0x100
	451	0x60a00 0x100>;
	452	clocks = <&gateclk 22>;
	453	status = "okay";
	454
	455	xor00 {
d11548e3	456	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	457	dmacap,memcpy;
	458	dmacap,xor;
	459	};
	460	xor01 {
d11548e3	461	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	462	dmacap,memcpy;
	463	dmacap,xor;
	464	dmacap,memset;
	465	};
	466	};
	467
a126de75	468	xor1: xor@60900 {
449e1d64	469	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	470	reg = <0x60900 0x100
	471	0x60b00 0x100>;
	472	clocks = <&gateclk 28>;
	473	status = "okay";
	474
	475	xor10 {
d11548e3	476	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	477	dmacap,memcpy;
	478	dmacap,xor;
	479	};
	480	xor11 {
d11548e3	481	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	482	dmacap,memcpy;
	483	dmacap,xor;
	484	dmacap,memset;
	485	};
	486	};
	487
973ed083	488	mdio: mdio@72004 {
0d3d96ab TP	489	#address-cells = <1>;
	490	#size-cells = <0>;
	491	compatible = "marvell,orion-mdio";
	492	reg = <0x72004 0x4>;
33faf20b	493	clocks = <&gateclk 4>;
0d3d96ab	494	};
d6bd4b4c	495
a126de75	496	cesa: crypto@90000 {
35c99ec9 BB	497	compatible = "marvell,armada-38x-crypto";
	498	reg = <0x90000 0x10000>;
	499	reg-names = "regs";
	500	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	501	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	502	clocks = <&gateclk 23>, <&gateclk 21>,
	503	<&gateclk 14>, <&gateclk 16>;
	504	clock-names = "cesa0", "cesa1",
	505	"cesaz0", "cesaz1";
	506	marvell,crypto-srams = <&crypto_sram0>,
	507	<&crypto_sram1>;
	508	marvell,crypto-sram-size = <0x800>;
	509	};
	510
a126de75	511	rtc: rtc@a3800 {
a73c7305 GC	512	compatible = "marvell,armada-380-rtc";
	513	reg = <0xa3800 0x20>, <0x184a0 0x0c>;
	514	reg-names = "rtc", "rtc-soc";
	515	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	516	};
	517
f3d1f759	518	ahci0: sata@a8000 {
d175b6e4 TP	519	compatible = "marvell,armada-380-ahci";
	520	reg = <0xa8000 0x2000>;
	521	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	522	clocks = <&gateclk 15>;
	523	status = "disabled";
	524	};
	525
4a547a5a MW	526	bm: bm@c8000 {
	527	compatible = "marvell,armada-380-neta-bm";
	528	reg = <0xc8000 0xac>;
	529	clocks = <&gateclk 13>;
	530	internal-mem = <&bm_bppi>;
	531	status = "disabled";
	532	};
	533
f3d1f759	534	ahci1: sata@e0000 {
d175b6e4 TP	535	compatible = "marvell,armada-380-ahci";
	536	reg = <0xe0000 0x2000>;
	537	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	538	clocks = <&gateclk 30>;
	539	status = "disabled";
	540	};
	541
d6bd4b4c EG	542	coredivclk: clock@e4250 {
	543	compatible = "marvell,armada-380-corediv-clock";
	544	reg = <0xe4250 0xc>;
	545	#clock-cells = <1>;
	546	clocks = <&mainpll>;
	547	clock-output-names = "nand";
	548	};
93b5577e	549
a126de75	550	thermal: thermal@e8078 {
c630829a	551	compatible = "marvell,armada380-thermal";
568cc2f0	552	reg = <0xe4078 0x4>, <0xe4070 0x8>;
c630829a EG	553	status = "okay";
	554	};
	555
925d5e42 MR	556	nand_controller: nand-controller@d0000 {
925d5e42 MR	557	compatible = "marvell,armada370-nand-controller";
93b5577e EG	558	reg = <0xd0000 0x54>;
93b5577e EG	559	#address-cells = <1>;
925d5e42	560	#size-cells = <0>;
93b5577e EG	561	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	562	clocks = <&coredivclk 0>;
	563	status = "disabled";
	564	};
6eccc52b	565
a126de75	566	sdhci: sdhci@d8000 {
6eccc52b	567	compatible = "marvell,armada-380-sdhci";
ddbdc579 GC	568	reg-names = "sdhci", "mbus", "conf-sdio3";
	569	reg = <0xd8000 0x1000>,
	570	<0xdc000 0x100>,
	571	<0x18454 0x4>;
b757258a	572	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6eccc52b TP	573	clocks = <&gateclk 17>;
	574	mrvl,clk-delay-cycles = <0x1F>;
	575	status = "disabled";
	576	};
87e2fc37	577
f3d1f759	578	usb3_0: usb3@f0000 {
87e2fc37 GC	579	compatible = "marvell,armada-380-xhci";
	580	reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
	581	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	582	clocks = <&gateclk 9>;
	583	status = "disabled";
	584	};
	585
f3d1f759	586	usb3_1: usb3@f8000 {
87e2fc37 GC	587	compatible = "marvell,armada-380-xhci";
	588	reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
	589	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	590	clocks = <&gateclk 10>;
	591	status = "disabled";
	592	};
0d3d96ab	593	};
35c99ec9 BB	594
	595	crypto_sram0: sa-sram0 {
	596	compatible = "mmio-sram";
	597	reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
	598	clocks = <&gateclk 23>;
	599	#address-cells = <1>;
	600	#size-cells = <1>;
	601	ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
	602	};
	603
	604	crypto_sram1: sa-sram1 {
	605	compatible = "mmio-sram";
	606	reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
	607	clocks = <&gateclk 21>;
	608	#address-cells = <1>;
	609	#size-cells = <1>;
	610	ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
	611	};
4a547a5a MW	612
	613	bm_bppi: bm-bppi {
	614	compatible = "mmio-sram";
	615	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
	616	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
	617	#address-cells = <1>;
	618	#size-cells = <1>;
	619	clocks = <&gateclk 13>;
	620	no-memory-wc;
	621	status = "disabled";
	622	};
0160a4b6 SR	623
	624	spi0: spi@10600 {
	625	compatible = "marvell,armada-380-spi",
	626	"marvell,orion-spi";
	627	reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
	628	#address-cells = <1>;
	629	#size-cells = <0>;
	630	cell-index = <0>;
	631	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	632	clocks = <&coreclk 0>;
	633	status = "disabled";
	634	};
	635
	636	spi1: spi@10680 {
	637	compatible = "marvell,armada-380-spi",
	638	"marvell,orion-spi";
	639	reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
	640	#address-cells = <1>;
	641	#size-cells = <0>;
	642	cell-index = <1>;
	643	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	644	clocks = <&coreclk 0>;
	645	status = "disabled";
	646	};
0d3d96ab TP	647	};
	648
	649	clocks {
ad0de58b	650	/* 1 GHz fixed main PLL */
5bc94c99 EG	651	mainpll: mainpll {
	652	compatible = "fixed-clock";
	653	#clock-cells = <0>;
ae142bd9	654	clock-frequency = <1000000000>;
5bc94c99 EG	655	};
5bc94c99 EG	656
0d3d96ab TP	657	/* 25 MHz reference crystal */
	658	refclk: oscillator {
	659	compatible = "fixed-clock";
	660	#clock-cells = <0>;
	661	clock-frequency = <25000000>;
	662	};
	663	};
	664	};