[linux-2.6-block.git] / arch / arm / boot / dts / armada-38x.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 38x family of SoCs.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Marvell Armada 38x family SoC";
	compatible = "marvell,armada380";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada380-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
		};

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			sdramc: sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <0>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <0>;
				prefetch-data = <1>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c200 {
				compatible = "arm,cortex-a9-global-timer";
				reg = <0xc200 0x20>;
				interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "marvell,armada-38x-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "marvell,armada-38x-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pinctrl@18000 {
				reg = <0x18000 0x20>;

				ge0_rgmii_pins: ge-rgmii-pins-0 {
					marvell,pins = "mpp6", "mpp7", "mpp8",
						       "mpp9", "mpp10", "mpp11",
						       "mpp12", "mpp13", "mpp14",
						       "mpp15", "mpp16", "mpp17";
					marvell,function = "ge0";
				};

				ge1_rgmii_pins: ge-rgmii-pins-1 {
					marvell,pins = "mpp21", "mpp27", "mpp28",
						       "mpp29", "mpp30", "mpp31",
						       "mpp32", "mpp37", "mpp38",
						       "mpp39", "mpp40", "mpp41";
					marvell,function = "ge1";
				};

				i2c0_pins: i2c-pins-0 {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				mdio_pins: mdio-pins {
					marvell,pins = "mpp4", "mpp5";
					marvell,function = "ge";
				};

				ref_clk0_pins: ref-clk-pins-0 {
					marvell,pins = "mpp45";
					marvell,function = "ref";
				};

				ref_clk1_pins: ref-clk-pins-1 {
					marvell,pins = "mpp46";
					marvell,function = "ref";
				};

				spi0_pins: spi-pins-0 {
					marvell,pins = "mpp22", "mpp23", "mpp24",
						       "mpp25";
					marvell,function = "spi0";
				};

				spi1_pins: spi-pins-1 {
					marvell,pins = "mpp56", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "spi1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp22", "mpp34", "mpp23",
						       "mpp33", "mpp38", "mpp28",
						       "mpp40", "mpp42", "mpp35",
						       "mpp36", "mpp25", "mpp30",
						       "mpp32";
					marvell,function = "dev";
				};

				nand_rb: nand-rb {
					marvell,pins = "mpp41";
					marvell,function = "nand";
				};

				uart0_pins: uart-pins-0 {
					marvell,pins = "mpp0", "mpp1";
					marvell,function = "ua0";
				};

				uart1_pins: uart-pins-1 {
					marvell,pins = "mpp19", "mpp20";
					marvell,function = "ua1";
				};

				sdhci_pins: sdhci-pins {
					marvell,pins = "mpp48", "mpp49", "mpp50",
						       "mpp52", "mpp53", "mpp54",
						       "mpp55", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "sd0";
				};

				sata0_pins: sata-pins-0 {
					marvell,pins = "mpp20";
					marvell,function = "sata0";
				};

				sata1_pins: sata-pins-1 {
					marvell,pins = "mpp19";
					marvell,function = "sata1";
				};

				sata2_pins: sata-pins-2 {
					marvell,pins = "mpp47";
					marvell,function = "sata2";
				};

				sata3_pins: sata-pins-3 {
					marvell,pins = "mpp44";
					marvell,function = "sata3";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <28>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-380-system-controller",
					     "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-380-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			comphy: phy@18300 {
				compatible = "marvell,armada-380-comphy";
				reg = <0x18300 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;

				comphy0: phy@0 {
					reg = <0>;
					#phy-cells = <1>;
				};

				comphy1: phy@1 {
					reg = <1>;
					#phy-cells = <1>;
				};

				comphy2: phy@2 {
					reg = <2>;
					#phy-cells = <1>;
				};

				comphy3: phy@3 {
					reg = <3>;
					#phy-cells = <1>;
				};

				comphy4: phy@4 {
					reg = <4>;
					#phy-cells = <1>;
				};

				comphy5: phy@5 {
					reg = <5>;
					#phy-cells = <1>;
				};
			};

			coreclk: mvebu-sar@18600 {
				compatible = "marvell,armada-380-core-clock";
				reg = <0x18600 0x04>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer: timer@20300 {
				compatible = "marvell,armada-380-timer",
					     "marvell,armada-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog: watchdog@20300 {
				compatible = "marvell,armada-380-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
				interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			mpcore-soc-ctrl@20d20 {
				compatible = "marvell,armada-380-mpcore-soc-ctrl";
				reg = <0x20d20 0x6c>;
			};

			coherencyfab: coherency-fabric@21010 {
				compatible = "marvell,armada-380-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			pmsu: pmsu@22000 {
				compatible = "marvell,armada-380-pmsu";
				reg = <0x22000 0x1000>;
			};

			/*
			 * As a special exception to the "order by
			 * register address" rule, the eth0 node is
			 * placed here to ensure that it gets
			 * registered as the first interface, since
			 * the network subsystem doesn't allow naming
			 * interfaces using DT aliases. Without this,
			 * the ordering of interfaces is different
			 * from the one used in U-Boot and the
			 * labeling of interfaces on the boards, which
			 * is very confusing for users.
			 */
			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts-extended = <&mpic 8>;
				clocks = <&gateclk 4>;
				tx-csum-limit = <9800>;
				status = "disabled";
			};

			eth1: ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x4000>;
				interrupts-extended = <&mpic 10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			eth2: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts-extended = <&mpic 12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb0: usb@58000 {
				compatible = "marvell,orion-ehci";
				reg = <0x58000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			xor0: xor@60800 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor1: xor@60900 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			cesa: crypto@90000 {
				compatible = "marvell,armada-38x-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 23>, <&gateclk 21>,
					 <&gateclk 14>, <&gateclk 16>;
				clock-names = "cesa0", "cesa1",
					      "cesaz0", "cesaz1";
				marvell,crypto-srams = <&crypto_sram0>,
						       <&crypto_sram1>;
				marvell,crypto-sram-size = <0x800>;
			};

			rtc: rtc@a3800 {
				compatible = "marvell,armada-380-rtc";
				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			ahci0: sata@a8000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xa8000 0x2000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 15>;
				status = "disabled";
			};

			bm: bm@c8000 {
				compatible = "marvell,armada-380-neta-bm";
				reg = <0xc8000 0xac>;
				clocks = <&gateclk 13>;
				internal-mem = <&bm_bppi>;
				status = "disabled";
			};

			ahci1: sata@e0000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>;
				status = "disabled";
			};

			coredivclk: clock@e4250 {
				compatible = "marvell,armada-380-corediv-clock";
				reg = <0xe4250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			thermal: thermal@e8078 {
				compatible = "marvell,armada380-thermal";
				reg = <0xe4078 0x4>, <0xe4070 0x8>;
				status = "okay";
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdhci: sdhci@d8000 {
				compatible = "marvell,armada-380-sdhci";
				reg-names = "sdhci", "mbus", "conf-sdio3";
				reg = <0xd8000 0x1000>,
					<0xdc000 0x100>,
					<0x18454 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				mrvl,clk-delay-cycles = <0x1F>;
				status = "disabled";
			};

			usb3_0: usb3@f0000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			usb3_1: usb3@f8000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};
		};

		crypto_sram0: sa-sram0 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
			clocks = <&gateclk 21>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
		};

		bm_bppi: bm-bppi {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gateclk 13>;
			no-memory-wc;
			status = "disabled";
		};

		spi0: spi@10600 {
			compatible = "marvell,armada-380-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			compatible = "marvell,armada-380-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 1 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};

		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};
Commit	Line	Data
69f5689b	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0d3d96ab TP	2	/*
	3	* Device Tree Include file for Marvell Armada 38x family of SoCs.
	4	*
	5	* Copyright (C) 2014 Marvell
	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0d3d96ab TP	10	*/
0d3d96ab TP	11
f327d43d	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	13	#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab TP	14
	15	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	16
	17	/ {
abe60a3a RH	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20
0d3d96ab	21	model = "Marvell Armada 38x family SoC";
8dbdb8e7	22	compatible = "marvell,armada380";
0d3d96ab TP	23
	24	aliases {
	25	gpio0 = &gpio0;
	26	gpio1 = &gpio1;
bf6acf16 TP	27	serial0 = &uart0;
bf6acf16 TP	28	serial1 = &uart1;
0d3d96ab TP	29	};
0d3d96ab TP	30
754c4b1b EG	31	pmu {
	32	compatible = "arm,cortex-a9-pmu";
	33	interrupts-extended = <&mpic 3>;
	34	};
	35
0d3d96ab	36	soc {
a9e274c4	37	compatible = "marvell,armada380-mbus", "simple-bus";
0d3d96ab TP	38	#address-cells = <2>;
	39	#size-cells = <1>;
	40	controller = <&mbusc>;
	41	interrupt-parent = <&gic>;
	42	pcie-mem-aperture = <0xe0000000 0x8000000>;
	43	pcie-io-aperture = <0xe8000000 0x100000>;
	44
	45	bootrom {
	46	compatible = "marvell,bootrom";
	47	reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
	48	};
	49
a126de75	50	devbus_bootcs: devbus-bootcs {
0d3d96ab TP	51	compatible = "marvell,mvebu-devbus";
	52	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	53	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	clocks = <&coreclk 0>;
	57	status = "disabled";
	58	};
	59
a126de75	60	devbus_cs0: devbus-cs0 {
0d3d96ab TP	61	compatible = "marvell,mvebu-devbus";
	62	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	63	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	clocks = <&coreclk 0>;
	67	status = "disabled";
	68	};
	69
a126de75	70	devbus_cs1: devbus-cs1 {
0d3d96ab TP	71	compatible = "marvell,mvebu-devbus";
	72	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	73	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	clocks = <&coreclk 0>;
	77	status = "disabled";
	78	};
	79
a126de75	80	devbus_cs2: devbus-cs2 {
0d3d96ab TP	81	compatible = "marvell,mvebu-devbus";
	82	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	83	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	clocks = <&coreclk 0>;
	87	status = "disabled";
	88	};
	89
a126de75	90	devbus_cs3: devbus-cs3 {
0d3d96ab TP	91	compatible = "marvell,mvebu-devbus";
	92	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	93	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	clocks = <&coreclk 0>;
	97	status = "disabled";
	98	};
	99
	100	internal-regs {
	101	compatible = "simple-bus";
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
	105
042fa3dc CP	106	sdramc: sdramc@1400 {
	107	compatible = "marvell,armada-xp-sdram-controller";
	108	reg = <0x1400 0x500>;
	109	};
	110
0d3d96ab TP	111	L2: cache-controller@8000 {
	112	compatible = "arm,pl310-cache";
	113	reg = <0x8000 0x1000>;
	114	cache-unified;
	115	cache-level = <2>;
cda80a82	116	arm,double-linefill-incr = <0>;
c8f5a878	117	arm,double-linefill-wrap = <0>;
cda80a82	118	arm,double-linefill = <0>;
c8f5a878	119	prefetch-data = <1>;
0d3d96ab TP	120	};
0d3d96ab TP	121
964a6156 TP	122	scu@c000 {
	123	compatible = "arm,cortex-a9-scu";
	124	reg = <0xc000 0x58>;
	125	};
	126
0f015017 MW	127	timer@c200 {
	128	compatible = "arm,cortex-a9-global-timer";
	129	reg = <0xc200 0x20>;
	130	interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
	131	clocks = <&coreclk 2>;
	132	};
	133
0d3d96ab TP	134	timer@c600 {
	135	compatible = "arm,cortex-a9-twd-timer";
	136	reg = <0xc600 0x20>;
d11548e3	137	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab TP	138	clocks = <&coreclk 2>;
	139	};
	140
	141	gic: interrupt-controller@d000 {
	142	compatible = "arm,cortex-a9-gic";
	143	#interrupt-cells = <3>;
	144	#size-cells = <0>;
	145	interrupt-controller;
	146	reg = <0xd000 0x1000>,
	147	<0xc100 0x100>;
	148	};
	149
0d3d96ab	150	i2c0: i2c@11000 {
fbffee74	151	compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0d3d96ab TP	152	reg = <0x11000 0x20>;
	153	#address-cells = <1>;
	154	#size-cells = <0>;
d11548e3	155	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	156	timeout-ms = <1000>;
	157	clocks = <&coreclk 0>;
	158	status = "disabled";
	159	};
	160
	161	i2c1: i2c@11100 {
fbffee74	162	compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
0d3d96ab TP	163	reg = <0x11100 0x20>;
	164	#address-cells = <1>;
	165	#size-cells = <0>;
d11548e3	166	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	167	timeout-ms = <1000>;
	168	clocks = <&coreclk 0>;
	169	status = "disabled";
	170	};
	171
10c5c472	172	uart0: serial@12000 {
b7639b0b	173	compatible = "marvell,armada-38x-uart";
0d3d96ab TP	174	reg = <0x12000 0x100>;
0d3d96ab TP	175	reg-shift = <2>;
d11548e3	176	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	177	reg-io-width = <1>;
64939dc5	178	clocks = <&coreclk 0>;
0d3d96ab TP	179	status = "disabled";
	180	};
	181
8a48dccb	182	uart1: serial@12100 {
b7639b0b	183	compatible = "marvell,armada-38x-uart";
0d3d96ab TP	184	reg = <0x12100 0x100>;
0d3d96ab TP	185	reg-shift = <2>;
d11548e3	186	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	187	reg-io-width = <1>;
64939dc5	188	clocks = <&coreclk 0>;
0d3d96ab TP	189	status = "disabled";
	190	};
	191
10c5c472	192	pinctrl: pinctrl@18000 {
0d3d96ab	193	reg = <0x18000 0x20>;
91b4c91f MR	194
	195	ge0_rgmii_pins: ge-rgmii-pins-0 {
	196	marvell,pins = "mpp6", "mpp7", "mpp8",
	197	"mpp9", "mpp10", "mpp11",
	198	"mpp12", "mpp13", "mpp14",
	199	"mpp15", "mpp16", "mpp17";
	200	marvell,function = "ge0";
	201	};
	202
34598503 GC	203	ge1_rgmii_pins: ge-rgmii-pins-1 {
	204	marvell,pins = "mpp21", "mpp27", "mpp28",
	205	"mpp29", "mpp30", "mpp31",
	206	"mpp32", "mpp37", "mpp38",
	207	"mpp39", "mpp40", "mpp41";
	208	marvell,function = "ge1";
	209	};
	210
91b4c91f MR	211	i2c0_pins: i2c-pins-0 {
	212	marvell,pins = "mpp2", "mpp3";
	213	marvell,function = "i2c0";
	214	};
	215
	216	mdio_pins: mdio-pins {
	217	marvell,pins = "mpp4", "mpp5";
	218	marvell,function = "ge";
	219	};
	220
	221	ref_clk0_pins: ref-clk-pins-0 {
	222	marvell,pins = "mpp45";
	223	marvell,function = "ref";
	224	};
	225
34598503 GC	226	ref_clk1_pins: ref-clk-pins-1 {
	227	marvell,pins = "mpp46";
	228	marvell,function = "ref";
	229	};
	230
	231	spi0_pins: spi-pins-0 {
	232	marvell,pins = "mpp22", "mpp23", "mpp24",
	233	"mpp25";
	234	marvell,function = "spi0";
	235	};
	236
91b4c91f MR	237	spi1_pins: spi-pins-1 {
	238	marvell,pins = "mpp56", "mpp57", "mpp58",
	239	"mpp59";
	240	marvell,function = "spi1";
	241	};
	242
4c0437d0 CP	243	nand_pins: nand-pins {
	244	marvell,pins = "mpp22", "mpp34", "mpp23",
	245	"mpp33", "mpp38", "mpp28",
	246	"mpp40", "mpp42", "mpp35",
	247	"mpp36", "mpp25", "mpp30",
	248	"mpp32";
	249	marvell,function = "dev";
	250	};
	251
ba369daa SN	252	nand_rb: nand-rb {
	253	marvell,pins = "mpp41";
	254	marvell,function = "nand";
	255	};
	256
91b4c91f MR	257	uart0_pins: uart-pins-0 {
	258	marvell,pins = "mpp0", "mpp1";
	259	marvell,function = "ua0";
	260	};
	261
	262	uart1_pins: uart-pins-1 {
	263	marvell,pins = "mpp19", "mpp20";
	264	marvell,function = "ua1";
	265	};
34598503 GC	266
	267	sdhci_pins: sdhci-pins {
	268	marvell,pins = "mpp48", "mpp49", "mpp50",
	269	"mpp52", "mpp53", "mpp54",
	270	"mpp55", "mpp57", "mpp58",
	271	"mpp59";
	272	marvell,function = "sd0";
	273	};
	274
	275	sata0_pins: sata-pins-0 {
	276	marvell,pins = "mpp20";
	277	marvell,function = "sata0";
	278	};
	279
	280	sata1_pins: sata-pins-1 {
	281	marvell,pins = "mpp19";
	282	marvell,function = "sata1";
	283	};
	284
	285	sata2_pins: sata-pins-2 {
	286	marvell,pins = "mpp47";
	287	marvell,function = "sata2";
	288	};
	289
	290	sata3_pins: sata-pins-3 {
	291	marvell,pins = "mpp44";
	292	marvell,function = "sata3";
	293	};
0d3d96ab TP	294	};
	295
	296	gpio0: gpio@18100 {
7cb2acb3 RS	297	compatible = "marvell,armada-370-gpio",
	298	"marvell,orion-gpio";
	299	reg = <0x18100 0x40>, <0x181c0 0x08>;
	300	reg-names = "gpio", "pwm";
0d3d96ab TP	301	ngpios = <32>;
	302	gpio-controller;
	303	#gpio-cells = <2>;
7cb2acb3	304	#pwm-cells = <2>;
0d3d96ab TP	305	interrupt-controller;
0d3d96ab TP	306	#interrupt-cells = <2>;
d11548e3 TP	307	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	308	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	309	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	310	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
7cb2acb3	311	clocks = <&coreclk 0>;
0d3d96ab TP	312	};
	313
	314	gpio1: gpio@18140 {
7cb2acb3 RS	315	compatible = "marvell,armada-370-gpio",
	316	"marvell,orion-gpio";
	317	reg = <0x18140 0x40>, <0x181c8 0x08>;
	318	reg-names = "gpio", "pwm";
0d3d96ab TP	319	ngpios = <28>;
	320	gpio-controller;
	321	#gpio-cells = <2>;
7cb2acb3	322	#pwm-cells = <2>;
0d3d96ab TP	323	interrupt-controller;
0d3d96ab TP	324	#interrupt-cells = <2>;
d11548e3 TP	325	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	326	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	327	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	328	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
7cb2acb3	329	clocks = <&coreclk 0>;
0d3d96ab TP	330	};
0d3d96ab TP	331
a126de75	332	systemc: system-controller@18200 {
0d3d96ab TP	333	compatible = "marvell,armada-380-system-controller",
	334	"marvell,armada-370-xp-system-controller";
	335	reg = <0x18200 0x100>;
	336	};
	337
	338	gateclk: clock-gating-control@18220 {
	339	compatible = "marvell,armada-380-gating-clock";
	340	reg = <0x18220 0x4>;
	341	clocks = <&coreclk 0>;
	342	#clock-cells = <1>;
	343	};
	344
f3a6a9f3 RK	345	comphy: phy@18300 {
	346	compatible = "marvell,armada-380-comphy";
	347	reg = <0x18300 0x100>;
	348	#address-cells = <1>;
	349	#size-cells = <0>;
	350
	351	comphy0: phy@0 {
	352	reg = <0>;
	353	#phy-cells = <1>;
	354	};
	355
	356	comphy1: phy@1 {
	357	reg = <1>;
	358	#phy-cells = <1>;
	359	};
	360
	361	comphy2: phy@2 {
	362	reg = <2>;
	363	#phy-cells = <1>;
	364	};
	365
	366	comphy3: phy@3 {
	367	reg = <3>;
	368	#phy-cells = <1>;
	369	};
	370
	371	comphy4: phy@4 {
	372	reg = <4>;
	373	#phy-cells = <1>;
	374	};
	375
	376	comphy5: phy@5 {
	377	reg = <5>;
	378	#phy-cells = <1>;
	379	};
	380	};
	381
0d3d96ab TP	382	coreclk: mvebu-sar@18600 {
	383	compatible = "marvell,armada-380-core-clock";
	384	reg = <0x18600 0x04>;
	385	#clock-cells = <1>;
	386	};
	387
	388	mbusc: mbus-controller@20000 {
	389	compatible = "marvell,mbus-controller";
b69f4697 GC	390	reg = <0x20000 0x100>, <0x20180 0x20>,
b69f4697 GC	391	<0x20250 0x8>;
0d3d96ab TP	392	};
0d3d96ab TP	393
1d7b0839	394	mpic: interrupt-controller@20a00 {
0d3d96ab TP	395	compatible = "marvell,mpic";
	396	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	397	#interrupt-cells = <1>;
	398	#size-cells = <1>;
	399	interrupt-controller;
	400	msi-controller;
d11548e3	401	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	402	};
0d3d96ab TP	403
a126de75	404	timer: timer@20300 {
0d3d96ab TP	405	compatible = "marvell,armada-380-timer",
	406	"marvell,armada-xp-timer";
	407	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	408	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	409	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	410	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	411	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab TP	412	<&mpic 5>,
	413	<&mpic 6>;
	414	clocks = <&coreclk 2>, <&refclk>;
	415	clock-names = "nbclk", "fixed";
	416	};
	417
a126de75	418	watchdog: watchdog@20300 {
153a964a EG	419	compatible = "marvell,armada-380-wdt";
	420	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
	421	clocks = <&coreclk 2>, <&refclk>;
	422	clock-names = "nbclk", "fixed";
71f2b995 CP	423	interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
71f2b995 CP	424	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
153a964a EG	425	};
153a964a EG	426
a126de75	427	cpurst: cpurst@20800 {
19b06d7f TP	428	compatible = "marvell,armada-370-cpu-reset";
	429	reg = <0x20800 0x10>;
	430	};
	431
d7f3ec2b GC	432	mpcore-soc-ctrl@20d20 {
	433	compatible = "marvell,armada-380-mpcore-soc-ctrl";
	434	reg = <0x20d20 0x6c>;
	435	};
	436
a126de75	437	coherencyfab: coherency-fabric@21010 {
964a6156 TP	438	compatible = "marvell,armada-380-coherency-fabric";
	439	reg = <0x21010 0x1c>;
	440	};
	441
a126de75	442	pmsu: pmsu@22000 {
19b06d7f TP	443	compatible = "marvell,armada-380-pmsu";
	444	reg = <0x22000 0x1000>;
	445	};
	446
cb4f71c4 TP	447	/*
	448	* As a special exception to the "order by
	449	* register address" rule, the eth0 node is
	450	* placed here to ensure that it gets
	451	* registered as the first interface, since
	452	* the network subsystem doesn't allow naming
	453	* interfaces using DT aliases. Without this,
	454	* the ordering of interfaces is different
	455	* from the one used in U-Boot and the
	456	* labeling of interfaces on the boards, which
	457	* is very confusing for users.
	458	*/
	459	eth0: ethernet@70000 {
	460	compatible = "marvell,armada-370-neta";
	461	reg = <0x70000 0x4000>;
	462	interrupts-extended = <&mpic 8>;
	463	clocks = <&gateclk 4>;
	464	tx-csum-limit = <9800>;
	465	status = "disabled";
	466	};
	467
0d3d96ab TP	468	eth1: ethernet@30000 {
	469	compatible = "marvell,armada-370-neta";
	470	reg = <0x30000 0x4000>;
	471	interrupts-extended = <&mpic 10>;
	472	clocks = <&gateclk 3>;
	473	status = "disabled";
	474	};
	475
	476	eth2: ethernet@34000 {
	477	compatible = "marvell,armada-370-neta";
	478	reg = <0x34000 0x4000>;
	479	interrupts-extended = <&mpic 12>;
	480	clocks = <&gateclk 2>;
	481	status = "disabled";
	482	};
	483
a126de75	484	usb0: usb@58000 {
9e81775a GC	485	compatible = "marvell,orion-ehci";
	486	reg = <0x58000 0x500>;
	487	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	488	clocks = <&gateclk 18>;
	489	status = "disabled";
	490	};
	491
a126de75	492	xor0: xor@60800 {
449e1d64	493	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	494	reg = <0x60800 0x100
	495	0x60a00 0x100>;
	496	clocks = <&gateclk 22>;
	497	status = "okay";
	498
	499	xor00 {
d11548e3	500	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	501	dmacap,memcpy;
	502	dmacap,xor;
	503	};
	504	xor01 {
d11548e3	505	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	506	dmacap,memcpy;
	507	dmacap,xor;
	508	dmacap,memset;
	509	};
	510	};
	511
a126de75	512	xor1: xor@60900 {
449e1d64	513	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	514	reg = <0x60900 0x100
	515	0x60b00 0x100>;
	516	clocks = <&gateclk 28>;
	517	status = "okay";
	518
	519	xor10 {
d11548e3	520	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	521	dmacap,memcpy;
	522	dmacap,xor;
	523	};
	524	xor11 {
d11548e3	525	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	526	dmacap,memcpy;
	527	dmacap,xor;
	528	dmacap,memset;
	529	};
	530	};
	531
973ed083	532	mdio: mdio@72004 {
0d3d96ab TP	533	#address-cells = <1>;
	534	#size-cells = <0>;
	535	compatible = "marvell,orion-mdio";
	536	reg = <0x72004 0x4>;
33faf20b	537	clocks = <&gateclk 4>;
0d3d96ab	538	};
d6bd4b4c	539
a126de75	540	cesa: crypto@90000 {
35c99ec9 BB	541	compatible = "marvell,armada-38x-crypto";
	542	reg = <0x90000 0x10000>;
	543	reg-names = "regs";
	544	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	545	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	546	clocks = <&gateclk 23>, <&gateclk 21>,
	547	<&gateclk 14>, <&gateclk 16>;
	548	clock-names = "cesa0", "cesa1",
	549	"cesaz0", "cesaz1";
	550	marvell,crypto-srams = <&crypto_sram0>,
	551	<&crypto_sram1>;
	552	marvell,crypto-sram-size = <0x800>;
	553	};
	554
a126de75	555	rtc: rtc@a3800 {
a73c7305 GC	556	compatible = "marvell,armada-380-rtc";
	557	reg = <0xa3800 0x20>, <0x184a0 0x0c>;
	558	reg-names = "rtc", "rtc-soc";
	559	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	560	};
	561
f3d1f759	562	ahci0: sata@a8000 {
d175b6e4 TP	563	compatible = "marvell,armada-380-ahci";
	564	reg = <0xa8000 0x2000>;
	565	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	566	clocks = <&gateclk 15>;
	567	status = "disabled";
	568	};
	569
4a547a5a MW	570	bm: bm@c8000 {
	571	compatible = "marvell,armada-380-neta-bm";
	572	reg = <0xc8000 0xac>;
	573	clocks = <&gateclk 13>;
	574	internal-mem = <&bm_bppi>;
	575	status = "disabled";
	576	};
	577
f3d1f759	578	ahci1: sata@e0000 {
d175b6e4 TP	579	compatible = "marvell,armada-380-ahci";
	580	reg = <0xe0000 0x2000>;
	581	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	582	clocks = <&gateclk 30>;
	583	status = "disabled";
	584	};
	585
d6bd4b4c EG	586	coredivclk: clock@e4250 {
	587	compatible = "marvell,armada-380-corediv-clock";
	588	reg = <0xe4250 0xc>;
	589	#clock-cells = <1>;
	590	clocks = <&mainpll>;
	591	clock-output-names = "nand";
	592	};
93b5577e	593
a126de75	594	thermal: thermal@e8078 {
c630829a	595	compatible = "marvell,armada380-thermal";
568cc2f0	596	reg = <0xe4078 0x4>, <0xe4070 0x8>;
c630829a EG	597	status = "okay";
	598	};
	599
925d5e42 MR	600	nand_controller: nand-controller@d0000 {
925d5e42 MR	601	compatible = "marvell,armada370-nand-controller";
93b5577e EG	602	reg = <0xd0000 0x54>;
93b5577e EG	603	#address-cells = <1>;
925d5e42	604	#size-cells = <0>;
93b5577e EG	605	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	606	clocks = <&coredivclk 0>;
	607	status = "disabled";
	608	};
6eccc52b	609
a126de75	610	sdhci: sdhci@d8000 {
6eccc52b	611	compatible = "marvell,armada-380-sdhci";
ddbdc579 GC	612	reg-names = "sdhci", "mbus", "conf-sdio3";
	613	reg = <0xd8000 0x1000>,
	614	<0xdc000 0x100>,
	615	<0x18454 0x4>;
b757258a	616	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6eccc52b TP	617	clocks = <&gateclk 17>;
	618	mrvl,clk-delay-cycles = <0x1F>;
	619	status = "disabled";
	620	};
87e2fc37	621
f3d1f759	622	usb3_0: usb3@f0000 {
87e2fc37 GC	623	compatible = "marvell,armada-380-xhci";
	624	reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
	625	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	626	clocks = <&gateclk 9>;
	627	status = "disabled";
	628	};
	629
f3d1f759	630	usb3_1: usb3@f8000 {
87e2fc37 GC	631	compatible = "marvell,armada-380-xhci";
	632	reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
	633	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	634	clocks = <&gateclk 10>;
	635	status = "disabled";
	636	};
0d3d96ab	637	};
35c99ec9 BB	638
	639	crypto_sram0: sa-sram0 {
	640	compatible = "mmio-sram";
	641	reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
	642	clocks = <&gateclk 23>;
	643	#address-cells = <1>;
	644	#size-cells = <1>;
	645	ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
	646	};
	647
	648	crypto_sram1: sa-sram1 {
	649	compatible = "mmio-sram";
	650	reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
	651	clocks = <&gateclk 21>;
	652	#address-cells = <1>;
	653	#size-cells = <1>;
	654	ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
	655	};
4a547a5a MW	656
	657	bm_bppi: bm-bppi {
	658	compatible = "mmio-sram";
	659	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
	660	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
	661	#address-cells = <1>;
	662	#size-cells = <1>;
	663	clocks = <&gateclk 13>;
	664	no-memory-wc;
	665	status = "disabled";
	666	};
0160a4b6 SR	667
	668	spi0: spi@10600 {
	669	compatible = "marvell,armada-380-spi",
	670	"marvell,orion-spi";
	671	reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
	672	#address-cells = <1>;
	673	#size-cells = <0>;
	674	cell-index = <0>;
	675	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	676	clocks = <&coreclk 0>;
	677	status = "disabled";
	678	};
	679
	680	spi1: spi@10680 {
	681	compatible = "marvell,armada-380-spi",
	682	"marvell,orion-spi";
	683	reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
	684	#address-cells = <1>;
	685	#size-cells = <0>;
	686	cell-index = <1>;
	687	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	688	clocks = <&coreclk 0>;
	689	status = "disabled";
	690	};
0d3d96ab TP	691	};
	692
	693	clocks {
ad0de58b	694	/* 1 GHz fixed main PLL */
5bc94c99 EG	695	mainpll: mainpll {
	696	compatible = "fixed-clock";
	697	#clock-cells = <0>;
ae142bd9	698	clock-frequency = <1000000000>;
5bc94c99 EG	699	};
5bc94c99 EG	700
0d3d96ab TP	701	/* 25 MHz reference crystal */
	702	refclk: oscillator {
	703	compatible = "fixed-clock";
	704	#clock-cells = <0>;
	705	clock-frequency = <25000000>;
	706	};
	707	};
	708	};