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ca36855e | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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2 | /* |
3 | * Device Tree include file for SolidRun Clearfog 88F6828 based boards | |
4 | * | |
5 | * Copyright (C) 2015 Russell King | |
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6 | */ |
7 | ||
8 | #include "armada-388.dtsi" | |
9 | #include "armada-38x-solidrun-microsom.dtsi" | |
10 | ||
11 | / { | |
12 | aliases { | |
13 | /* So that mvebu u-boot can update the MAC addresses */ | |
14 | ethernet1 = ð0; | |
15 | ethernet2 = ð1; | |
16 | ethernet3 = ð2; | |
17 | }; | |
18 | ||
19 | chosen { | |
20 | stdout-path = "serial0:115200n8"; | |
21 | }; | |
22 | ||
23 | reg_3p3v: regulator-3p3v { | |
24 | compatible = "regulator-fixed"; | |
25 | regulator-name = "3P3V"; | |
26 | regulator-min-microvolt = <3300000>; | |
27 | regulator-max-microvolt = <3300000>; | |
28 | regulator-always-on; | |
29 | }; | |
30 | ||
31 | soc { | |
32 | internal-regs { | |
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33 | sata@a8000 { |
34 | /* pinctrl? */ | |
35 | status = "okay"; | |
36 | }; | |
37 | ||
38 | sata@e0000 { | |
39 | /* pinctrl? */ | |
40 | status = "okay"; | |
41 | }; | |
42 | ||
43 | sdhci@d8000 { | |
44 | bus-width = <4>; | |
45 | cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; | |
46 | no-1-8-v; | |
47 | pinctrl-0 = <µsom_sdhci_pins | |
48 | &clearfog_sdhci_cd_pins>; | |
49 | pinctrl-names = "default"; | |
50 | status = "okay"; | |
e807f029 | 51 | vmmc-supply = <®_3p3v>; |
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52 | wp-inverted; |
53 | }; | |
54 | ||
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55 | usb@58000 { |
56 | /* CON3, nearest power. */ | |
57 | status = "okay"; | |
58 | }; | |
59 | ||
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60 | usb3@f8000 { |
61 | /* CON7 */ | |
62 | status = "okay"; | |
63 | }; | |
64 | }; | |
65 | ||
28fbb9c5 | 66 | pcie { |
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67 | status = "okay"; |
68 | /* | |
69 | * The two PCIe units are accessible through | |
70 | * the mini-PCIe connectors on the board. | |
71 | */ | |
72 | pcie@2,0 { | |
73 | /* Port 1, Lane 0. CON3, nearest power. */ | |
74 | reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; | |
75 | status = "okay"; | |
76 | }; | |
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77 | }; |
78 | }; | |
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79 | |
80 | sfp: sfp { | |
81 | compatible = "sff,sfp"; | |
82 | i2c-bus = <&i2c1>; | |
83 | los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; | |
84 | mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; | |
85 | tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; | |
86 | tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; | |
87 | maximum-power-milliwatt = <2000>; | |
88 | }; | |
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89 | }; |
90 | ||
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91 | ð1 { |
92 | /* ethernet@30000 */ | |
93 | bm,pool-long = <2>; | |
94 | bm,pool-short = <1>; | |
95 | buffer-manager = <&bm>; | |
96 | phy-mode = "sgmii"; | |
97 | status = "okay"; | |
98 | }; | |
99 | ||
100 | ð2 { | |
101 | /* ethernet@34000 */ | |
102 | bm,pool-long = <3>; | |
103 | bm,pool-short = <1>; | |
104 | buffer-manager = <&bm>; | |
29e36c1f | 105 | managed = "in-band-status"; |
a14c2338 | 106 | phy-mode = "sgmii"; |
29e36c1f | 107 | sfp = <&sfp>; |
a14c2338 | 108 | status = "okay"; |
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109 | }; |
110 | ||
aa09b30f | 111 | &i2c0 { |
a83aeb38 | 112 | clock-frequency = <400000>; |
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113 | pinctrl-0 = <&i2c0_pins>; |
114 | pinctrl-names = "default"; | |
115 | status = "okay"; | |
116 | ||
117 | /* | |
118 | * PCA9655 GPIO expander, up to 1MHz clock. | |
119 | * 0-CON3 CLKREQ# | |
120 | * 1-CON3 PERST# | |
121 | * 2- | |
122 | * 3-CON3 W_DISABLE | |
123 | * 4- | |
124 | * 5-USB3 overcurrent | |
125 | * 6-USB3 power | |
126 | * 7- | |
127 | * 8-JP4 P1 | |
128 | * 9-JP4 P4 | |
129 | * 10-JP4 P5 | |
130 | * 11-m.2 DEVSLP | |
131 | * 12-SFP_LOS | |
132 | * 13-SFP_TX_FAULT | |
133 | * 14-SFP_TX_DISABLE | |
134 | * 15-SFP_MOD_DEF0 | |
135 | */ | |
136 | expander0: gpio-expander@20 { | |
137 | /* | |
138 | * This is how it should be: | |
139 | * compatible = "onnn,pca9655", "nxp,pca9555"; | |
140 | * but you can't do this because of the way I2C works. | |
141 | */ | |
142 | compatible = "nxp,pca9555"; | |
143 | gpio-controller; | |
144 | #gpio-cells = <2>; | |
145 | reg = <0x20>; | |
146 | ||
147 | pcie1_0_clkreq { | |
148 | gpio-hog; | |
149 | gpios = <0 GPIO_ACTIVE_LOW>; | |
150 | input; | |
151 | line-name = "pcie1.0-clkreq"; | |
152 | }; | |
153 | pcie1_0_w_disable { | |
154 | gpio-hog; | |
155 | gpios = <3 GPIO_ACTIVE_LOW>; | |
156 | output-low; | |
157 | line-name = "pcie1.0-w-disable"; | |
158 | }; | |
159 | usb3_ilimit { | |
160 | gpio-hog; | |
161 | gpios = <5 GPIO_ACTIVE_LOW>; | |
162 | input; | |
163 | line-name = "usb3-current-limit"; | |
164 | }; | |
165 | usb3_power { | |
166 | gpio-hog; | |
167 | gpios = <6 GPIO_ACTIVE_HIGH>; | |
168 | output-high; | |
169 | line-name = "usb3-power"; | |
170 | }; | |
171 | m2_devslp { | |
172 | gpio-hog; | |
173 | gpios = <11 GPIO_ACTIVE_HIGH>; | |
174 | output-low; | |
175 | line-name = "m.2 devslp"; | |
176 | }; | |
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177 | }; |
178 | ||
a83aeb38 | 179 | /* The MCP3021 supports standard and fast modes */ |
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180 | mikrobus_adc: mcp3021@4c { |
181 | compatible = "microchip,mcp3021"; | |
182 | reg = <0x4c>; | |
183 | }; | |
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184 | }; |
185 | ||
186 | &i2c1 { | |
187 | /* | |
188 | * Routed to SFP, mikrobus, and PCIe. | |
189 | * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with | |
190 | * address pins tied low, which takes addresses 0x50 and 0x51. | |
191 | * Mikrobus doesn't specify beyond an I2C bus being present. | |
192 | * PCIe uses ARP to assign addresses, or 0x63-0x64. | |
193 | */ | |
194 | clock-frequency = <100000>; | |
195 | pinctrl-0 = <&clearfog_i2c1_pins>; | |
196 | pinctrl-names = "default"; | |
197 | status = "okay"; | |
198 | }; | |
199 | ||
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200 | &pinctrl { |
201 | clearfog_i2c1_pins: i2c1-pins { | |
202 | /* SFP, PCIe, mSATA, mikrobus */ | |
203 | marvell,pins = "mpp26", "mpp27"; | |
204 | marvell,function = "i2c1"; | |
205 | }; | |
206 | clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { | |
207 | marvell,pins = "mpp20"; | |
208 | marvell,function = "gpio"; | |
209 | }; | |
210 | mikro_pins: mikro-pins { | |
211 | /* int: mpp22 rst: mpp29 */ | |
212 | marvell,pins = "mpp22", "mpp29"; | |
213 | marvell,function = "gpio"; | |
214 | }; | |
215 | mikro_spi_pins: mikro-spi-pins { | |
216 | marvell,pins = "mpp43"; | |
217 | marvell,function = "spi1"; | |
218 | }; | |
219 | mikro_uart_pins: mikro-uart-pins { | |
220 | marvell,pins = "mpp24", "mpp25"; | |
221 | marvell,function = "ua1"; | |
222 | }; | |
223 | }; | |
224 | ||
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225 | &spi1 { |
226 | /* | |
227 | * Add SPI CS pins for clearfog: | |
bb683d7a | 228 | * CS0: W25Q32 |
869fe59c | 229 | * CS1: PIC microcontroller (Pro models) |
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230 | * CS2: mikrobus |
231 | */ | |
869fe59c | 232 | pinctrl-0 = <&spi1_pins &mikro_spi_pins>; |
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233 | pinctrl-names = "default"; |
234 | status = "okay"; | |
235 | }; | |
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236 | |
237 | &uart1 { | |
238 | /* mikrobus uart */ | |
239 | pinctrl-0 = <&mikro_uart_pins>; | |
240 | pinctrl-names = "default"; | |
241 | status = "okay"; | |
242 | }; |