[linux-2.6-block.git] / arch / arm / boot / dts / armada-385.dtsi

/*
 * Device Tree Include file for Marvell Armada 385 SoC.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armada-38x.dtsi"

/ {
	model = "Marvell Armada 385 family SoC";
	compatible = "marvell,armada385", "marvell,armada380";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-380-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	soc {
		pciec: pcie {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;

			/*
			 * This port can be either x4 or x1. When
			 * configured in x4 by the bootloader, then
			 * pcie@4,0 is not available.
			 */
			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 8>;
				status = "disabled";
			};

			/* x1 port */
			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			/* x1 port */
			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

			/*
			 * x1 port only available when pcie@1,0 is
			 * configured as a x1 port
			 */
			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 7>;
				status = "disabled";
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv88f6820-pinctrl";
};
Commit	Line	Data
0d3d96ab TP	1	/*
	2	* Device Tree Include file for Marvell Armada 385 SoC.
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
3e0bccf2 GC	10	* This file is dual-licensed: you can use it either under the terms
	11	* of the GPL or the X11 license, at your option. Note that this dual
	12	* licensing only applies to this file, and not this project as a
	13	* whole.
	14	*
	15	* a) This file is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of the
	18	* License, or (at your option) any later version.
	19	*
24f0b6fe	20	* This file is distributed in the hope that it will be useful,
3e0bccf2 GC	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
24f0b6fe	25	* Or, alternatively,
3e0bccf2 GC	26	*
	27	* b) Permission is hereby granted, free of charge, to any person
	28	* obtaining a copy of this software and associated documentation
	29	* files (the "Software"), to deal in the Software without
24f0b6fe	30	* restriction, including without limitation the rights to use,
3e0bccf2 GC	31	* copy, modify, merge, publish, distribute, sublicense, and/or
	32	* sell copies of the Software, and to permit persons to whom the
	33	* Software is furnished to do so, subject to the following
	34	* conditions:
	35	*
	36	* The above copyright notice and this permission notice shall be
	37	* included in all copies or substantial portions of the Software.
	38	*
24f0b6fe	39	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3e0bccf2 GC	40	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	41	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	42	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
24f0b6fe	43	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3e0bccf2 GC	44	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	45	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	46	* OTHER DEALINGS IN THE SOFTWARE.
0d3d96ab TP	47	*/
	48
	49	#include "armada-38x.dtsi"
	50
	51	/ {
	52	model = "Marvell Armada 385 family SoC";
8dbdb8e7	53	compatible = "marvell,armada385", "marvell,armada380";
0d3d96ab TP	54
	55	cpus {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
19b06d7f TP	58	enable-method = "marvell,armada-380-smp";
19b06d7f TP	59
0d3d96ab TP	60	cpu@0 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a9";
	63	reg = <0>;
	64	};
	65	cpu@1 {
	66	device_type = "cpu";
	67	compatible = "arm,cortex-a9";
	68	reg = <1>;
	69	};
	70	};
	71
	72	soc {
28fbb9c5	73	pciec: pcie {
0d3d96ab TP	74	compatible = "marvell,armada-370-pcie";
	75	status = "disabled";
	76	device_type = "pci";
	77
	78	#address-cells = <3>;
	79	#size-cells = <2>;
	80
	81	msi-parent = <&mpic>;
	82	bus-range = <0x00 0xff>;
	83
	84	ranges =
	85	<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
	86	0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	87	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
	88	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
	89	0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
	90	0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
	91	0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
	92	0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
	93	0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
	94	0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
	95	0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
	96	0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
	97
	98	/*
	99	* This port can be either x4 or x1. When
	100	* configured in x4 by the bootloader, then
	101	* pcie@4,0 is not available.
	102	*/
a126de75	103	pcie1: pcie@1,0 {
0d3d96ab TP	104	device_type = "pci";
	105	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
	106	reg = <0x0800 0 0 0 0>;
	107	#address-cells = <3>;
	108	#size-cells = <2>;
	109	#interrupt-cells = <1>;
	110	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	111	0x81000000 0 0 0x81000000 0x1 0 1 0>;
28fbb9c5	112	bus-range = <0x00 0xff>;
0d3d96ab	113	interrupt-map-mask = <0 0 0 0>;
d11548e3	114	interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	115	marvell,pcie-port = <0>;
	116	marvell,pcie-lane = <0>;
	117	clocks = <&gateclk 8>;
	118	status = "disabled";
	119	};
	120
	121	/* x1 port */
a126de75	122	pcie2: pcie@2,0 {
0d3d96ab TP	123	device_type = "pci";
	124	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	125	reg = <0x1000 0 0 0 0>;
	126	#address-cells = <3>;
	127	#size-cells = <2>;
	128	#interrupt-cells = <1>;
	129	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	130	0x81000000 0 0 0x81000000 0x2 0 1 0>;
28fbb9c5	131	bus-range = <0x00 0xff>;
0d3d96ab	132	interrupt-map-mask = <0 0 0 0>;
d11548e3	133	interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	134	marvell,pcie-port = <1>;
	135	marvell,pcie-lane = <0>;
	136	clocks = <&gateclk 5>;
	137	status = "disabled";
	138	};
	139
	140	/* x1 port */
a126de75	141	pcie3: pcie@3,0 {
0d3d96ab TP	142	device_type = "pci";
0d3d96ab TP	143	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
c2a3dd9d	144	reg = <0x1800 0 0 0 0>;
0d3d96ab TP	145	#address-cells = <3>;
	146	#size-cells = <2>;
	147	#interrupt-cells = <1>;
	148	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	149	0x81000000 0 0 0x81000000 0x3 0 1 0>;
28fbb9c5	150	bus-range = <0x00 0xff>;
0d3d96ab	151	interrupt-map-mask = <0 0 0 0>;
d11548e3	152	interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	153	marvell,pcie-port = <2>;
	154	marvell,pcie-lane = <0>;
	155	clocks = <&gateclk 6>;
	156	status = "disabled";
	157	};
	158
	159	/*
	160	* x1 port only available when pcie@1,0 is
	161	* configured as a x1 port
	162	*/
a126de75	163	pcie4: pcie@4,0 {
0d3d96ab TP	164	device_type = "pci";
0d3d96ab TP	165	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
c2a3dd9d	166	reg = <0x2000 0 0 0 0>;
0d3d96ab TP	167	#address-cells = <3>;
	168	#size-cells = <2>;
	169	#interrupt-cells = <1>;
	170	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	171	0x81000000 0 0 0x81000000 0x4 0 1 0>;
28fbb9c5	172	bus-range = <0x00 0xff>;
0d3d96ab	173	interrupt-map-mask = <0 0 0 0>;
d11548e3	174	interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	175	marvell,pcie-port = <3>;
	176	marvell,pcie-lane = <0>;
	177	clocks = <&gateclk 7>;
	178	status = "disabled";
	179	};
	180	};
	181	};
	182	};
a126de75 CP	183
	184	&pinctrl {
	185	compatible = "marvell,mv88f6820-pinctrl";
	186	};