[linux-2.6-block.git] / arch / arm / boot / dts / armada-385-db-ap.dts

/*
 * Device Tree file for Marvell Armada 385 Access Point Development board
 * (DB-88F6820-AP)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Nadav Haklai <nadavh@marvell.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is licensed under the terms of the GNU General Public
 *     License version 2.  This program is licensed "as is" without
 *     any warranty of any kind, whether express or implied.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 385 Access Point Development Board";
	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = "serial1:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			i2c0: i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";

				/*
				 * This bus is wired to two EEPROM
				 * sockets, one of which holding the
				 * board ID used by the	bootloader.
				 * Erasing this EEPROM's content will
				 * brick the board.
				 * Use this bus with caution.
				 */
			};

			mdio@72004 {
				pinctrl-names = "default";
				pinctrl-0 = <&mdio_pins>;

				phy0: ethernet-phy@1 {
					reg = <1>;
				};

				phy1: ethernet-phy@4 {
					reg = <4>;
				};

				phy2: ethernet-phy@6 {
					reg = <6>;
				};
			};

			/* UART0 is exposed through the JP8 connector */
			uart0: serial@12000 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};

			/*
			 * UART1 is exposed through a FTDI chip
			 * wired to the mini-USB connector
			 */
			uart1: serial@12100 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart1_pins>;
				status = "okay";
			};

			pinctrl@18000 {
				xhci0_vbus_pins: xhci0-vbus-pins {
					marvell,pins = "mpp44";
					marvell,function = "gpio";
				};
			};

			/* CON3 */
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
				bm,pool-short = <3>;
			};

			/* CON2 */
			ethernet@34000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <3>;
			};

			/* CON4 */
			ethernet@70000 {
				pinctrl-names = "default";

				/*
				 * The Reference Clock 0 is used to
				 * provide a clock to the PHY
				 */
				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
				bm,pool-short = <3>;
			};

			bm@c8000 {
				status = "okay";
			};

			nfc: flash@d0000 {
				status = "okay";
				#address-cells = <1>;
				#size-cells = <1>;

				num-cs = <1>;
				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				marvell,nand-keep-config;
				marvell,nand-enable-arbiter;
				nand-on-flash-bbt;
			};

			usb3@f0000 {
				status = "okay";
				usb-phy = <&usb3_phy>;
			};
		};

		bm-bppi {
			status = "okay";
		};

		pcie-controller {
			status = "okay";

			/*
			 * The three PCIe units are accessible through
			 * standard mini-PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};

			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};
	};

	usb3_phy: usb3_phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&reg_xhci0_vbus>;
	};

	reg_xhci0_vbus: xhci0-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&xhci0_vbus_pins>;
		regulator-name = "xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p128", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <54000000>;
	};
};
Commit	Line	Data
e5ee1281 MR	1	/*
	2	* Device Tree file for Marvell Armada 385 Access Point Development board
	3	* (DB-88F6820-AP)
	4	*
	5	* Copyright (C) 2014 Marvell
	6	*
	7	* Nadav Haklai <nadavh@marvell.com>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is licensed under the terms of the GNU General Public
	15	* License version 2. This program is licensed "as is" without
	16	* any warranty of any kind, whether express or implied.
	17	*
	18	* Or, alternatively,
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use,
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	/dts-v1/;
	43	#include "armada-385.dtsi"
	44
	45	#include <dt-bindings/gpio/gpio.h>
	46
	47	/ {
	48	model = "Marvell Armada 385 Access Point Development Board";
db347f1a	49	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
e5ee1281 MR	50
e5ee1281 MR	51	chosen {
9552203c	52	stdout-path = "serial1:115200n8";
e5ee1281 MR	53	};
	54
	55	memory {
	56	device_type = "memory";
	57	reg = <0x00000000 0x80000000>; /* 2GB */
	58	};
	59
	60	soc {
	61	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
d716f2e8 BB	62	MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
d716f2e8 BB	63	MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
c49e99c2 MW	64	MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
c49e99c2 MW	65	MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
e5ee1281 MR	66
e5ee1281 MR	67	internal-regs {
e5ee1281 MR	68	i2c0: i2c@11000 {
	69	pinctrl-names = "default";
	70	pinctrl-0 = <&i2c0_pins>;
	71	status = "okay";
	72
	73	/*
	74	* This bus is wired to two EEPROM
	75	* sockets, one of which holding the
	76	* board ID used by the bootloader.
	77	* Erasing this EEPROM's content will
	78	* brick the board.
	79	* Use this bus with caution.
	80	*/
	81	};
	82
	83	mdio@72004 {
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&mdio_pins>;
	86
	87	phy0: ethernet-phy@1 {
	88	reg = <1>;
	89	};
	90
	91	phy1: ethernet-phy@4 {
	92	reg = <4>;
	93	};
	94
	95	phy2: ethernet-phy@6 {
	96	reg = <6>;
	97	};
	98	};
	99
	100	/* UART0 is exposed through the JP8 connector */
	101	uart0: serial@12000 {
	102	pinctrl-names = "default";
	103	pinctrl-0 = <&uart0_pins>;
	104	status = "okay";
	105	};
	106
	107	/*
	108	* UART1 is exposed through a FTDI chip
	109	* wired to the mini-USB connector
	110	*/
	111	uart1: serial@12100 {
	112	pinctrl-names = "default";
	113	pinctrl-0 = <&uart1_pins>;
	114	status = "okay";
	115	};
	116
7776ab70 MR	117	pinctrl@18000 {
	118	xhci0_vbus_pins: xhci0-vbus-pins {
	119	marvell,pins = "mpp44";
	120	marvell,function = "gpio";
	121	};
	122	};
	123
34d48290	124	/* CON3 */
e5ee1281 MR	125	ethernet@30000 {
	126	status = "okay";
	127	phy = <&phy2>;
	128	phy-mode = "sgmii";
c49e99c2 MW	129	buffer-manager = <&bm>;
	130	bm,pool-long = <1>;
	131	bm,pool-short = <3>;
e5ee1281 MR	132	};
e5ee1281 MR	133
34d48290	134	/* CON2 */
e5ee1281 MR	135	ethernet@34000 {
	136	status = "okay";
	137	phy = <&phy1>;
	138	phy-mode = "sgmii";
c49e99c2 MW	139	buffer-manager = <&bm>;
	140	bm,pool-long = <2>;
	141	bm,pool-short = <3>;
e5ee1281 MR	142	};
e5ee1281 MR	143
34d48290	144	/* CON4 */
e5ee1281 MR	145	ethernet@70000 {
	146	pinctrl-names = "default";
	147
	148	/*
	149	* The Reference Clock 0 is used to
	150	* provide a clock to the PHY
	151	*/
	152	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
	153	status = "okay";
	154	phy = <&phy0>;
	155	phy-mode = "rgmii-id";
c49e99c2 MW	156	buffer-manager = <&bm>;
	157	bm,pool-long = <0>;
	158	bm,pool-short = <3>;
	159	};
	160
	161	bm@c8000 {
	162	status = "okay";
e5ee1281	163	};
2a2dbd8b MR	164
	165	nfc: flash@d0000 {
	166	status = "okay";
	167	#address-cells = <1>;
	168	#size-cells = <1>;
	169
	170	num-cs = <1>;
	171	nand-ecc-strength = <4>;
	172	nand-ecc-step-size = <512>;
	173	marvell,nand-keep-config;
	174	marvell,nand-enable-arbiter;
	175	nand-on-flash-bbt;
	176	};
7776ab70 MR	177
	178	usb3@f0000 {
	179	status = "okay";
	180	usb-phy = <&usb3_phy>;
	181	};
e5ee1281 MR	182	};
e5ee1281 MR	183
c49e99c2 MW	184	bm-bppi {
	185	status = "okay";
	186	};
	187
e5ee1281 MR	188	pcie-controller {
	189	status = "okay";
	190
	191	/*
	192	* The three PCIe units are accessible through
	193	* standard mini-PCIe slots on the board.
	194	*/
	195	pcie@1,0 {
	196	/* Port 0, Lane 0 */
	197	status = "okay";
	198	};
	199
	200	pcie@2,0 {
	201	/* Port 1, Lane 0 */
	202	status = "okay";
	203	};
	204
	205	pcie@3,0 {
	206	/* Port 2, Lane 0 */
	207	status = "okay";
	208	};
	209	};
	210	};
7776ab70 MR	211
	212	usb3_phy: usb3_phy {
	213	compatible = "usb-nop-xceiv";
	214	vcc-supply = <&reg_xhci0_vbus>;
	215	};
	216
	217	reg_xhci0_vbus: xhci0-vbus {
	218	compatible = "regulator-fixed";
	219	pinctrl-names = "default";
	220	pinctrl-0 = <&xhci0_vbus_pins>;
	221	regulator-name = "xhci0-vbus";
	222	regulator-min-microvolt = <5000000>;
	223	regulator-max-microvolt = <5000000>;
	224	enable-active-high;
	225	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	226	};
e5ee1281	227	};
0160a4b6 SR	228
	229	&spi1 {
	230	pinctrl-names = "default";
	231	pinctrl-0 = <&spi1_pins>;
	232	status = "okay";
	233
	234	spi-flash@0 {
	235	#address-cells = <1>;
	236	#size-cells = <1>;
	237	compatible = "st,m25p128", "jedec,spi-nor";
	238	reg = <0>; /* Chip select 0 */
	239	spi-max-frequency = <54000000>;
	240	};
	241	};