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4de59085 GC |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 375 family SoC | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
a2be1561 | 14 | #include "skeleton.dtsi" |
f327d43d | 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
d11548e3 | 16 | #include <dt-bindings/interrupt-controller/irq.h> |
4de59085 GC |
17 | |
18 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
19 | ||
20 | / { | |
21 | model = "Marvell Armada 375 family SoC"; | |
22 | compatible = "marvell,armada375"; | |
23 | ||
24 | aliases { | |
25 | gpio0 = &gpio0; | |
26 | gpio1 = &gpio1; | |
27 | gpio2 = &gpio2; | |
28 | }; | |
29 | ||
30 | clocks { | |
31 | /* 2 GHz fixed main PLL */ | |
32 | mainpll: mainpll { | |
33 | compatible = "fixed-clock"; | |
34 | #clock-cells = <0>; | |
35 | clock-frequency = <2000000000>; | |
36 | }; | |
37 | }; | |
38 | ||
39 | cpus { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42eae5a4 GC |
42 | enable-method = "marvell,armada-375-smp"; |
43 | ||
4de59085 GC |
44 | cpu@0 { |
45 | device_type = "cpu"; | |
46 | compatible = "arm,cortex-a9"; | |
47 | reg = <0>; | |
48 | }; | |
49 | cpu@1 { | |
50 | device_type = "cpu"; | |
51 | compatible = "arm,cortex-a9"; | |
52 | reg = <1>; | |
53 | }; | |
54 | }; | |
55 | ||
56 | soc { | |
57 | compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; | |
58 | #address-cells = <2>; | |
59 | #size-cells = <1>; | |
60 | controller = <&mbusc>; | |
61 | interrupt-parent = <&gic>; | |
62 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
63 | pcie-io-aperture = <0xe8000000 0x100000>; | |
64 | ||
65 | bootrom { | |
66 | compatible = "marvell,bootrom"; | |
67 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
68 | }; | |
69 | ||
70 | devbus-bootcs { | |
71 | compatible = "marvell,mvebu-devbus"; | |
72 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | |
73 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | |
74 | #address-cells = <1>; | |
75 | #size-cells = <1>; | |
76 | clocks = <&coreclk 0>; | |
77 | status = "disabled"; | |
78 | }; | |
79 | ||
80 | devbus-cs0 { | |
81 | compatible = "marvell,mvebu-devbus"; | |
82 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | |
83 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | |
84 | #address-cells = <1>; | |
85 | #size-cells = <1>; | |
86 | clocks = <&coreclk 0>; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | devbus-cs1 { | |
91 | compatible = "marvell,mvebu-devbus"; | |
92 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | |
93 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | |
94 | #address-cells = <1>; | |
95 | #size-cells = <1>; | |
96 | clocks = <&coreclk 0>; | |
97 | status = "disabled"; | |
98 | }; | |
99 | ||
100 | devbus-cs2 { | |
101 | compatible = "marvell,mvebu-devbus"; | |
102 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | |
103 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | clocks = <&coreclk 0>; | |
107 | status = "disabled"; | |
108 | }; | |
109 | ||
110 | devbus-cs3 { | |
111 | compatible = "marvell,mvebu-devbus"; | |
112 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | |
113 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | |
114 | #address-cells = <1>; | |
115 | #size-cells = <1>; | |
116 | clocks = <&coreclk 0>; | |
117 | status = "disabled"; | |
118 | }; | |
119 | ||
120 | internal-regs { | |
121 | compatible = "simple-bus"; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <1>; | |
124 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
125 | ||
126 | L2: cache-controller@8000 { | |
127 | compatible = "arm,pl310-cache"; | |
128 | reg = <0x8000 0x1000>; | |
129 | cache-unified; | |
130 | cache-level = <2>; | |
131 | }; | |
132 | ||
6a8a57f2 TP |
133 | scu@c000 { |
134 | compatible = "arm,cortex-a9-scu"; | |
135 | reg = <0xc000 0x58>; | |
136 | }; | |
137 | ||
4de59085 GC |
138 | timer@c600 { |
139 | compatible = "arm,cortex-a9-twd-timer"; | |
140 | reg = <0xc600 0x20>; | |
d11548e3 | 141 | interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; |
4de59085 GC |
142 | clocks = <&coreclk 2>; |
143 | }; | |
144 | ||
145 | gic: interrupt-controller@d000 { | |
146 | compatible = "arm,cortex-a9-gic"; | |
147 | #interrupt-cells = <3>; | |
148 | #size-cells = <0>; | |
149 | interrupt-controller; | |
150 | reg = <0xd000 0x1000>, | |
151 | <0xc100 0x100>; | |
152 | }; | |
153 | ||
154 | spi0: spi@10600 { | |
155 | compatible = "marvell,orion-spi"; | |
156 | reg = <0x10600 0x50>; | |
157 | #address-cells = <1>; | |
158 | #size-cells = <0>; | |
159 | cell-index = <0>; | |
d11548e3 | 160 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
161 | clocks = <&coreclk 0>; |
162 | status = "disabled"; | |
163 | }; | |
164 | ||
165 | spi1: spi@10680 { | |
166 | compatible = "marvell,orion-spi"; | |
167 | reg = <0x10680 0x50>; | |
168 | #address-cells = <1>; | |
169 | #size-cells = <0>; | |
170 | cell-index = <1>; | |
d11548e3 | 171 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
172 | clocks = <&coreclk 0>; |
173 | status = "disabled"; | |
174 | }; | |
175 | ||
176 | i2c0: i2c@11000 { | |
177 | compatible = "marvell,mv64xxx-i2c"; | |
178 | reg = <0x11000 0x20>; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
d11548e3 | 181 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
182 | timeout-ms = <1000>; |
183 | clocks = <&coreclk 0>; | |
184 | status = "disabled"; | |
185 | }; | |
186 | ||
187 | i2c1: i2c@11100 { | |
188 | compatible = "marvell,mv64xxx-i2c"; | |
189 | reg = <0x11100 0x20>; | |
190 | #address-cells = <1>; | |
191 | #size-cells = <0>; | |
d11548e3 | 192 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
193 | timeout-ms = <1000>; |
194 | clocks = <&coreclk 0>; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | serial@12000 { | |
199 | compatible = "snps,dw-apb-uart"; | |
200 | reg = <0x12000 0x100>; | |
201 | reg-shift = <2>; | |
d11548e3 | 202 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 | 203 | reg-io-width = <1>; |
64939dc5 | 204 | clocks = <&coreclk 0>; |
4de59085 GC |
205 | status = "disabled"; |
206 | }; | |
207 | ||
208 | serial@12100 { | |
209 | compatible = "snps,dw-apb-uart"; | |
210 | reg = <0x12100 0x100>; | |
211 | reg-shift = <2>; | |
d11548e3 | 212 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 | 213 | reg-io-width = <1>; |
64939dc5 | 214 | clocks = <&coreclk 0>; |
4de59085 GC |
215 | status = "disabled"; |
216 | }; | |
217 | ||
218 | pinctrl { | |
219 | compatible = "marvell,mv88f6720-pinctrl"; | |
220 | reg = <0x18000 0x24>; | |
221 | ||
222 | i2c0_pins: i2c0-pins { | |
223 | marvell,pins = "mpp14", "mpp15"; | |
224 | marvell,function = "i2c0"; | |
225 | }; | |
226 | ||
227 | i2c1_pins: i2c1-pins { | |
228 | marvell,pins = "mpp61", "mpp62"; | |
229 | marvell,function = "i2c1"; | |
230 | }; | |
231 | ||
232 | nand_pins: nand-pins { | |
233 | marvell,pins = "mpp0", "mpp1", "mpp2", | |
234 | "mpp3", "mpp4", "mpp5", | |
235 | "mpp6", "mpp7", "mpp8", | |
236 | "mpp9", "mpp10", "mpp11", | |
237 | "mpp12", "mpp13"; | |
238 | marvell,function = "nand"; | |
239 | }; | |
240 | ||
241 | sdio_pins: sdio-pins { | |
242 | marvell,pins = "mpp24", "mpp25", "mpp26", | |
243 | "mpp27", "mpp28", "mpp29"; | |
244 | marvell,function = "sd"; | |
245 | }; | |
246 | ||
247 | spi0_pins: spi0-pins { | |
248 | marvell,pins = "mpp0", "mpp1", "mpp4", | |
249 | "mpp5", "mpp8", "mpp9"; | |
250 | marvell,function = "spi0"; | |
251 | }; | |
252 | }; | |
253 | ||
254 | gpio0: gpio@18100 { | |
255 | compatible = "marvell,orion-gpio"; | |
256 | reg = <0x18100 0x40>; | |
257 | ngpios = <32>; | |
258 | gpio-controller; | |
259 | #gpio-cells = <2>; | |
260 | interrupt-controller; | |
261 | #interrupt-cells = <2>; | |
d11548e3 TP |
262 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
263 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
264 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
265 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
4de59085 GC |
266 | }; |
267 | ||
268 | gpio1: gpio@18140 { | |
269 | compatible = "marvell,orion-gpio"; | |
270 | reg = <0x18140 0x40>; | |
271 | ngpios = <32>; | |
272 | gpio-controller; | |
273 | #gpio-cells = <2>; | |
274 | interrupt-controller; | |
275 | #interrupt-cells = <2>; | |
d11548e3 TP |
276 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
277 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
278 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
279 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
4de59085 GC |
280 | }; |
281 | ||
282 | gpio2: gpio@18180 { | |
283 | compatible = "marvell,orion-gpio"; | |
284 | reg = <0x18180 0x40>; | |
285 | ngpios = <3>; | |
286 | gpio-controller; | |
287 | #gpio-cells = <2>; | |
288 | interrupt-controller; | |
289 | #interrupt-cells = <2>; | |
d11548e3 | 290 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
291 | }; |
292 | ||
293 | system-controller@18200 { | |
294 | compatible = "marvell,armada-375-system-controller"; | |
295 | reg = <0x18200 0x100>; | |
296 | }; | |
297 | ||
298 | gateclk: clock-gating-control@18220 { | |
299 | compatible = "marvell,armada-375-gating-clock"; | |
300 | reg = <0x18220 0x4>; | |
301 | clocks = <&coreclk 0>; | |
302 | #clock-cells = <1>; | |
303 | }; | |
304 | ||
305 | mbusc: mbus-controller@20000 { | |
306 | compatible = "marvell,mbus-controller"; | |
307 | reg = <0x20000 0x100>, <0x20180 0x20>; | |
308 | }; | |
309 | ||
310 | mpic: interrupt-controller@20000 { | |
311 | compatible = "marvell,mpic"; | |
312 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
313 | #interrupt-cells = <1>; | |
314 | #size-cells = <1>; | |
315 | interrupt-controller; | |
316 | msi-controller; | |
d11548e3 | 317 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
318 | }; |
319 | ||
320 | timer@20300 { | |
321 | compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; | |
322 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
d11548e3 TP |
323 | interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
324 | <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
325 | <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
326 | <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
4de59085 GC |
327 | <&mpic 5>, |
328 | <&mpic 6>; | |
329 | clocks = <&coreclk 0>; | |
330 | }; | |
331 | ||
13dacc56 EG |
332 | watchdog@20300 { |
333 | compatible = "marvell,armada-375-wdt"; | |
334 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; | |
335 | clocks = <&coreclk 0>; | |
336 | }; | |
337 | ||
42eae5a4 GC |
338 | cpurst@20800 { |
339 | compatible = "marvell,armada-370-cpu-reset"; | |
340 | reg = <0x20800 0x10>; | |
341 | }; | |
342 | ||
6a8a57f2 TP |
343 | coherency-fabric@21010 { |
344 | compatible = "marvell,armada-375-coherency-fabric"; | |
345 | reg = <0x21010 0x1c>; | |
346 | }; | |
347 | ||
4de59085 GC |
348 | xor@60800 { |
349 | compatible = "marvell,orion-xor"; | |
350 | reg = <0x60800 0x100 | |
351 | 0x60A00 0x100>; | |
352 | clocks = <&gateclk 22>; | |
353 | status = "okay"; | |
354 | ||
355 | xor00 { | |
d11548e3 | 356 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
357 | dmacap,memcpy; |
358 | dmacap,xor; | |
359 | }; | |
360 | xor01 { | |
d11548e3 | 361 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
362 | dmacap,memcpy; |
363 | dmacap,xor; | |
364 | dmacap,memset; | |
365 | }; | |
366 | }; | |
367 | ||
368 | xor@60900 { | |
369 | compatible = "marvell,orion-xor"; | |
370 | reg = <0x60900 0x100 | |
371 | 0x60b00 0x100>; | |
372 | clocks = <&gateclk 23>; | |
373 | status = "okay"; | |
374 | ||
375 | xor10 { | |
d11548e3 | 376 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
377 | dmacap,memcpy; |
378 | dmacap,xor; | |
379 | }; | |
380 | xor11 { | |
d11548e3 | 381 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
382 | dmacap,memcpy; |
383 | dmacap,xor; | |
384 | dmacap,memset; | |
385 | }; | |
386 | }; | |
387 | ||
388 | sata@a0000 { | |
389 | compatible = "marvell,orion-sata"; | |
390 | reg = <0xa0000 0x5000>; | |
d11548e3 | 391 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
392 | clocks = <&gateclk 14>, <&gateclk 20>; |
393 | clock-names = "0", "1"; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
397 | nand@d0000 { | |
398 | compatible = "marvell,armada370-nand"; | |
399 | reg = <0xd0000 0x54>; | |
400 | #address-cells = <1>; | |
401 | #size-cells = <1>; | |
d11548e3 | 402 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
403 | clocks = <&gateclk 11>; |
404 | status = "disabled"; | |
405 | }; | |
406 | ||
407 | mvsdio@d4000 { | |
408 | compatible = "marvell,orion-sdio"; | |
409 | reg = <0xd4000 0x200>; | |
d11548e3 | 410 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
411 | clocks = <&gateclk 17>; |
412 | bus-width = <4>; | |
413 | cap-sdio-irq; | |
414 | cap-sd-highspeed; | |
415 | cap-mmc-highspeed; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
419 | coreclk: mvebu-sar@e8204 { | |
420 | compatible = "marvell,armada-375-core-clock"; | |
421 | reg = <0xe8204 0x04>; | |
422 | #clock-cells = <1>; | |
423 | }; | |
424 | ||
425 | coredivclk: corediv-clock@e8250 { | |
426 | compatible = "marvell,armada-375-corediv-clock"; | |
427 | reg = <0xe8250 0xc>; | |
428 | #clock-cells = <1>; | |
429 | clocks = <&mainpll>; | |
430 | clock-output-names = "nand"; | |
431 | }; | |
432 | }; | |
433 | ||
434 | pcie-controller { | |
435 | compatible = "marvell,armada-370-pcie"; | |
436 | status = "disabled"; | |
437 | device_type = "pci"; | |
438 | ||
439 | #address-cells = <3>; | |
440 | #size-cells = <2>; | |
441 | ||
442 | msi-parent = <&mpic>; | |
443 | bus-range = <0x00 0xff>; | |
444 | ||
445 | ranges = | |
446 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
447 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
448 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ | |
449 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ | |
450 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ | |
451 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; | |
452 | ||
453 | pcie@1,0 { | |
454 | device_type = "pci"; | |
455 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
456 | reg = <0x0800 0 0 0 0>; | |
457 | #address-cells = <3>; | |
458 | #size-cells = <2>; | |
459 | #interrupt-cells = <1>; | |
460 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
461 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
462 | interrupt-map-mask = <0 0 0 0>; | |
d11548e3 | 463 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
464 | marvell,pcie-port = <0>; |
465 | marvell,pcie-lane = <0>; | |
466 | clocks = <&gateclk 5>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | pcie@2,0 { | |
471 | device_type = "pci"; | |
472 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
473 | reg = <0x1000 0 0 0 0>; | |
474 | #address-cells = <3>; | |
475 | #size-cells = <2>; | |
476 | #interrupt-cells = <1>; | |
477 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
478 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
479 | interrupt-map-mask = <0 0 0 0>; | |
d11548e3 | 480 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
4de59085 GC |
481 | marvell,pcie-port = <0>; |
482 | marvell,pcie-lane = <1>; | |
483 | clocks = <&gateclk 6>; | |
484 | status = "disabled"; | |
485 | }; | |
486 | ||
487 | }; | |
488 | }; | |
489 | }; |