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4de59085 GC |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 375 family SoC | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) | |
17 | ||
18 | / { | |
19 | model = "Marvell Armada 375 family SoC"; | |
20 | compatible = "marvell,armada375"; | |
21 | ||
22 | aliases { | |
23 | gpio0 = &gpio0; | |
24 | gpio1 = &gpio1; | |
25 | gpio2 = &gpio2; | |
26 | }; | |
27 | ||
28 | clocks { | |
29 | /* 2 GHz fixed main PLL */ | |
30 | mainpll: mainpll { | |
31 | compatible = "fixed-clock"; | |
32 | #clock-cells = <0>; | |
33 | clock-frequency = <2000000000>; | |
34 | }; | |
35 | }; | |
36 | ||
37 | cpus { | |
38 | #address-cells = <1>; | |
39 | #size-cells = <0>; | |
40 | cpu@0 { | |
41 | device_type = "cpu"; | |
42 | compatible = "arm,cortex-a9"; | |
43 | reg = <0>; | |
44 | }; | |
45 | cpu@1 { | |
46 | device_type = "cpu"; | |
47 | compatible = "arm,cortex-a9"; | |
48 | reg = <1>; | |
49 | }; | |
50 | }; | |
51 | ||
52 | soc { | |
53 | compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; | |
54 | #address-cells = <2>; | |
55 | #size-cells = <1>; | |
56 | controller = <&mbusc>; | |
57 | interrupt-parent = <&gic>; | |
58 | pcie-mem-aperture = <0xe0000000 0x8000000>; | |
59 | pcie-io-aperture = <0xe8000000 0x100000>; | |
60 | ||
61 | bootrom { | |
62 | compatible = "marvell,bootrom"; | |
63 | reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; | |
64 | }; | |
65 | ||
66 | devbus-bootcs { | |
67 | compatible = "marvell,mvebu-devbus"; | |
68 | reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; | |
69 | ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | clocks = <&coreclk 0>; | |
73 | status = "disabled"; | |
74 | }; | |
75 | ||
76 | devbus-cs0 { | |
77 | compatible = "marvell,mvebu-devbus"; | |
78 | reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; | |
79 | ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; | |
80 | #address-cells = <1>; | |
81 | #size-cells = <1>; | |
82 | clocks = <&coreclk 0>; | |
83 | status = "disabled"; | |
84 | }; | |
85 | ||
86 | devbus-cs1 { | |
87 | compatible = "marvell,mvebu-devbus"; | |
88 | reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; | |
89 | ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; | |
90 | #address-cells = <1>; | |
91 | #size-cells = <1>; | |
92 | clocks = <&coreclk 0>; | |
93 | status = "disabled"; | |
94 | }; | |
95 | ||
96 | devbus-cs2 { | |
97 | compatible = "marvell,mvebu-devbus"; | |
98 | reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; | |
99 | ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <1>; | |
102 | clocks = <&coreclk 0>; | |
103 | status = "disabled"; | |
104 | }; | |
105 | ||
106 | devbus-cs3 { | |
107 | compatible = "marvell,mvebu-devbus"; | |
108 | reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; | |
109 | ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; | |
110 | #address-cells = <1>; | |
111 | #size-cells = <1>; | |
112 | clocks = <&coreclk 0>; | |
113 | status = "disabled"; | |
114 | }; | |
115 | ||
116 | internal-regs { | |
117 | compatible = "simple-bus"; | |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
120 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | |
121 | ||
122 | L2: cache-controller@8000 { | |
123 | compatible = "arm,pl310-cache"; | |
124 | reg = <0x8000 0x1000>; | |
125 | cache-unified; | |
126 | cache-level = <2>; | |
127 | }; | |
128 | ||
129 | timer@c600 { | |
130 | compatible = "arm,cortex-a9-twd-timer"; | |
131 | reg = <0xc600 0x20>; | |
132 | interrupts = <1 13 0x301>; | |
133 | clocks = <&coreclk 2>; | |
134 | }; | |
135 | ||
136 | gic: interrupt-controller@d000 { | |
137 | compatible = "arm,cortex-a9-gic"; | |
138 | #interrupt-cells = <3>; | |
139 | #size-cells = <0>; | |
140 | interrupt-controller; | |
141 | reg = <0xd000 0x1000>, | |
142 | <0xc100 0x100>; | |
143 | }; | |
144 | ||
145 | spi0: spi@10600 { | |
146 | compatible = "marvell,orion-spi"; | |
147 | reg = <0x10600 0x50>; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | cell-index = <0>; | |
151 | interrupts = <0 1 0x4>; | |
152 | clocks = <&coreclk 0>; | |
153 | status = "disabled"; | |
154 | }; | |
155 | ||
156 | spi1: spi@10680 { | |
157 | compatible = "marvell,orion-spi"; | |
158 | reg = <0x10680 0x50>; | |
159 | #address-cells = <1>; | |
160 | #size-cells = <0>; | |
161 | cell-index = <1>; | |
162 | interrupts = <0 63 0x4>; | |
163 | clocks = <&coreclk 0>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
167 | i2c0: i2c@11000 { | |
168 | compatible = "marvell,mv64xxx-i2c"; | |
169 | reg = <0x11000 0x20>; | |
170 | #address-cells = <1>; | |
171 | #size-cells = <0>; | |
172 | interrupts = <0 2 0x4>; | |
173 | timeout-ms = <1000>; | |
174 | clocks = <&coreclk 0>; | |
175 | status = "disabled"; | |
176 | }; | |
177 | ||
178 | i2c1: i2c@11100 { | |
179 | compatible = "marvell,mv64xxx-i2c"; | |
180 | reg = <0x11100 0x20>; | |
181 | #address-cells = <1>; | |
182 | #size-cells = <0>; | |
183 | interrupts = <0 3 0x4>; | |
184 | timeout-ms = <1000>; | |
185 | clocks = <&coreclk 0>; | |
186 | status = "disabled"; | |
187 | }; | |
188 | ||
189 | serial@12000 { | |
190 | compatible = "snps,dw-apb-uart"; | |
191 | reg = <0x12000 0x100>; | |
192 | reg-shift = <2>; | |
193 | interrupts = <0 12 4>; | |
194 | reg-io-width = <1>; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | serial@12100 { | |
199 | compatible = "snps,dw-apb-uart"; | |
200 | reg = <0x12100 0x100>; | |
201 | reg-shift = <2>; | |
202 | interrupts = <0 13 4>; | |
203 | reg-io-width = <1>; | |
204 | status = "disabled"; | |
205 | }; | |
206 | ||
207 | pinctrl { | |
208 | compatible = "marvell,mv88f6720-pinctrl"; | |
209 | reg = <0x18000 0x24>; | |
210 | ||
211 | i2c0_pins: i2c0-pins { | |
212 | marvell,pins = "mpp14", "mpp15"; | |
213 | marvell,function = "i2c0"; | |
214 | }; | |
215 | ||
216 | i2c1_pins: i2c1-pins { | |
217 | marvell,pins = "mpp61", "mpp62"; | |
218 | marvell,function = "i2c1"; | |
219 | }; | |
220 | ||
221 | nand_pins: nand-pins { | |
222 | marvell,pins = "mpp0", "mpp1", "mpp2", | |
223 | "mpp3", "mpp4", "mpp5", | |
224 | "mpp6", "mpp7", "mpp8", | |
225 | "mpp9", "mpp10", "mpp11", | |
226 | "mpp12", "mpp13"; | |
227 | marvell,function = "nand"; | |
228 | }; | |
229 | ||
230 | sdio_pins: sdio-pins { | |
231 | marvell,pins = "mpp24", "mpp25", "mpp26", | |
232 | "mpp27", "mpp28", "mpp29"; | |
233 | marvell,function = "sd"; | |
234 | }; | |
235 | ||
236 | spi0_pins: spi0-pins { | |
237 | marvell,pins = "mpp0", "mpp1", "mpp4", | |
238 | "mpp5", "mpp8", "mpp9"; | |
239 | marvell,function = "spi0"; | |
240 | }; | |
241 | }; | |
242 | ||
243 | gpio0: gpio@18100 { | |
244 | compatible = "marvell,orion-gpio"; | |
245 | reg = <0x18100 0x40>; | |
246 | ngpios = <32>; | |
247 | gpio-controller; | |
248 | #gpio-cells = <2>; | |
249 | interrupt-controller; | |
250 | #interrupt-cells = <2>; | |
251 | interrupts = <0 53 0x4>, <0 54 0x4>, | |
252 | <0 55 0x4>, <0 56 0x4>; | |
253 | }; | |
254 | ||
255 | gpio1: gpio@18140 { | |
256 | compatible = "marvell,orion-gpio"; | |
257 | reg = <0x18140 0x40>; | |
258 | ngpios = <32>; | |
259 | gpio-controller; | |
260 | #gpio-cells = <2>; | |
261 | interrupt-controller; | |
262 | #interrupt-cells = <2>; | |
263 | interrupts = <0 58 0x4>, <0 59 0x4>, | |
264 | <0 60 0x4>, <0 61 0x4>; | |
265 | }; | |
266 | ||
267 | gpio2: gpio@18180 { | |
268 | compatible = "marvell,orion-gpio"; | |
269 | reg = <0x18180 0x40>; | |
270 | ngpios = <3>; | |
271 | gpio-controller; | |
272 | #gpio-cells = <2>; | |
273 | interrupt-controller; | |
274 | #interrupt-cells = <2>; | |
275 | interrupts = <0 62 0x4>; | |
276 | }; | |
277 | ||
278 | system-controller@18200 { | |
279 | compatible = "marvell,armada-375-system-controller"; | |
280 | reg = <0x18200 0x100>; | |
281 | }; | |
282 | ||
283 | gateclk: clock-gating-control@18220 { | |
284 | compatible = "marvell,armada-375-gating-clock"; | |
285 | reg = <0x18220 0x4>; | |
286 | clocks = <&coreclk 0>; | |
287 | #clock-cells = <1>; | |
288 | }; | |
289 | ||
290 | mbusc: mbus-controller@20000 { | |
291 | compatible = "marvell,mbus-controller"; | |
292 | reg = <0x20000 0x100>, <0x20180 0x20>; | |
293 | }; | |
294 | ||
295 | mpic: interrupt-controller@20000 { | |
296 | compatible = "marvell,mpic"; | |
297 | reg = <0x20a00 0x2d0>, <0x21070 0x58>; | |
298 | #interrupt-cells = <1>; | |
299 | #size-cells = <1>; | |
300 | interrupt-controller; | |
301 | msi-controller; | |
302 | interrupts = <1 15 0x4>; | |
303 | }; | |
304 | ||
305 | timer@20300 { | |
306 | compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; | |
307 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
308 | interrupts-extended = <&gic 0 8 4>, | |
309 | <&gic 0 9 4>, | |
310 | <&gic 0 10 4>, | |
311 | <&gic 0 11 4>, | |
312 | <&mpic 5>, | |
313 | <&mpic 6>; | |
314 | clocks = <&coreclk 0>; | |
315 | }; | |
316 | ||
317 | xor@60800 { | |
318 | compatible = "marvell,orion-xor"; | |
319 | reg = <0x60800 0x100 | |
320 | 0x60A00 0x100>; | |
321 | clocks = <&gateclk 22>; | |
322 | status = "okay"; | |
323 | ||
324 | xor00 { | |
325 | interrupts = <0 22 0x4>; | |
326 | dmacap,memcpy; | |
327 | dmacap,xor; | |
328 | }; | |
329 | xor01 { | |
330 | interrupts = <0 23 0x4>; | |
331 | dmacap,memcpy; | |
332 | dmacap,xor; | |
333 | dmacap,memset; | |
334 | }; | |
335 | }; | |
336 | ||
337 | xor@60900 { | |
338 | compatible = "marvell,orion-xor"; | |
339 | reg = <0x60900 0x100 | |
340 | 0x60b00 0x100>; | |
341 | clocks = <&gateclk 23>; | |
342 | status = "okay"; | |
343 | ||
344 | xor10 { | |
345 | interrupts = <0 65 0x4>; | |
346 | dmacap,memcpy; | |
347 | dmacap,xor; | |
348 | }; | |
349 | xor11 { | |
350 | interrupts = <0 66 0x4>; | |
351 | dmacap,memcpy; | |
352 | dmacap,xor; | |
353 | dmacap,memset; | |
354 | }; | |
355 | }; | |
356 | ||
357 | sata@a0000 { | |
358 | compatible = "marvell,orion-sata"; | |
359 | reg = <0xa0000 0x5000>; | |
360 | interrupts = <0 26 0x4>; | |
361 | clocks = <&gateclk 14>, <&gateclk 20>; | |
362 | clock-names = "0", "1"; | |
363 | status = "disabled"; | |
364 | }; | |
365 | ||
366 | nand@d0000 { | |
367 | compatible = "marvell,armada370-nand"; | |
368 | reg = <0xd0000 0x54>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <1>; | |
371 | interrupts = <0 84 0x4>; | |
372 | clocks = <&gateclk 11>; | |
373 | status = "disabled"; | |
374 | }; | |
375 | ||
376 | mvsdio@d4000 { | |
377 | compatible = "marvell,orion-sdio"; | |
378 | reg = <0xd4000 0x200>; | |
379 | interrupts = <0 25 0x4>; | |
380 | clocks = <&gateclk 17>; | |
381 | bus-width = <4>; | |
382 | cap-sdio-irq; | |
383 | cap-sd-highspeed; | |
384 | cap-mmc-highspeed; | |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | coreclk: mvebu-sar@e8204 { | |
389 | compatible = "marvell,armada-375-core-clock"; | |
390 | reg = <0xe8204 0x04>; | |
391 | #clock-cells = <1>; | |
392 | }; | |
393 | ||
394 | coredivclk: corediv-clock@e8250 { | |
395 | compatible = "marvell,armada-375-corediv-clock"; | |
396 | reg = <0xe8250 0xc>; | |
397 | #clock-cells = <1>; | |
398 | clocks = <&mainpll>; | |
399 | clock-output-names = "nand"; | |
400 | }; | |
401 | }; | |
402 | ||
403 | pcie-controller { | |
404 | compatible = "marvell,armada-370-pcie"; | |
405 | status = "disabled"; | |
406 | device_type = "pci"; | |
407 | ||
408 | #address-cells = <3>; | |
409 | #size-cells = <2>; | |
410 | ||
411 | msi-parent = <&mpic>; | |
412 | bus-range = <0x00 0xff>; | |
413 | ||
414 | ranges = | |
415 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 | |
416 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 | |
417 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ | |
418 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ | |
419 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ | |
420 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; | |
421 | ||
422 | pcie@1,0 { | |
423 | device_type = "pci"; | |
424 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | |
425 | reg = <0x0800 0 0 0 0>; | |
426 | #address-cells = <3>; | |
427 | #size-cells = <2>; | |
428 | #interrupt-cells = <1>; | |
429 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | |
430 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | |
431 | interrupt-map-mask = <0 0 0 0>; | |
432 | interrupt-map = <0 0 0 0 &gic 0 29 0x4>; | |
433 | marvell,pcie-port = <0>; | |
434 | marvell,pcie-lane = <0>; | |
435 | clocks = <&gateclk 5>; | |
436 | status = "disabled"; | |
437 | }; | |
438 | ||
439 | pcie@2,0 { | |
440 | device_type = "pci"; | |
441 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | |
442 | reg = <0x1000 0 0 0 0>; | |
443 | #address-cells = <3>; | |
444 | #size-cells = <2>; | |
445 | #interrupt-cells = <1>; | |
446 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | |
447 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | |
448 | interrupt-map-mask = <0 0 0 0>; | |
449 | interrupt-map = <0 0 0 0 &gic 0 33 0x4>; | |
450 | marvell,pcie-port = <0>; | |
451 | marvell,pcie-lane = <1>; | |
452 | clocks = <&gateclk 6>; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | }; | |
457 | }; | |
458 | }; |