[linux-2.6-block.git] / arch / arm / boot / dts / armada-375.dtsi

/*
 * Device Tree Include file for Marvell Armada 375 family SoC
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 375 family SoC";
	compatible = "marvell,armada375";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-375-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	soc {
		compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl {
				compatible = "marvell,mv88f6720-pinctrl";
				reg = <0x18000 0x24>;

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp14",  "mpp15";
					marvell,function = "i2c0";
				};

				i2c1_pins: i2c1-pins {
					marvell,pins = "mpp61",  "mpp62";
					marvell,function = "i2c1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp0", "mpp1", "mpp2",
						"mpp3", "mpp4", "mpp5",
						"mpp6", "mpp7", "mpp8",
						"mpp9", "mpp10", "mpp11",
						"mpp12", "mpp13";
					marvell,function = "nand";
				};

				sdio_pins: sdio-pins {
					marvell,pins = "mpp24",  "mpp25", "mpp26",
						     "mpp27", "mpp28", "mpp29";
					marvell,function = "sd";
				};

				spi0_pins: spi0-pins {
					marvell,pins = "mpp0",  "mpp1", "mpp4",
						     "mpp5", "mpp8", "mpp9";
					marvell,function = "spi0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-375-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-375-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 0>;
			};

			watchdog@20300 {
				compatible = "marvell,armada-375-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
				clocks = <&coreclk 0>;
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-375-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			usb@54000 {
				compatible = "marvell,orion-ehci";
				reg = <0x54000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			usb3@58000 {
				compatible = "marvell,armada-375-xhci";
				reg = <0x58000 0x20000>,<0x5b880 0x80>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 16>;
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 23>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 14>, <&gateclk 20>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			thermal@e8078 {
				compatible = "marvell,armada375-thermal";
				reg = <0xe8078 0x4>, <0xe807c 0x8>;
				status = "okay";
			};

			coreclk: mvebu-sar@e8204 {
				compatible = "marvell,armada-375-core-clock";
				reg = <0xe8204 0x04>;
				#clock-cells = <1>;
			};

			coredivclk: corediv-clock@e8250 {
				compatible = "marvell,armada-375-corediv-clock";
				reg = <0xe8250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		pcie-controller {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";
			};

		};
	};
};
Commit	Line	Data
4de59085 GC	1	/*
	2	* Device Tree Include file for Marvell Armada 375 family SoC
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	7	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
a2be1561	14	#include "skeleton.dtsi"
f327d43d	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	16	#include <dt-bindings/interrupt-controller/irq.h>
4de59085 GC	17
	18	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	19
	20	/ {
	21	model = "Marvell Armada 375 family SoC";
	22	compatible = "marvell,armada375";
	23
	24	aliases {
	25	gpio0 = &gpio0;
	26	gpio1 = &gpio1;
	27	gpio2 = &gpio2;
	28	};
	29
	30	clocks {
	31	/* 2 GHz fixed main PLL */
	32	mainpll: mainpll {
	33	compatible = "fixed-clock";
	34	#clock-cells = <0>;
	35	clock-frequency = <2000000000>;
	36	};
	37	};
	38
	39	cpus {
	40	#address-cells = <1>;
	41	#size-cells = <0>;
42eae5a4 GC	42	enable-method = "marvell,armada-375-smp";
42eae5a4 GC	43
4de59085 GC	44	cpu@0 {
	45	device_type = "cpu";
	46	compatible = "arm,cortex-a9";
	47	reg = <0>;
	48	};
	49	cpu@1 {
	50	device_type = "cpu";
	51	compatible = "arm,cortex-a9";
	52	reg = <1>;
	53	};
	54	};
	55
	56	soc {
	57	compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
	58	#address-cells = <2>;
	59	#size-cells = <1>;
	60	controller = <&mbusc>;
	61	interrupt-parent = <&gic>;
	62	pcie-mem-aperture = <0xe0000000 0x8000000>;
	63	pcie-io-aperture = <0xe8000000 0x100000>;
	64
	65	bootrom {
	66	compatible = "marvell,bootrom";
	67	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	68	};
	69
	70	devbus-bootcs {
	71	compatible = "marvell,mvebu-devbus";
	72	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	73	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	clocks = <&coreclk 0>;
	77	status = "disabled";
	78	};
	79
	80	devbus-cs0 {
	81	compatible = "marvell,mvebu-devbus";
	82	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	83	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	clocks = <&coreclk 0>;
	87	status = "disabled";
	88	};
	89
	90	devbus-cs1 {
	91	compatible = "marvell,mvebu-devbus";
	92	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	93	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	clocks = <&coreclk 0>;
	97	status = "disabled";
	98	};
	99
	100	devbus-cs2 {
	101	compatible = "marvell,mvebu-devbus";
	102	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	103	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	104	#address-cells = <1>;
	105	#size-cells = <1>;
	106	clocks = <&coreclk 0>;
	107	status = "disabled";
108	};
109
110	devbus-cs3 {
111	compatible = "marvell,mvebu-devbus";
112	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
113	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
114	#address-cells = <1>;
115	#size-cells = <1>;
116	clocks = <&coreclk 0>;
117	status = "disabled";
118	};
119
120	internal-regs {
121	compatible = "simple-bus";
122	#address-cells = <1>;
123	#size-cells = <1>;
124	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
125
126	L2: cache-controller@8000 {
127	compatible = "arm,pl310-cache";
128	reg = <0x8000 0x1000>;
129	cache-unified;
130	cache-level = <2>;
131	};
132
6a8a57f2 TP	133	scu@c000 {
	134	compatible = "arm,cortex-a9-scu";
	135	reg = <0xc000 0x58>;
	136	};
	137
4de59085 GC	138	timer@c600 {
	139	compatible = "arm,cortex-a9-twd-timer";
	140	reg = <0xc600 0x20>;
d11548e3	141	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
4de59085 GC	142	clocks = <&coreclk 2>;
	143	};
	144
	145	gic: interrupt-controller@d000 {
	146	compatible = "arm,cortex-a9-gic";
	147	#interrupt-cells = <3>;
	148	#size-cells = <0>;
	149	interrupt-controller;
	150	reg = <0xd000 0x1000>,
	151	<0xc100 0x100>;
	152	};
	153
	154	spi0: spi@10600 {
	155	compatible = "marvell,orion-spi";
	156	reg = <0x10600 0x50>;
	157	#address-cells = <1>;
	158	#size-cells = <0>;
	159	cell-index = <0>;
d11548e3	160	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	161	clocks = <&coreclk 0>;
	162	status = "disabled";
	163	};
	164
	165	spi1: spi@10680 {
	166	compatible = "marvell,orion-spi";
	167	reg = <0x10680 0x50>;
	168	#address-cells = <1>;
	169	#size-cells = <0>;
	170	cell-index = <1>;
d11548e3	171	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	172	clocks = <&coreclk 0>;
	173	status = "disabled";
	174	};
	175
	176	i2c0: i2c@11000 {
	177	compatible = "marvell,mv64xxx-i2c";
	178	reg = <0x11000 0x20>;
	179	#address-cells = <1>;
	180	#size-cells = <0>;
d11548e3	181	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	182	timeout-ms = <1000>;
	183	clocks = <&coreclk 0>;
	184	status = "disabled";
	185	};
	186
	187	i2c1: i2c@11100 {
	188	compatible = "marvell,mv64xxx-i2c";
	189	reg = <0x11100 0x20>;
	190	#address-cells = <1>;
	191	#size-cells = <0>;
d11548e3	192	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	193	timeout-ms = <1000>;
	194	clocks = <&coreclk 0>;
	195	status = "disabled";
	196	};
	197
	198	serial@12000 {
	199	compatible = "snps,dw-apb-uart";
	200	reg = <0x12000 0x100>;
	201	reg-shift = <2>;
d11548e3	202	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4de59085	203	reg-io-width = <1>;
64939dc5	204	clocks = <&coreclk 0>;
4de59085 GC	205	status = "disabled";
	206	};
	207
	208	serial@12100 {
	209	compatible = "snps,dw-apb-uart";
	210	reg = <0x12100 0x100>;
	211	reg-shift = <2>;
d11548e3	212	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4de59085	213	reg-io-width = <1>;
64939dc5	214	clocks = <&coreclk 0>;
4de59085 GC	215	status = "disabled";
	216	};
	217
	218	pinctrl {
	219	compatible = "marvell,mv88f6720-pinctrl";
	220	reg = <0x18000 0x24>;
	221
	222	i2c0_pins: i2c0-pins {
	223	marvell,pins = "mpp14", "mpp15";
	224	marvell,function = "i2c0";
	225	};
	226
	227	i2c1_pins: i2c1-pins {
	228	marvell,pins = "mpp61", "mpp62";
	229	marvell,function = "i2c1";
	230	};
	231
	232	nand_pins: nand-pins {
	233	marvell,pins = "mpp0", "mpp1", "mpp2",
	234	"mpp3", "mpp4", "mpp5",
	235	"mpp6", "mpp7", "mpp8",
	236	"mpp9", "mpp10", "mpp11",
	237	"mpp12", "mpp13";
	238	marvell,function = "nand";
	239	};
	240
	241	sdio_pins: sdio-pins {
	242	marvell,pins = "mpp24", "mpp25", "mpp26",
	243	"mpp27", "mpp28", "mpp29";
	244	marvell,function = "sd";
	245	};
	246
	247	spi0_pins: spi0-pins {
	248	marvell,pins = "mpp0", "mpp1", "mpp4",
	249	"mpp5", "mpp8", "mpp9";
	250	marvell,function = "spi0";
	251	};
	252	};
	253
	254	gpio0: gpio@18100 {
	255	compatible = "marvell,orion-gpio";
	256	reg = <0x18100 0x40>;
	257	ngpios = <32>;
	258	gpio-controller;
	259	#gpio-cells = <2>;
	260	interrupt-controller;
	261	#interrupt-cells = <2>;
d11548e3 TP	262	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	263	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	264	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	265	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	266	};
	267
	268	gpio1: gpio@18140 {
	269	compatible = "marvell,orion-gpio";
	270	reg = <0x18140 0x40>;
	271	ngpios = <32>;
	272	gpio-controller;
	273	#gpio-cells = <2>;
	274	interrupt-controller;
	275	#interrupt-cells = <2>;
d11548e3 TP	276	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	277	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	278	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	279	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	280	};
	281
	282	gpio2: gpio@18180 {
	283	compatible = "marvell,orion-gpio";
	284	reg = <0x18180 0x40>;
	285	ngpios = <3>;
	286	gpio-controller;
	287	#gpio-cells = <2>;
	288	interrupt-controller;
	289	#interrupt-cells = <2>;
d11548e3	290	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	291	};
	292
	293	system-controller@18200 {
	294	compatible = "marvell,armada-375-system-controller";
	295	reg = <0x18200 0x100>;
	296	};
	297
	298	gateclk: clock-gating-control@18220 {
	299	compatible = "marvell,armada-375-gating-clock";
	300	reg = <0x18220 0x4>;
	301	clocks = <&coreclk 0>;
	302	#clock-cells = <1>;
	303	};
	304
	305	mbusc: mbus-controller@20000 {
	306	compatible = "marvell,mbus-controller";
	307	reg = <0x20000 0x100>, <0x20180 0x20>;
	308	};
	309
	310	mpic: interrupt-controller@20000 {
	311	compatible = "marvell,mpic";
	312	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	313	#interrupt-cells = <1>;
	314	#size-cells = <1>;
	315	interrupt-controller;
	316	msi-controller;
d11548e3	317	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	318	};
	319
	320	timer@20300 {
	321	compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
	322	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	323	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	324	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	325	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	326	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
4de59085 GC	327	<&mpic 5>,
	328	<&mpic 6>;
	329	clocks = <&coreclk 0>;
	330	};
	331
13dacc56 EG	332	watchdog@20300 {
	333	compatible = "marvell,armada-375-wdt";
	334	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
	335	clocks = <&coreclk 0>;
	336	};
	337
42eae5a4 GC	338	cpurst@20800 {
	339	compatible = "marvell,armada-370-cpu-reset";
	340	reg = <0x20800 0x10>;
	341	};
	342
6a8a57f2 TP	343	coherency-fabric@21010 {
	344	compatible = "marvell,armada-375-coherency-fabric";
	345	reg = <0x21010 0x1c>;
	346	};
	347
57dc7971 GC	348	usb@50000 {
	349	compatible = "marvell,orion-ehci";
	350	reg = <0x50000 0x500>;
	351	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	352	clocks = <&gateclk 18>;
	353	status = "disabled";
	354	};
	355
	356	usb@54000 {
	357	compatible = "marvell,orion-ehci";
	358	reg = <0x54000 0x500>;
	359	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	360	clocks = <&gateclk 26>;
	361	status = "disabled";
	362	};
	363
e8f99c5b GC	364	usb3@58000 {
	365	compatible = "marvell,armada-375-xhci";
	366	reg = <0x58000 0x20000>,<0x5b880 0x80>;
	367	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	368	clocks = <&gateclk 16>;
	369	status = "disabled";
	370	};
	371
4de59085 GC	372	xor@60800 {
	373	compatible = "marvell,orion-xor";
	374	reg = <0x60800 0x100
	375	0x60A00 0x100>;
	376	clocks = <&gateclk 22>;
	377	status = "okay";
	378
	379	xor00 {
d11548e3	380	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	381	dmacap,memcpy;
	382	dmacap,xor;
	383	};
	384	xor01 {
d11548e3	385	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	386	dmacap,memcpy;
	387	dmacap,xor;
	388	dmacap,memset;
	389	};
	390	};
	391
	392	xor@60900 {
	393	compatible = "marvell,orion-xor";
	394	reg = <0x60900 0x100
	395	0x60b00 0x100>;
	396	clocks = <&gateclk 23>;
	397	status = "okay";
	398
	399	xor10 {
d11548e3	400	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	401	dmacap,memcpy;
	402	dmacap,xor;
	403	};
	404	xor11 {
d11548e3	405	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	406	dmacap,memcpy;
	407	dmacap,xor;
	408	dmacap,memset;
	409	};
	410	};
	411
	412	sata@a0000 {
	413	compatible = "marvell,orion-sata";
	414	reg = <0xa0000 0x5000>;
d11548e3	415	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	416	clocks = <&gateclk 14>, <&gateclk 20>;
	417	clock-names = "0", "1";
	418	status = "disabled";
	419	};
	420
	421	nand@d0000 {
	422	compatible = "marvell,armada370-nand";
	423	reg = <0xd0000 0x54>;
	424	#address-cells = <1>;
	425	#size-cells = <1>;
d11548e3	426	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	427	clocks = <&gateclk 11>;
	428	status = "disabled";
	429	};
	430
	431	mvsdio@d4000 {
	432	compatible = "marvell,orion-sdio";
	433	reg = <0xd4000 0x200>;
d11548e3	434	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	435	clocks = <&gateclk 17>;
	436	bus-width = <4>;
	437	cap-sdio-irq;
	438	cap-sd-highspeed;
	439	cap-mmc-highspeed;
	440	status = "disabled";
f672e481 EG	441	};
	442
	443	thermal@e8078 {
	444	compatible = "marvell,armada375-thermal";
	445	reg = <0xe8078 0x4>, <0xe807c 0x8>;
	446	status = "okay";
4de59085 GC	447	};
	448
	449	coreclk: mvebu-sar@e8204 {
	450	compatible = "marvell,armada-375-core-clock";
	451	reg = <0xe8204 0x04>;
	452	#clock-cells = <1>;
	453	};
	454
	455	coredivclk: corediv-clock@e8250 {
	456	compatible = "marvell,armada-375-corediv-clock";
	457	reg = <0xe8250 0xc>;
	458	#clock-cells = <1>;
	459	clocks = <&mainpll>;
	460	clock-output-names = "nand";
	461	};
	462	};
	463
	464	pcie-controller {
	465	compatible = "marvell,armada-370-pcie";
	466	status = "disabled";
	467	device_type = "pci";
	468
	469	#address-cells = <3>;
	470	#size-cells = <2>;
	471
	472	msi-parent = <&mpic>;
	473	bus-range = <0x00 0xff>;
	474
	475	ranges =
	476	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	477	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
	478	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
	479	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
	480	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
	481	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
	482
	483	pcie@1,0 {
	484	device_type = "pci";
	485	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	486	reg = <0x0800 0 0 0 0>;
	487	#address-cells = <3>;
	488	#size-cells = <2>;
	489	#interrupt-cells = <1>;
	490	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	491	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	492	interrupt-map-mask = <0 0 0 0>;
d11548e3	493	interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	494	marvell,pcie-port = <0>;
	495	marvell,pcie-lane = <0>;
	496	clocks = <&gateclk 5>;
	497	status = "disabled";
	498	};
	499
	500	pcie@2,0 {
	501	device_type = "pci";
	502	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	503	reg = <0x1000 0 0 0 0>;
	504	#address-cells = <3>;
	505	#size-cells = <2>;
	506	#interrupt-cells = <1>;
	507	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	508	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	509	interrupt-map-mask = <0 0 0 0>;
d11548e3	510	interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4de59085 GC	511	marvell,pcie-port = <0>;
	512	marvell,pcie-lane = <1>;
	513	clocks = <&gateclk 6>;
	514	status = "disabled";
	515	};
	516
	517	};
	518	};
	519	};