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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
15 | * This file contains the definitions that are common to the Armada | |
16 | * 370 and Armada XP SoC. | |
17 | */ | |
18 | ||
19 | /include/ "skeleton.dtsi" | |
20 | ||
21 | / { | |
22 | model = "Marvell Armada 370 and XP SoC"; | |
92ece1cd | 23 | compatible = "marvell,armada-370-xp"; |
9ae6f740 TP |
24 | |
25 | cpus { | |
26 | cpu@0 { | |
27 | compatible = "marvell,sheeva-v7"; | |
28 | }; | |
29 | }; | |
30 | ||
31 | mpic: interrupt-controller@d0020000 { | |
32 | compatible = "marvell,mpic"; | |
33 | #interrupt-cells = <1>; | |
34 | #address-cells = <1>; | |
35 | #size-cells = <1>; | |
36 | interrupt-controller; | |
37 | }; | |
38 | ||
009f1315 GC |
39 | coherency-fabric@d0020200 { |
40 | compatible = "marvell,coherency-fabric"; | |
e60304f8 GC |
41 | reg = <0xd0020200 0xb0>, |
42 | <0xd0021810 0x1c>; | |
009f1315 GC |
43 | }; |
44 | ||
9ae6f740 TP |
45 | soc { |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | compatible = "simple-bus"; | |
49 | interrupt-parent = <&mpic>; | |
50 | ranges; | |
51 | ||
52 | serial@d0012000 { | |
53 | compatible = "ns16550"; | |
54 | reg = <0xd0012000 0x100>; | |
55 | reg-shift = <2>; | |
56 | interrupts = <41>; | |
57 | status = "disabled"; | |
58 | }; | |
59 | serial@d0012100 { | |
60 | compatible = "ns16550"; | |
61 | reg = <0xd0012100 0x100>; | |
62 | reg-shift = <2>; | |
63 | interrupts = <42>; | |
64 | status = "disabled"; | |
65 | }; | |
66 | ||
67 | timer@d0020300 { | |
68 | compatible = "marvell,armada-370-xp-timer"; | |
69 | reg = <0xd0020300 0x30>; | |
70 | interrupts = <37>, <38>, <39>, <40>; | |
307c2bf4 | 71 | clocks = <&coreclk 2>; |
9ae6f740 | 72 | }; |
5b40baee TP |
73 | |
74 | addr-decoding@d0020000 { | |
75 | compatible = "marvell,armada-addr-decoding-controller"; | |
76 | reg = <0xd0020000 0x258>; | |
77 | }; | |
a6a6de1a GC |
78 | |
79 | sata@d00a0000 { | |
80 | compatible = "marvell,orion-sata"; | |
81 | reg = <0xd00a0000 0x2400>; | |
82 | interrupts = <55>; | |
83 | clocks = <&gateclk 15>, <&gateclk 30>; | |
84 | clock-names = "0", "1"; | |
85 | status = "disabled"; | |
86 | }; | |
87 | ||
323c1010 TP |
88 | mdio { |
89 | #address-cells = <1>; | |
90 | #size-cells = <0>; | |
91 | compatible = "marvell,orion-mdio"; | |
92 | reg = <0xd0072004 0x4>; | |
93 | }; | |
94 | ||
95 | ethernet@d0070000 { | |
96 | compatible = "marvell,armada-370-neta"; | |
97 | reg = <0xd0070000 0x2500>; | |
98 | interrupts = <8>; | |
4aa935a2 | 99 | clocks = <&gateclk 4>; |
323c1010 TP |
100 | status = "disabled"; |
101 | }; | |
102 | ||
103 | ethernet@d0074000 { | |
104 | compatible = "marvell,armada-370-neta"; | |
105 | reg = <0xd0074000 0x2500>; | |
106 | interrupts = <10>; | |
4aa935a2 | 107 | clocks = <&gateclk 3>; |
323c1010 TP |
108 | status = "disabled"; |
109 | }; | |
539eb5bc NI |
110 | |
111 | i2c0: i2c@d0011000 { | |
112 | compatible = "marvell,mv64xxx-i2c"; | |
113 | reg = <0xd0011000 0x20>; | |
114 | #address-cells = <1>; | |
115 | #size-cells = <0>; | |
116 | interrupts = <31>; | |
117 | timeout-ms = <1000>; | |
118 | clocks = <&coreclk 0>; | |
119 | status = "disabled"; | |
120 | }; | |
121 | ||
122 | i2c1: i2c@d0011100 { | |
123 | compatible = "marvell,mv64xxx-i2c"; | |
124 | reg = <0xd0011100 0x20>; | |
125 | #address-cells = <1>; | |
126 | #size-cells = <0>; | |
127 | interrupts = <32>; | |
128 | timeout-ms = <1000>; | |
129 | clocks = <&coreclk 0>; | |
130 | status = "disabled"; | |
131 | }; | |
9ae6f740 TP |
132 | }; |
133 | }; | |
134 |