[linux-2.6-block.git] / arch / arm / boot / dts / armada-370-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

/include/ "skeleton64.dtsi"

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		eth0 = &eth0;
		eth1 = &eth1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	soc {
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&mpic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				reg = <0x10600 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <30>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,orion-spi";
				reg = <0x10680 0x28>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <92>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				status = "disabled";
			};
			serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				status = "disabled";
			};

			coredivclk: corediv-clock@18740 {
				compatible = "marvell,armada-370-corediv-clock";
				reg = <0x18740 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20000 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21810 0x1c>;
			};

			timer@20300 {
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
			};

			eth1: ethernet@74000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <113>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};
 };
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
	15	* This file contains the definitions that are common to the Armada
	16	* 370 and Armada XP SoC.
	17	*/
	18
74898364	19	/include/ "skeleton64.dtsi"
9ae6f740	20
5e12a613 EG	21	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
5e12a613 EG	22
9ae6f740 TP	23	/ {
9ae6f740 TP	24	model = "Marvell Armada 370 and XP SoC";
92ece1cd	25	compatible = "marvell,armada-370-xp";
9ae6f740	26
be5a9389 WT	27	aliases {
	28	eth0 = &eth0;
	29	eth1 = &eth1;
	30	};
	31
9ae6f740	32	cpus {
7a7ed290 LP	33	#address-cells = <1>;
7a7ed290 LP	34	#size-cells = <0>;
9ae6f740 TP	35	cpu@0 {
9ae6f740 TP	36	compatible = "marvell,sheeva-v7";
7a7ed290 LP	37	device_type = "cpu";
7a7ed290 LP	38	reg = <0>;
9ae6f740 TP	39	};
	40	};
	41
9ae6f740	42	soc {
5e12a613	43	#address-cells = <2>;
9ae6f740	44	#size-cells = <1>;
5e12a613	45	controller = <&mbusc>;
9ae6f740	46	interrupt-parent = <&mpic>;
14fd8ed0 EG	47	pcie-mem-aperture = <0xe0000000 0x8000000>;
14fd8ed0 EG	48	pcie-io-aperture = <0xe8000000 0x100000>;
9ae6f740	49
de1af8d4 EG	50	devbus-bootcs {
	51	compatible = "marvell,mvebu-devbus";
	52	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	53	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	clocks = <&coreclk 0>;
	57	status = "disabled";
	58	};
	59
	60	devbus-cs0 {
	61	compatible = "marvell,mvebu-devbus";
	62	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	63	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	clocks = <&coreclk 0>;
	67	status = "disabled";
	68	};
	69
	70	devbus-cs1 {
	71	compatible = "marvell,mvebu-devbus";
	72	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	73	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	clocks = <&coreclk 0>;
	77	status = "disabled";
	78	};
	79
	80	devbus-cs2 {
	81	compatible = "marvell,mvebu-devbus";
	82	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	83	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	clocks = <&coreclk 0>;
	87	status = "disabled";
	88	};
	89
	90	devbus-cs3 {
	91	compatible = "marvell,mvebu-devbus";
	92	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	93	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	clocks = <&coreclk 0>;
	97	status = "disabled";
	98	};
	99
467f54b2 GC	100	internal-regs {
	101	compatible = "simple-bus";
	102	#address-cells = <1>;
	103	#size-cells = <1>;
5e12a613 EG	104	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
5e12a613 EG	105
a095b1c7 JC	106	rtc@10300 {
	107	compatible = "marvell,orion-rtc";
	108	reg = <0x10300 0x20>;
	109	interrupts = <50>;
5e12a613	110	};
467f54b2	111
a095b1c7 JC	112	spi0: spi@10600 {
	113	compatible = "marvell,orion-spi";
	114	reg = <0x10600 0x28>;
	115	#address-cells = <1>;
	116	#size-cells = <0>;
	117	cell-index = <0>;
	118	interrupts = <30>;
	119	clocks = <&coreclk 0>;
	120	status = "disabled";
467f54b2	121	};
b18ea4dc	122
a095b1c7 JC	123	spi1: spi@10680 {
	124	compatible = "marvell,orion-spi";
	125	reg = <0x10680 0x28>;
	126	#address-cells = <1>;
	127	#size-cells = <0>;
	128	cell-index = <1>;
	129	interrupts = <92>;
	130	clocks = <&coreclk 0>;
	131	status = "disabled";
	132	};
	133
	134	i2c0: i2c@11000 {
	135	compatible = "marvell,mv64xxx-i2c";
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	interrupts = <31>;
	139	timeout-ms = <1000>;
	140	clocks = <&coreclk 0>;
	141	status = "disabled";
	142	};
	143
	144	i2c1: i2c@11100 {
	145	compatible = "marvell,mv64xxx-i2c";
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148	interrupts = <32>;
	149	timeout-ms = <1000>;
	150	clocks = <&coreclk 0>;
	151	status = "disabled";
467f54b2	152	};
b18ea4dc	153
467f54b2	154	serial@12000 {
b24212fb	155	compatible = "snps,dw-apb-uart";
82a68267	156	reg = <0x12000 0x100>;
9ae6f740 TP	157	reg-shift = <2>;
9ae6f740 TP	158	interrupts = <41>;
e366154f	159	reg-io-width = <1>;
9ae6f740	160	status = "disabled";
467f54b2 GC	161	};
467f54b2 GC	162	serial@12100 {
b24212fb	163	compatible = "snps,dw-apb-uart";
82a68267	164	reg = <0x12100 0x100>;
9ae6f740 TP	165	reg-shift = <2>;
9ae6f740 TP	166	interrupts = <42>;
e366154f	167	reg-io-width = <1>;
9ae6f740	168	status = "disabled";
467f54b2 GC	169	};
467f54b2 GC	170
f039dfb5 EG	171	coredivclk: corediv-clock@18740 {
	172	compatible = "marvell,armada-370-corediv-clock";
	173	reg = <0x18740 0xc>;
	174	#clock-cells = <1>;
	175	clocks = <&mainpll>;
	176	clock-output-names = "nand";
	177	};
	178
a095b1c7 JC	179	mbusc: mbus-controller@20000 {
	180	compatible = "marvell,mbus-controller";
	181	reg = <0x20000 0x100>, <0x20180 0x20>;
	182	};
	183
	184	mpic: interrupt-controller@20000 {
	185	compatible = "marvell,mpic";
	186	#interrupt-cells = <1>;
	187	#size-cells = <1>;
	188	interrupt-controller;
	189	msi-controller;
	190	};
	191
	192	coherency-fabric@20200 {
	193	compatible = "marvell,coherency-fabric";
	194	reg = <0x20200 0xb0>, <0x21810 0x1c>;
	195	};
	196
467f54b2	197	timer@20300 {
467f54b2 GC	198	reg = <0x20300 0x30>, <0x21040 0x30>;
467f54b2 GC	199	interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
467f54b2 GC	200	};
467f54b2 GC	201
a095b1c7 JC	202	usb@50000 {
	203	compatible = "marvell,orion-ehci";
	204	reg = <0x50000 0x500>;
	205	interrupts = <45>;
467f54b2 GC	206	status = "disabled";
467f54b2 GC	207	};
a6a6de1a	208
a095b1c7 JC	209	usb@51000 {
	210	compatible = "marvell,orion-ehci";
	211	reg = <0x51000 0x500>;
	212	interrupts = <46>;
	213	status = "disabled";
467f54b2	214	};
323c1010	215
be5a9389	216	eth0: ethernet@70000 {
323c1010	217	compatible = "marvell,armada-370-neta";
cf8088c5	218	reg = <0x70000 0x4000>;
323c1010	219	interrupts = <8>;
4aa935a2	220	clocks = <&gateclk 4>;
323c1010	221	status = "disabled";
467f54b2	222	};
323c1010	223
a095b1c7 JC	224	mdio {
	225	#address-cells = <1>;
	226	#size-cells = <0>;
	227	compatible = "marvell,orion-mdio";
	228	reg = <0x72004 0x4>;
	229	};
	230
be5a9389	231	eth1: ethernet@74000 {
323c1010	232	compatible = "marvell,armada-370-neta";
cf8088c5	233	reg = <0x74000 0x4000>;
323c1010	234	interrupts = <10>;
4aa935a2	235	clocks = <&gateclk 3>;
323c1010	236	status = "disabled";
467f54b2 GC	237	};
467f54b2 GC	238
a095b1c7 JC	239	sata@a0000 {
	240	compatible = "marvell,orion-sata";
	241	reg = <0xa0000 0x5000>;
	242	interrupts = <55>;
	243	clocks = <&gateclk 15>, <&gateclk 30>;
	244	clock-names = "0", "1";
467f54b2 GC	245	status = "disabled";
	246	};
	247
a095b1c7 JC	248	nand@d0000 {
	249	compatible = "marvell,armada370-nand";
	250	reg = <0xd0000 0x54>;
467f54b2	251	#address-cells = <1>;
a095b1c7 JC	252	#size-cells = <1>;
	253	interrupts = <113>;
	254	clocks = <&coredivclk 0>;
467f54b2 GC	255	status = "disabled";
	256	};
	257
467f54b2 GC	258	mvsdio@d4000 {
	259	compatible = "marvell,orion-sdio";
	260	reg = <0xd4000 0x200>;
	261	interrupts = <54>;
	262	clocks = <&gateclk 17>;
d87b5fbb SB	263	bus-width = <4>;
	264	cap-sdio-irq;
	265	cap-sd-highspeed;
	266	cap-mmc-highspeed;
467f54b2 GC	267	status = "disabled";
467f54b2 GC	268	};
3d76e1f3	269	};
9ae6f740	270	};
4675cf57 EG	271
	272	clocks {
	273	/* 2 GHz fixed main PLL */
	274	mainpll: mainpll {
	275	compatible = "fixed-clock";
	276	#clock-cells = <0>;
	277	clock-frequency = <2000000000>;
	278	};
	279	};
467f54b2	280	};