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9ae6f740 TP |
1 | /* |
2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | * | |
15 | * This file contains the definitions that are common to the Armada | |
16 | * 370 and Armada XP SoC. | |
17 | */ | |
18 | ||
19 | /include/ "skeleton.dtsi" | |
20 | ||
21 | / { | |
22 | model = "Marvell Armada 370 and XP SoC"; | |
92ece1cd | 23 | compatible = "marvell,armada-370-xp"; |
9ae6f740 TP |
24 | |
25 | cpus { | |
26 | cpu@0 { | |
27 | compatible = "marvell,sheeva-v7"; | |
28 | }; | |
29 | }; | |
30 | ||
31 | mpic: interrupt-controller@d0020000 { | |
32 | compatible = "marvell,mpic"; | |
33 | #interrupt-cells = <1>; | |
34 | #address-cells = <1>; | |
35 | #size-cells = <1>; | |
36 | interrupt-controller; | |
37 | }; | |
38 | ||
009f1315 GC |
39 | coherency-fabric@d0020200 { |
40 | compatible = "marvell,coherency-fabric"; | |
e60304f8 GC |
41 | reg = <0xd0020200 0xb0>, |
42 | <0xd0021810 0x1c>; | |
009f1315 GC |
43 | }; |
44 | ||
9ae6f740 TP |
45 | soc { |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | compatible = "simple-bus"; | |
49 | interrupt-parent = <&mpic>; | |
50 | ranges; | |
51 | ||
52 | serial@d0012000 { | |
b24212fb | 53 | compatible = "snps,dw-apb-uart"; |
9ae6f740 TP |
54 | reg = <0xd0012000 0x100>; |
55 | reg-shift = <2>; | |
56 | interrupts = <41>; | |
b24212fb | 57 | reg-io-width = <4>; |
9ae6f740 TP |
58 | status = "disabled"; |
59 | }; | |
60 | serial@d0012100 { | |
b24212fb | 61 | compatible = "snps,dw-apb-uart"; |
9ae6f740 TP |
62 | reg = <0xd0012100 0x100>; |
63 | reg-shift = <2>; | |
64 | interrupts = <42>; | |
b24212fb | 65 | reg-io-width = <4>; |
9ae6f740 TP |
66 | status = "disabled"; |
67 | }; | |
68 | ||
69 | timer@d0020300 { | |
70 | compatible = "marvell,armada-370-xp-timer"; | |
71 | reg = <0xd0020300 0x30>; | |
72 | interrupts = <37>, <38>, <39>, <40>; | |
307c2bf4 | 73 | clocks = <&coreclk 2>; |
9ae6f740 | 74 | }; |
5b40baee TP |
75 | |
76 | addr-decoding@d0020000 { | |
77 | compatible = "marvell,armada-addr-decoding-controller"; | |
78 | reg = <0xd0020000 0x258>; | |
79 | }; | |
a6a6de1a GC |
80 | |
81 | sata@d00a0000 { | |
82 | compatible = "marvell,orion-sata"; | |
83 | reg = <0xd00a0000 0x2400>; | |
84 | interrupts = <55>; | |
85 | clocks = <&gateclk 15>, <&gateclk 30>; | |
86 | clock-names = "0", "1"; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
323c1010 TP |
90 | mdio { |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
93 | compatible = "marvell,orion-mdio"; | |
94 | reg = <0xd0072004 0x4>; | |
95 | }; | |
96 | ||
97 | ethernet@d0070000 { | |
98 | compatible = "marvell,armada-370-neta"; | |
99 | reg = <0xd0070000 0x2500>; | |
100 | interrupts = <8>; | |
4aa935a2 | 101 | clocks = <&gateclk 4>; |
323c1010 TP |
102 | status = "disabled"; |
103 | }; | |
104 | ||
105 | ethernet@d0074000 { | |
106 | compatible = "marvell,armada-370-neta"; | |
107 | reg = <0xd0074000 0x2500>; | |
108 | interrupts = <10>; | |
4aa935a2 | 109 | clocks = <&gateclk 3>; |
323c1010 TP |
110 | status = "disabled"; |
111 | }; | |
539eb5bc NI |
112 | |
113 | i2c0: i2c@d0011000 { | |
114 | compatible = "marvell,mv64xxx-i2c"; | |
115 | reg = <0xd0011000 0x20>; | |
116 | #address-cells = <1>; | |
117 | #size-cells = <0>; | |
118 | interrupts = <31>; | |
119 | timeout-ms = <1000>; | |
120 | clocks = <&coreclk 0>; | |
121 | status = "disabled"; | |
122 | }; | |
123 | ||
124 | i2c1: i2c@d0011100 { | |
125 | compatible = "marvell,mv64xxx-i2c"; | |
126 | reg = <0xd0011100 0x20>; | |
127 | #address-cells = <1>; | |
128 | #size-cells = <0>; | |
129 | interrupts = <32>; | |
130 | timeout-ms = <1000>; | |
131 | clocks = <&coreclk 0>; | |
132 | status = "disabled"; | |
133 | }; | |
9ae6f740 TP |
134 | }; |
135 | }; | |
136 |