projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ae6f740 TP |
1 | /* |
| 2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Marvell | |
| 5 | * | |
| 6 | * Lior Amsalem <alior@marvell.com> | |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
| 10 | * | |
| 11 | * This file is licensed under the terms of the GNU General Public | |
| 12 | * License version 2. This program is licensed "as is" without any | |
| 13 | * warranty of any kind, whether express or implied. | |
| 14 | * | |
| 15 | * This file contains the definitions that are common to the Armada | |
| 16 | * 370 and Armada XP SoC. | |
| 17 | */ | |
| 18 | ||
| 74898364 | 19 | /include/ "skeleton64.dtsi" |
| 9ae6f740 TP |
20 | |
| 21 | / { | |
| 22 | model = "Marvell Armada 370 and XP SoC"; | |
| 92ece1cd | 23 | compatible = "marvell,armada-370-xp"; |
| 9ae6f740 TP |
24 | |
| 25 | cpus { | |
| 26 | cpu@0 { | |
| 27 | compatible = "marvell,sheeva-v7"; | |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 9ae6f740 TP |
31 | soc { |
| 32 | #address-cells = <1>; | |
| 33 | #size-cells = <1>; | |
| 34 | compatible = "simple-bus"; | |
| 35 | interrupt-parent = <&mpic>; | |
| 74898364 | 36 | ranges = <0 0 0xd0000000 0x100000>; |
| 9ae6f740 | 37 | |
| 467f54b2 GC |
38 | internal-regs { |
| 39 | compatible = "simple-bus"; | |
| 40 | #address-cells = <1>; | |
| 41 | #size-cells = <1>; | |
| 42 | ranges; | |
| 43 | ||
| 44 | mpic: interrupt-controller@20000 { | |
| 82a68267 GC |
45 | compatible = "marvell,mpic"; |
| 46 | #interrupt-cells = <1>; | |
| 47 | #size-cells = <1>; | |
| 48 | interrupt-controller; | |
| 467f54b2 | 49 | }; |
| b18ea4dc | 50 | |
| 467f54b2 | 51 | coherency-fabric@20200 { |
| 82a68267 | 52 | compatible = "marvell,coherency-fabric"; |
| 467f54b2 GC |
53 | reg = <0x20200 0xb0>, <0x21810 0x1c>; |
| 54 | }; | |
| b18ea4dc | 55 | |
| 467f54b2 | 56 | serial@12000 { |
| b24212fb | 57 | compatible = "snps,dw-apb-uart"; |
| 82a68267 | 58 | reg = <0x12000 0x100>; |
| 9ae6f740 TP |
59 | reg-shift = <2>; |
| 60 | interrupts = <41>; | |
| e366154f | 61 | reg-io-width = <1>; |
| 9ae6f740 | 62 | status = "disabled"; |
| 467f54b2 GC |
63 | }; |
| 64 | serial@12100 { | |
| b24212fb | 65 | compatible = "snps,dw-apb-uart"; |
| 82a68267 | 66 | reg = <0x12100 0x100>; |
| 9ae6f740 TP |
67 | reg-shift = <2>; |
| 68 | interrupts = <42>; | |
| e366154f | 69 | reg-io-width = <1>; |
| 9ae6f740 | 70 | status = "disabled"; |
| 467f54b2 GC |
71 | }; |
| 72 | ||
| 73 | timer@20300 { | |
| 74 | compatible = "marvell,armada-370-xp-timer"; | |
| 75 | reg = <0x20300 0x30>, <0x21040 0x30>; | |
| 76 | interrupts = <37>, <38>, <39>, <40>, <5>, <6>; | |
| 77 | clocks = <&coreclk 2>; | |
| 78 | }; | |
| 79 | ||
| 80 | sata@a0000 { | |
| 81 | compatible = "marvell,orion-sata"; | |
| 82 | reg = <0xa0000 0x2400>; | |
| 83 | interrupts = <55>; | |
| 84 | clocks = <&gateclk 15>, <&gateclk 30>; | |
| 85 | clock-names = "0", "1"; | |
| 86 | status = "disabled"; | |
| 87 | }; | |
| a6a6de1a | 88 | |
| 467f54b2 GC |
89 | mdio { |
| 90 | #address-cells = <1>; | |
| 91 | #size-cells = <0>; | |
| 92 | compatible = "marvell,orion-mdio"; | |
| 93 | reg = <0x72004 0x4>; | |
| 94 | }; | |
| 323c1010 | 95 | |
| 467f54b2 | 96 | ethernet@70000 { |
| 323c1010 | 97 | compatible = "marvell,armada-370-neta"; |
| 82a68267 | 98 | reg = <0x70000 0x2500>; |
| 323c1010 | 99 | interrupts = <8>; |
| 4aa935a2 | 100 | clocks = <&gateclk 4>; |
| 323c1010 | 101 | status = "disabled"; |
| 467f54b2 | 102 | }; |
| 323c1010 | 103 | |
| 467f54b2 | 104 | ethernet@74000 { |
| 323c1010 | 105 | compatible = "marvell,armada-370-neta"; |
| 82a68267 | 106 | reg = <0x74000 0x2500>; |
| 323c1010 | 107 | interrupts = <10>; |
| 4aa935a2 | 108 | clocks = <&gateclk 3>; |
| 323c1010 | 109 | status = "disabled"; |
| 467f54b2 GC |
110 | }; |
| 111 | ||
| 112 | i2c0: i2c@11000 { | |
| 113 | compatible = "marvell,mv64xxx-i2c"; | |
| 114 | reg = <0x11000 0x20>; | |
| 115 | #address-cells = <1>; | |
| 116 | #size-cells = <0>; | |
| 117 | interrupts = <31>; | |
| 118 | timeout-ms = <1000>; | |
| 119 | clocks = <&coreclk 0>; | |
| 120 | status = "disabled"; | |
| 121 | }; | |
| 122 | ||
| 123 | i2c1: i2c@11100 { | |
| 124 | compatible = "marvell,mv64xxx-i2c"; | |
| 125 | reg = <0x11100 0x20>; | |
| 126 | #address-cells = <1>; | |
| 127 | #size-cells = <0>; | |
| 128 | interrupts = <32>; | |
| 129 | timeout-ms = <1000>; | |
| 130 | clocks = <&coreclk 0>; | |
| 131 | status = "disabled"; | |
| 132 | }; | |
| 133 | ||
| 134 | rtc@10300 { | |
| 135 | compatible = "marvell,orion-rtc"; | |
| 136 | reg = <0x10300 0x20>; | |
| 137 | interrupts = <50>; | |
| 138 | }; | |
| 139 | ||
| 140 | mvsdio@d4000 { | |
| 141 | compatible = "marvell,orion-sdio"; | |
| 142 | reg = <0xd4000 0x200>; | |
| 143 | interrupts = <54>; | |
| 144 | clocks = <&gateclk 17>; | |
| d87b5fbb SB |
145 | bus-width = <4>; |
| 146 | cap-sdio-irq; | |
| 147 | cap-sd-highspeed; | |
| 148 | cap-mmc-highspeed; | |
| 467f54b2 GC |
149 | status = "disabled"; |
| 150 | }; | |
| b2bb806f | 151 | |
| 467f54b2 GC |
152 | usb@50000 { |
| 153 | compatible = "marvell,orion-ehci"; | |
| 154 | reg = <0x50000 0x500>; | |
| 155 | interrupts = <45>; | |
| 156 | status = "disabled"; | |
| 157 | }; | |
| d5dc035e | 158 | |
| 467f54b2 GC |
159 | usb@51000 { |
| 160 | compatible = "marvell,orion-ehci"; | |
| 161 | reg = <0x51000 0x500>; | |
| 162 | interrupts = <46>; | |
| 163 | status = "disabled"; | |
| 164 | }; | |
| 165 | ||
| 166 | spi0: spi@10600 { | |
| 167 | compatible = "marvell,orion-spi"; | |
| 168 | reg = <0x10600 0x28>; | |
| 169 | #address-cells = <1>; | |
| 170 | #size-cells = <0>; | |
| 171 | cell-index = <0>; | |
| 172 | interrupts = <30>; | |
| 173 | clocks = <&coreclk 0>; | |
| 174 | status = "disabled"; | |
| 175 | }; | |
| 176 | ||
| 177 | spi1: spi@10680 { | |
| 178 | compatible = "marvell,orion-spi"; | |
| 179 | reg = <0x10680 0x28>; | |
| 180 | #address-cells = <1>; | |
| 181 | #size-cells = <0>; | |
| 182 | cell-index = <1>; | |
| 183 | interrupts = <92>; | |
| 184 | clocks = <&coreclk 0>; | |
| 185 | status = "disabled"; | |
| 186 | }; | |
| 3d76e1f3 | 187 | |
| 467f54b2 GC |
188 | devbus-bootcs@10400 { |
| 189 | compatible = "marvell,mvebu-devbus"; | |
| 190 | reg = <0x10400 0x8>; | |
| 191 | #address-cells = <1>; | |
| 192 | #size-cells = <1>; | |
| 193 | clocks = <&coreclk 0>; | |
| 194 | status = "disabled"; | |
| 195 | }; | |
| 3d76e1f3 | 196 | |
| 467f54b2 GC |
197 | devbus-cs0@10408 { |
| 198 | compatible = "marvell,mvebu-devbus"; | |
| 199 | reg = <0x10408 0x8>; | |
| 200 | #address-cells = <1>; | |
| 201 | #size-cells = <1>; | |
| 202 | clocks = <&coreclk 0>; | |
| 203 | status = "disabled"; | |
| 204 | }; | |
| 3d76e1f3 | 205 | |
| 467f54b2 GC |
206 | devbus-cs1@10410 { |
| 207 | compatible = "marvell,mvebu-devbus"; | |
| 208 | reg = <0x10410 0x8>; | |
| 209 | #address-cells = <1>; | |
| 210 | #size-cells = <1>; | |
| 211 | clocks = <&coreclk 0>; | |
| 212 | status = "disabled"; | |
| 213 | }; | |
| 3d76e1f3 | 214 | |
| 467f54b2 GC |
215 | devbus-cs2@10418 { |
| 216 | compatible = "marvell,mvebu-devbus"; | |
| 217 | reg = <0x10418 0x8>; | |
| 218 | #address-cells = <1>; | |
| 219 | #size-cells = <1>; | |
| 220 | clocks = <&coreclk 0>; | |
| 221 | status = "disabled"; | |
| 222 | }; | |
| 3d76e1f3 | 223 | |
| 467f54b2 GC |
224 | devbus-cs3@10420 { |
| 225 | compatible = "marvell,mvebu-devbus"; | |
| 226 | reg = <0x10420 0x8>; | |
| 227 | #address-cells = <1>; | |
| 228 | #size-cells = <1>; | |
| 229 | clocks = <&coreclk 0>; | |
| 230 | status = "disabled"; | |
| 231 | }; | |
| 3d76e1f3 | 232 | }; |
| 9ae6f740 | 233 | }; |
| 467f54b2 | 234 | }; |