[linux-2.6-block.git] / arch / arm / boot / dts / armada-370-xp.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&mpic>;
		pcie-mem-aperture = <0xf8000000 0x7e00000>;
		pcie-io-aperture  = <0xffe00000 0x100000>;

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			rtc: rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pin-ctrl@18000 {
				reg = <0x18000 0x38>;
			};

			coredivclk: corediv-clock@18740 {
				compatible = "marvell,armada-370-corediv-clock";
				reg = <0x18740 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			coherencyfab: coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21010 0x1c>;
			};

			timer: timer@20300 {
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
			};

			watchdog: watchdog@20300 {
				reg = <0x20300 0x34>, <0x20704 0x4>;
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x8>;
			};

			pmsu: pmsu@22000 {
				compatible = "marvell,armada-370-pmsu";
				reg = <0x22000 0x1000>;
			};

			usb0: usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb1: usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			eth0: ethernet@70000 {
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			eth1: ethernet@74000 {
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			sata: sata@a0000 {
				compatible = "marvell,armada-370-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <113>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdio: mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};
		};

		spi0: spi@10600 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <30>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <92>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};
 };
Commit	Line	Data
69f5689b	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9ae6f740 TP	2	/*
	3	* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
	4	*
	5	* Copyright (C) 2012 Marvell
	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	* Ben Dooks <ben.dooks@codethink.co.uk>
	11	*
9ae6f740 TP	12	* This file contains the definitions that are common to the Armada
	13	* 370 and Armada XP SoC.
	14	*/
	15
5e12a613 EG	16	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
5e12a613 EG	17
9ae6f740 TP	18	/ {
9ae6f740 TP	19	model = "Marvell Armada 370 and XP SoC";
92ece1cd	20	compatible = "marvell,armada-370-xp";
9ae6f740	21
be5a9389	22	aliases {
bf6acf16 TP	23	serial0 = &uart0;
bf6acf16 TP	24	serial1 = &uart1;
be5a9389 WT	25	};
be5a9389 WT	26
9ae6f740	27	cpus {
7a7ed290 LP	28	#address-cells = <1>;
7a7ed290 LP	29	#size-cells = <0>;
9ae6f740 TP	30	cpu@0 {
9ae6f740 TP	31	compatible = "marvell,sheeva-v7";
7a7ed290 LP	32	device_type = "cpu";
7a7ed290 LP	33	reg = <0>;
9ae6f740 TP	34	};
	35	};
	36
a87cd07b MR	37	pmu {
	38	compatible = "arm,cortex-a9-pmu";
	39	interrupts-extended = <&mpic 3>;
	40	};
	41
9ae6f740	42	soc {
5e12a613	43	#address-cells = <2>;
9ae6f740	44	#size-cells = <1>;
5e12a613	45	controller = <&mbusc>;
9ae6f740	46	interrupt-parent = <&mpic>;
46febc63 TP	47	pcie-mem-aperture = <0xf8000000 0x7e00000>;
46febc63 TP	48	pcie-io-aperture = <0xffe00000 0x100000>;
9ae6f740	49
11f7135b	50	devbus_bootcs: devbus-bootcs {
de1af8d4 EG	51	compatible = "marvell,mvebu-devbus";
	52	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	53	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	clocks = <&coreclk 0>;
	57	status = "disabled";
	58	};
	59
11f7135b	60	devbus_cs0: devbus-cs0 {
de1af8d4 EG	61	compatible = "marvell,mvebu-devbus";
	62	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	63	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	clocks = <&coreclk 0>;
	67	status = "disabled";
	68	};
	69
11f7135b	70	devbus_cs1: devbus-cs1 {
de1af8d4 EG	71	compatible = "marvell,mvebu-devbus";
	72	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	73	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	clocks = <&coreclk 0>;
	77	status = "disabled";
	78	};
	79
11f7135b	80	devbus_cs2: devbus-cs2 {
de1af8d4 EG	81	compatible = "marvell,mvebu-devbus";
	82	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	83	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	clocks = <&coreclk 0>;
	87	status = "disabled";
	88	};
	89
11f7135b	90	devbus_cs3: devbus-cs3 {
de1af8d4 EG	91	compatible = "marvell,mvebu-devbus";
	92	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	93	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	clocks = <&coreclk 0>;
	97	status = "disabled";
	98	};
	99
467f54b2 GC	100	internal-regs {
	101	compatible = "simple-bus";
	102	#address-cells = <1>;
	103	#size-cells = <1>;
5e12a613 EG	104	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
5e12a613 EG	105
11f7135b	106	rtc: rtc@10300 {
a095b1c7 JC	107	compatible = "marvell,orion-rtc";
	108	reg = <0x10300 0x20>;
	109	interrupts = <50>;
5e12a613	110	};
467f54b2	111
a095b1c7 JC	112	i2c0: i2c@11000 {
	113	compatible = "marvell,mv64xxx-i2c";
	114	#address-cells = <1>;
	115	#size-cells = <0>;
	116	interrupts = <31>;
	117	timeout-ms = <1000>;
	118	clocks = <&coreclk 0>;
	119	status = "disabled";
	120	};
	121
	122	i2c1: i2c@11100 {
	123	compatible = "marvell,mv64xxx-i2c";
	124	#address-cells = <1>;
	125	#size-cells = <0>;
	126	interrupts = <32>;
	127	timeout-ms = <1000>;
	128	clocks = <&coreclk 0>;
	129	status = "disabled";
467f54b2	130	};
b18ea4dc	131
181d9b28	132	uart0: serial@12000 {
b24212fb	133	compatible = "snps,dw-apb-uart";
82a68267	134	reg = <0x12000 0x100>;
9ae6f740 TP	135	reg-shift = <2>;
9ae6f740 TP	136	interrupts = <41>;
e366154f	137	reg-io-width = <1>;
64939dc5	138	clocks = <&coreclk 0>;
9ae6f740	139	status = "disabled";
467f54b2	140	};
181d9b28 AE	141
181d9b28 AE	142	uart1: serial@12100 {
b24212fb	143	compatible = "snps,dw-apb-uart";
82a68267	144	reg = <0x12100 0x100>;
9ae6f740 TP	145	reg-shift = <2>;
9ae6f740 TP	146	interrupts = <42>;
e366154f	147	reg-io-width = <1>;
64939dc5	148	clocks = <&coreclk 0>;
9ae6f740	149	status = "disabled";
467f54b2 GC	150	};
467f54b2 GC	151
4904a82a AE	152	pinctrl: pin-ctrl@18000 {
	153	reg = <0x18000 0x38>;
	154	};
	155
f039dfb5 EG	156	coredivclk: corediv-clock@18740 {
	157	compatible = "marvell,armada-370-corediv-clock";
	158	reg = <0x18740 0xc>;
	159	#clock-cells = <1>;
	160	clocks = <&mainpll>;
	161	clock-output-names = "nand";
	162	};
	163
a095b1c7 JC	164	mbusc: mbus-controller@20000 {
a095b1c7 JC	165	compatible = "marvell,mbus-controller";
8b7dc9d3 TP	166	reg = <0x20000 0x100>, <0x20180 0x20>,
8b7dc9d3 TP	167	<0x20250 0x8>;
a095b1c7 JC	168	};
a095b1c7 JC	169
24c2573b	170	mpic: interrupt-controller@20a00 {
a095b1c7 JC	171	compatible = "marvell,mpic";
	172	#interrupt-cells = <1>;
	173	#size-cells = <1>;
	174	interrupt-controller;
	175	msi-controller;
	176	};
	177
11f7135b	178	coherencyfab: coherency-fabric@20200 {
a095b1c7	179	compatible = "marvell,coherency-fabric";
939ac3cd	180	reg = <0x20200 0xb0>, <0x21010 0x1c>;
a095b1c7 JC	181	};
a095b1c7 JC	182
11f7135b	183	timer: timer@20300 {
467f54b2 GC	184	reg = <0x20300 0x30>, <0x21040 0x30>;
467f54b2 GC	185	interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
467f54b2 GC	186	};
467f54b2 GC	187
11f7135b	188	watchdog: watchdog@20300 {
05afeeb9 EG	189	reg = <0x20300 0x34>, <0x20704 0x4>;
	190	};
	191
11f7135b	192	cpurst: cpurst@20800 {
e72996b8 GC	193	compatible = "marvell,armada-370-cpu-reset";
	194	reg = <0x20800 0x8>;
	195	};
	196
11f7135b	197	pmsu: pmsu@22000 {
b6249d4b GC	198	compatible = "marvell,armada-370-pmsu";
	199	reg = <0x22000 0x1000>;
	200	};
	201
11f7135b	202	usb0: usb@50000 {
a095b1c7 JC	203	compatible = "marvell,orion-ehci";
	204	reg = <0x50000 0x500>;
	205	interrupts = <45>;
467f54b2 GC	206	status = "disabled";
467f54b2 GC	207	};
a6a6de1a	208
11f7135b	209	usb1: usb@51000 {
a095b1c7 JC	210	compatible = "marvell,orion-ehci";
	211	reg = <0x51000 0x500>;
	212	interrupts = <46>;
	213	status = "disabled";
467f54b2	214	};
323c1010	215
be5a9389	216	eth0: ethernet@70000 {
cf8088c5	217	reg = <0x70000 0x4000>;
323c1010	218	interrupts = <8>;
4aa935a2	219	clocks = <&gateclk 4>;
323c1010	220	status = "disabled";
467f54b2	221	};
323c1010	222
1fc21295	223	mdio: mdio@72004 {
a095b1c7 JC	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	compatible = "marvell,orion-mdio";
	227	reg = <0x72004 0x4>;
a6e03dd4	228	clocks = <&gateclk 4>;
a095b1c7 JC	229	};
a095b1c7 JC	230
be5a9389	231	eth1: ethernet@74000 {
cf8088c5	232	reg = <0x74000 0x4000>;
323c1010	233	interrupts = <10>;
4aa935a2	234	clocks = <&gateclk 3>;
323c1010	235	status = "disabled";
467f54b2 GC	236	};
467f54b2 GC	237
11f7135b	238	sata: sata@a0000 {
9b6d351a	239	compatible = "marvell,armada-370-sata";
a095b1c7 JC	240	reg = <0xa0000 0x5000>;
	241	interrupts = <55>;
	242	clocks = <&gateclk 15>, <&gateclk 30>;
	243	clock-names = "0", "1";
467f54b2 GC	244	status = "disabled";
	245	};
	246
3b799199 MR	247	nand_controller: nand-controller@d0000 {
3b799199 MR	248	compatible = "marvell,armada370-nand-controller";
a095b1c7	249	reg = <0xd0000 0x54>;
467f54b2	250	#address-cells = <1>;
3b799199	251	#size-cells = <0>;
a095b1c7 JC	252	interrupts = <113>;
a095b1c7 JC	253	clocks = <&coredivclk 0>;
467f54b2 GC	254	status = "disabled";
	255	};
	256
11f7135b	257	sdio: mvsdio@d4000 {
467f54b2 GC	258	compatible = "marvell,orion-sdio";
	259	reg = <0xd4000 0x200>;
	260	interrupts = <54>;
	261	clocks = <&gateclk 17>;
d87b5fbb SB	262	bus-width = <4>;
	263	cap-sdio-irq;
	264	cap-sd-highspeed;
	265	cap-mmc-highspeed;
467f54b2 GC	266	status = "disabled";
467f54b2 GC	267	};
3d76e1f3	268	};
0160a4b6 SR	269
0160a4b6 SR	270	spi0: spi@10600 {
55877f58 SR	271	reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
	272	<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
	273	<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
	274	<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
	275	<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
	276	<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
	277	<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
	278	<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
	279	<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
0160a4b6 SR	280	#address-cells = <1>;
	281	#size-cells = <0>;
	282	cell-index = <0>;
	283	interrupts = <30>;
	284	clocks = <&coreclk 0>;
	285	status = "disabled";
	286	};
	287
	288	spi1: spi@10680 {
55877f58 SR	289	reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
	290	<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
	291	<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
	292	<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
	293	<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
	294	<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
	295	<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
	296	<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
	297	<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
0160a4b6 SR	298	#address-cells = <1>;
	299	#size-cells = <0>;
	300	cell-index = <1>;
	301	interrupts = <92>;
	302	clocks = <&coreclk 0>;
	303	status = "disabled";
	304	};
9ae6f740	305	};
4675cf57 EG	306
	307	clocks {
	308	/* 2 GHz fixed main PLL */
	309	mainpll: mainpll {
	310	compatible = "fixed-clock";
	311	#clock-cells = <0>;
	312	clock-frequency = <2000000000>;
	313	};
	314	};
467f54b2	315	};