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ARM: dts: omap: Add generic compatible string for I2C EEPROM
[linux-2.6-block.git] / arch / arm / boot / dts / am43x-epos-evm.dts
CommitLineData
4730bcfb
AM		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM43x EPOS EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
e54686e4
M		 14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h>
2e3a9385 16#include <dt-bindings/pwm/pwm.h>
cbfc7e6f 17#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
4730bcfb
AM		 18
19/ {
20 model = "TI AM43x EPOS EVM";
69101b20 21 compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
e54686e4 22
999c3f1a
TV		 23 aliases {
24 display0 = &lcd0;
25 };
26
24a1eb45
LV		 27 chosen {
28 stdout-path = &uart0;
29 };
30
e54686e4
M		 31 vmmcsd_fixed: fixedregulator-sd {
32 compatible = "regulator-fixed";
33 regulator-name = "vmmcsd_fixed";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 enable-active-high;
37 };
38
4c049a5b 39 vbat: fixedregulator0 {
7ec341d9
PU		 40 compatible = "regulator-fixed";
41 regulator-name = "vbat";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 regulator-boot-on;
45 };
46
999c3f1a
TV		 47 lcd0: display {
48 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
49 label = "lcd";
50
999c3f1a
TV		 51 panel-timing {
52 clock-frequency = <33000000>;
53 hactive = <800>;
54 vactive = <480>;
55 hfront-porch = <210>;
56 hback-porch = <16>;
57 hsync-len = <30>;
58 vback-porch = <10>;
59 vfront-porch = <22>;
60 vsync-len = <13>;
61 hsync-active = <0>;
62 vsync-active = <0>;
63 de-active = <1>;
64 pixelclk-active = <1>;
65 };
66
67 port {
68 lcd_in: endpoint {
69 remote-endpoint = <&dpi_out>;
70 };
71 };
72 };
73
18ad99d4 74 matrix_keypad: matrix_keypad0 {
d7eaf3c4
TK		 75 compatible = "gpio-matrix-keypad";
76 debounce-delay-ms = <5>;
77 col-scan-delay-us = <2>;
78
79 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
80 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
81 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
82 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
83
84 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
85 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
86 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
87 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
88
89 linux,keymap = <0x00000201 /* P1 */
90 0x01000204 /* P4 */
91 0x02000207 /* P7 */
92 0x0300020a /* NUMERIC_STAR */
93 0x00010202 /* P2 */
94 0x01010205 /* P5 */
95 0x02010208 /* P8 */
96 0x03010200 /* P0 */
97 0x00020203 /* P3 */
98 0x01020206 /* P6 */
99 0x02020209 /* P9 */
100 0x0302020b /* NUMERIC_POUND */
101 0x00030067 /* UP */
102 0x0103006a /* RIGHT */
103 0x0203006c /* DOWN */
104 0x03030069>; /* LEFT */
105 };
106
107 backlight {
108 compatible = "pwm-backlight";
109 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
110 brightness-levels = <0 51 53 56 62 75 101 152 255>;
111 default-brightness-level = <8>;
112 };
22d7fb57 113
4e8603ef 114 sound0: sound0 {
22d7fb57
PU		 115 compatible = "simple-audio-card";
116 simple-audio-card,name = "AM43-EPOS-EVM";
117 simple-audio-card,widgets =
118 "Microphone", "Microphone Jack",
119 "Headphone", "Headphone Jack",
120 "Speaker", "Speaker";
121 simple-audio-card,routing =
122 "MIC1LP", "Microphone Jack",
123 "MIC1RP", "Microphone Jack",
124 "MIC1LP", "MICBIAS",
125 "MIC1RP", "MICBIAS",
126 "Headphone Jack", "HPL",
127 "Headphone Jack", "HPR",
128 "Speaker", "SPL",
129 "Speaker", "SPR";
130 simple-audio-card,format = "dsp_b";
131 simple-audio-card,bitclock-master = <&sound0_master>;
132 simple-audio-card,frame-master = <&sound0_master>;
133 simple-audio-card,bitclock-inversion;
134
135 simple-audio-card,cpu {
136 sound-dai = <&mcasp1>;
137 system-clock-frequency = <12000000>;
138 };
139
140 sound0_master: simple-audio-card,codec {
141 sound-dai = <&tlv320aic3111>;
142 system-clock-frequency = <12000000>;
143 };
144 };
d7eaf3c4
TK		 145};
146
147&am43xx_pinmux {
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M		 148 cpsw_default: cpsw_default {
149 pinctrl-single,pins = <
150 /* Slave 1 */
43ade6a3
JMC		 151 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
152 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
153 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
154 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
155 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
156 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
157 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
158 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
159 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
e54686e4
M		 160 >;
161 };
162
163 cpsw_sleep: cpsw_sleep {
164 pinctrl-single,pins = <
165 /* Slave 1 reset value */
43ade6a3
JMC		 166 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
167 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
168 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
169 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
170 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
171 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
172 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
173 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
174 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
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M		 175 >;
176 };
177
178 davinci_mdio_default: davinci_mdio_default {
179 pinctrl-single,pins = <
180 /* MDIO */
43ade6a3
JMC		 181 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
182 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
e54686e4
M		 183 >;
184 };
185
186 davinci_mdio_sleep: davinci_mdio_sleep {
187 pinctrl-single,pins = <
188 /* MDIO reset value */
43ade6a3
JMC		 189 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
190 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
e54686e4
M		 191 >;
192 };
193
194 i2c0_pins: pinmux_i2c0_pins {
195 pinctrl-single,pins = <
43ade6a3
JMC		 196 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
197 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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M		 198 >;
199 };
f68e355c
PG		 200
201 nand_flash_x8: nand_flash_x8 {
202 pinctrl-single,pins = <
43ade6a3
JMC		 203 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
204 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
205 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
206 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
207 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
208 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
209 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
210 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
211 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
212 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
213 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
214 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
215 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
216 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
217 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
218 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
f68e355c
PG		 219 >;
220 };
f777ba17 221
2e3a9385
SP		 222 ecap0_pins: backlight_pins {
223 pinctrl-single,pins = <
43ade6a3 224 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
2e3a9385
SP		 225 >;
226 };
0aeaf1c6
SP		 227
228 i2c2_pins: pinmux_i2c2_pins {
229 pinctrl-single,pins = <
43ade6a3
JMC		 230 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
231 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
0aeaf1c6
SP		 232 >;
233 };
416f3d50
SP		 234
235 spi0_pins: pinmux_spi0_pins {
236 pinctrl-single,pins = <
43ade6a3
JMC		 237 AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
238 AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
239 AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
240 AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
416f3d50
SP		 241 >;
242 };
243
244 spi1_pins: pinmux_spi1_pins {
245 pinctrl-single,pins = <
43ade6a3
JMC		 246 AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
247 AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
248 AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
249 AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
416f3d50
SP		 250 >;
251 };
d2885dbb
B		 252
253 mmc1_pins: pinmux_mmc1_pins {
254 pinctrl-single,pins = <
43ade6a3 255 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
d2885dbb
B		 256 >;
257 };
2a1a5043
SP		 258
259 qspi1_default: qspi1_default {
260 pinctrl-single,pins = <
43ade6a3
JMC		 261 AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
262 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
263 AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
264 AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
265 AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
266 AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
2a1a5043
SP		 267 >;
268 };
6cfcb5be
RQ		 269
270 pixcir_ts_pins: pixcir_ts_pins {
271 pinctrl-single,pins = <
43ade6a3 272 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
6cfcb5be
RQ		 273 >;
274 };
741cac5f
SP		 275
276 hdq_pins: pinmux_hdq_pins {
277 pinctrl-single,pins = <
43ade6a3 278 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
741cac5f
SP		 279 >;
280 };
999c3f1a
TV		 281
282 dss_pins: dss_pins {
283 pinctrl-single,pins = <
43ade6a3
JMC		 284 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
285 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
286 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
287 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
288 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
289 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
290 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
291 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
292 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
293 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
294 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
295 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
296 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
297 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
298 AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
299 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
300 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
301 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
302 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
303 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
304 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
305 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
306 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
307 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
308 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
309 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
310 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
311 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
999c3f1a
TV		 312 >;
313 };
314
56fd3dc7 315 display_mux_pins: display_mux_pins {
999c3f1a
TV		 316 pinctrl-single,pins = <
317 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
43ade6a3 318 AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
999c3f1a
TV		 319 >;
320 };
d890edcd
BP		 321
322 vpfe1_pins_default: vpfe1_pins_default {
323 pinctrl-single,pins = <
43ade6a3
JMC		 324 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
325 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
326 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
327 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
328 AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
329 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
330 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
331 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
332 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
333 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
334 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
335 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
336 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
d890edcd
BP		 337 >;
338 };
339
340 vpfe1_pins_sleep: vpfe1_pins_sleep {
341 pinctrl-single,pins = <
43ade6a3
JMC		 342 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
343 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
344 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
345 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
346 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
347 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
348 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
349 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
350 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
351 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
352 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
353 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
354 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
d890edcd
BP		 355 >;
356 };
06e2bf6b
PU		 357
358 mcasp1_pins: mcasp1_pins {
359 pinctrl-single,pins = <
43ade6a3
JMC		 360 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
361 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
362 AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
363 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
06e2bf6b
PU		 364 >;
365 };
366
367 mcasp1_sleep_pins: mcasp1_sleep_pins {
368 pinctrl-single,pins = <
43ade6a3
JMC		 369 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
370 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
371 AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
372 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
06e2bf6b
PU		 373 >;
374 };
e54686e4
M		 375};
376
377&mmc1 {
378 status = "okay";
379 vmmc-supply = <&vmmcsd_fixed>;
380 bus-width = <4>;
d2885dbb
B		 381 pinctrl-names = "default";
382 pinctrl-0 = <&mmc1_pins>;
0731cbdd 383 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
e54686e4
M		 384};
385
386&mac {
387 pinctrl-names = "default", "sleep";
388 pinctrl-0 = <&cpsw_default>;
389 pinctrl-1 = <&cpsw_sleep>;
390 status = "okay";
391};
392
393&davinci_mdio {
394 pinctrl-names = "default", "sleep";
395 pinctrl-0 = <&davinci_mdio_default>;
396 pinctrl-1 = <&davinci_mdio_sleep>;
397 status = "okay";
398};
399
400&cpsw_emac0 {
401 phy_id = <&davinci_mdio>, <16>;
402 phy-mode = "rmii";
403};
404
405&cpsw_emac1 {
406 phy_id = <&davinci_mdio>, <1>;
407 phy-mode = "rmii";
408};
409
fe797553
GC		 410&phy_sel {
411 rmii-clock-ext;
412};
413
e54686e4
M		 414&i2c0 {
415 status = "okay";
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c0_pins>;
497d64a3
K		 418 clock-frequency = <400000>;
419
420 tps65218: tps65218@24 {
421 reg = <0x24>;
422 compatible = "ti,tps65218";
423 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
497d64a3
K		 424 interrupt-controller;
425 #interrupt-cells = <2>;
426
427 dcdc1: regulator-dcdc1 {
497d64a3
K		 428 regulator-name = "vdd_core";
429 regulator-min-microvolt = <912000>;
430 regulator-max-microvolt = <1144000>;
431 regulator-boot-on;
432 regulator-always-on;
433 };
434
435 dcdc2: regulator-dcdc2 {
497d64a3
K		 436 regulator-name = "vdd_mpu";
437 regulator-min-microvolt = <912000>;
438 regulator-max-microvolt = <1378000>;
439 regulator-boot-on;
440 regulator-always-on;
441 };
442
443 dcdc3: regulator-dcdc3 {
497d64a3 444 regulator-name = "vdcdc3";
fc2a602f
K		 445 regulator-min-microvolt = <1500000>;
446 regulator-max-microvolt = <1500000>;
497d64a3
K		 447 regulator-boot-on;
448 regulator-always-on;
449 };
450
7ec341d9 451 dcdc4: regulator-dcdc4 {
7ec341d9
PU		 452 regulator-name = "vdcdc4";
453 regulator-min-microvolt = <3300000>;
454 regulator-max-microvolt = <3300000>;
455 regulator-boot-on;
456 regulator-always-on;
457 };
458
497d64a3 459 dcdc5: regulator-dcdc5 {
497d64a3
K		 460 regulator-name = "v1_0bat";
461 regulator-min-microvolt = <1000000>;
462 regulator-max-microvolt = <1000000>;
463 };
464
465 dcdc6: regulator-dcdc6 {
497d64a3
K		 466 regulator-name = "v1_8bat";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>;
469 };
470
471 ldo1: regulator-ldo1 {
497d64a3
K		 472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <1800000>;
474 regulator-boot-on;
475 regulator-always-on;
476 };
477 };
e54686e4
M		 478
479 at24@50 {
05e7d622 480 compatible = "atmel,24c256";
e54686e4
M		 481 pagesize = <64>;
482 reg = <0x50>;
483 };
484
485 pixcir_ts@5c {
6cfcb5be
RQ		 486 compatible = "pixcir,pixcir_tangoc";
487 pinctrl-names = "default";
488 pinctrl-0 = <&pixcir_ts_pins>;
e54686e4
M		 489 reg = <0x5c>;
490 interrupt-parent = <&gpio1>;
95e7d03e 491 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
e54686e4
M		 492
493 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
494
342666ce
RQ		 495 touchscreen-size-x = <1024>;
496 touchscreen-size-y = <600>;
e54686e4 497 };
cbfc7e6f
PU		 498
499 tlv320aic3111: tlv320aic3111@18 {
22d7fb57 500 #sound-dai-cells = <0>;
cbfc7e6f
PU		 501 compatible = "ti,tlv320aic3111";
502 reg = <0x18>;
503 status = "okay";
504
505 ai31xx-micbias-vg = <MICBIAS_2_0V>;
506
507 /* Regulators */
508 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
509 SPRVDD-supply = <&vbat>; /* vbat */
510 SPLVDD-supply = <&vbat>; /* vbat */
511 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
512 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
513 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
514 };
e54686e4
M		 515};
516
0aeaf1c6
SP		 517&i2c2 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c2_pins>;
520 status = "okay";
521};
522
e54686e4
M		 523&gpio0 {
524 status = "okay";
525};
526
527&gpio1 {
528 status = "okay";
529};
530
531&gpio2 {
56fd3dc7
PU		 532 pinctrl-names = "default";
533 pinctrl-0 = <&display_mux_pins>;
e54686e4 534 status = "okay";
56fd3dc7
PU		 535
536 p1 {
537 /*
538 * SelLCDorHDMI selects between display and audio paths:
539 * Low: HDMI display with audio via HDMI
540 * High: LCD display with analog audio via aic3111 codec
541 */
542 gpio-hog;
543 gpios = <1 GPIO_ACTIVE_HIGH>;
544 output-high;
545 line-name = "SelLCDorHDMI";
546 };
e54686e4
M		 547};
548
549&gpio3 {
550 status = "okay";
4730bcfb 551};
f68e355c
PG		 552
553&elm {
554 status = "okay";
555};
556
557&gpmc {
331bbb59 558 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
f68e355c
PG		 559 pinctrl-names = "default";
560 pinctrl-0 = <&nand_flash_x8>;
be3f39c8 561 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
f68e355c 562 nand@0,0 {
be3f39c8 563 compatible = "ti,omap2-nand";
e2c5eb78 564 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
be3f39c8
RQ		 565 interrupt-parent = <&gpmc>;
566 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
567 <1 IRQ_TYPE_NONE>; /* termcount */
99a41011 568 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
db01e6c7 569 ti,nand-ecc-opt = "bch16";
f68e355c
PG		 570 ti,elm-id = <&elm>;
571 nand-bus-width = <8>;
572 gpmc,device-width = <1>;
573 gpmc,sync-clk-ps = <0>;
574 gpmc,cs-on-ns = <0>;
575 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
576 gpmc,cs-wr-off-ns = <40>;
577 gpmc,adv-on-ns = <0>; /* cs-on-ns */
578 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
579 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
580 gpmc,we-on-ns = <0>; /* cs-on-ns */
581 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
582 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
583 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
584 gpmc,access-ns = <30>; /* tCEA + 4*/
585 gpmc,rd-cycle-ns = <40>;
586 gpmc,wr-cycle-ns = <40>;
f68e355c
PG		 587 gpmc,bus-turnaround-ns = <0>;
588 gpmc,cycle2cycle-delay-ns = <0>;
589 gpmc,clk-activation-ns = <0>;
f68e355c
PG		 590 gpmc,wr-access-ns = <40>;
591 gpmc,wr-data-mux-bus-ns = <0>;
592 /* MTD partition table */
593 /* All SPL-* partitions are sized to minimal length
594 * which can be independently programmable. For
595 * NAND flash this is equal to size of erase-block */
596 #address-cells = <1>;
597 #size-cells = <1>;
598 partition@0 {
599 label = "NAND.SPL";
600 reg = <0x00000000 0x00040000>;
601 };
602 partition@1 {
603 label = "NAND.SPL.backup1";
604 reg = <0x00040000 0x00040000>;
605 };
606 partition@2 {
607 label = "NAND.SPL.backup2";
608 reg = <0x00080000 0x00040000>;
609 };
610 partition@3 {
611 label = "NAND.SPL.backup3";
612 reg = <0x000C0000 0x00040000>;
613 };
614 partition@4 {
615 label = "NAND.u-boot-spl-os";
616 reg = <0x00100000 0x00080000>;
617 };
618 partition@5 {
619 label = "NAND.u-boot";
620 reg = <0x00180000 0x00100000>;
621 };
622 partition@6 {
623 label = "NAND.u-boot-env";
624 reg = <0x00280000 0x00040000>;
625 };
626 partition@7 {
627 label = "NAND.u-boot-env.backup1";
628 reg = <0x002C0000 0x00040000>;
629 };
630 partition@8 {
631 label = "NAND.kernel";
632 reg = <0x00300000 0x00700000>;
633 };
634 partition@9 {
635 label = "NAND.file-system";
c4de4ecd 636 reg = <0x00a00000 0x1f600000>;
f68e355c
PG		 637 };
638 };
639};
f777ba17 640
2e3a9385
SP		 641&epwmss0 {
642 status = "okay";
643};
644
0f39f7b9
V		 645&tscadc {
646 status = "okay";
647
648 adc {
649 ti,adc-channels = <0 1 2 3 4 5 6 7>;
650 };
651};
652
2e3a9385
SP		 653&ecap0 {
654 status = "okay";
655 pinctrl-names = "default";
656 pinctrl-0 = <&ecap0_pins>;
657};
416f3d50
SP		 658
659&spi0 {
660 pinctrl-names = "default";
661 pinctrl-0 = <&spi0_pins>;
662 status = "okay";
663};
664
665&spi1 {
666 pinctrl-names = "default";
667 pinctrl-0 = <&spi1_pins>;
668 status = "okay";
669};
61d5924f
GC		 670
671&usb2_phy1 {
672 status = "okay";
673};
674
675&usb1 {
676 dr_mode = "peripheral";
677 status = "okay";
678};
679
680&usb2_phy2 {
681 status = "okay";
682};
683
684&usb2 {
685 dr_mode = "host";
686 status = "okay";
687};
2a1a5043
SP		 688
689&qspi {
331bbb59 690 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
2a1a5043
SP		 691 pinctrl-names = "default";
692 pinctrl-0 = <&qspi1_default>;
693
694 spi-max-frequency = <48000000>;
695 m25p80@0 {
696 compatible = "mx66l51235l";
697 spi-max-frequency = <48000000>;
698 reg = <0>;
699 spi-cpol;
700 spi-cpha;
701 spi-tx-bus-width = <1>;
702 spi-rx-bus-width = <4>;
703 #address-cells = <1>;
704 #size-cells = <1>;
705
706 /* MTD partition table.
707 * The ROM checks the first 512KiB
708 * for a valid file to boot(XIP).
709 */
710 partition@0 {
711 label = "QSPI.U_BOOT";
712 reg = <0x00000000 0x000080000>;
713 };
714 partition@1 {
715 label = "QSPI.U_BOOT.backup";
716 reg = <0x00080000 0x00080000>;
717 };
718 partition@2 {
719 label = "QSPI.U-BOOT-SPL_OS";
720 reg = <0x00100000 0x00010000>;
721 };
722 partition@3 {
723 label = "QSPI.U_BOOT_ENV";
724 reg = <0x00110000 0x00010000>;
725 };
726 partition@4 {
727 label = "QSPI.U-BOOT-ENV.backup";
728 reg = <0x00120000 0x00010000>;
729 };
730 partition@5 {
731 label = "QSPI.KERNEL";
732 reg = <0x00130000 0x0800000>;
733 };
734 partition@6 {
735 label = "QSPI.FILESYSTEM";
736 reg = <0x00930000 0x36D0000>;
737 };
738 };
739};
741cac5f
SP		 740
741&hdq {
742 status = "okay";
743 pinctrl-names = "default";
744 pinctrl-0 = <&hdq_pins>;
745};
999c3f1a
TV		 746
747&dss {
748 status = "ok";
749
750 pinctrl-names = "default";
751 pinctrl-0 = <&dss_pins>;
752
753 port {
bc8bffd0 754 dpi_out: endpoint {
999c3f1a
TV		 755 remote-endpoint = <&lcd_in>;
756 data-lines = <24>;
757 };
758 };
759};
d890edcd
BP		 760
761&vpfe1 {
762 status = "okay";
763 pinctrl-names = "default", "sleep";
764 pinctrl-0 = <&vpfe1_pins_default>;
765 pinctrl-1 = <&vpfe1_pins_sleep>;
766
767 port {
768 vpfe1_ep: endpoint {
769 /* remote-endpoint = <&sensor>; add once we have it */
770 ti,am437x-vpfe-interface = <0>;
771 bus-width = <8>;
772 hsync-active = <0>;
773 vsync-active = <0>;
774 };
775 };
776};
06e2bf6b
PU		 777
778&mcasp1 {
22d7fb57 779 #sound-dai-cells = <0>;
06e2bf6b
PU		 780 pinctrl-names = "default", "sleep";
781 pinctrl-0 = <&mcasp1_pins>;
782 pinctrl-1 = <&mcasp1_sleep_pins>;
783
784 status = "okay";
785
786 op-mode = <0>; /* MCASP_IIS_MODE */
787 tdm-slots = <2>;
788 /* 4 serializer */
789 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
790 1 2 0 0
791 >;
792 tx-num-evt = <32>;
793 rx-num-evt = <32>;
794};
cfe1580a
LV		 795
796&synctimer_32kclk {
797 assigned-clocks = <&mux_synctimer32k_ck>;
798 assigned-clock-parents = <&clkdiv32k_ick>;
799};
Linux 6.x block layer and io_uring tree(s)