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ARM: dts: am43xx: Introduce MUX_MODE9 for pinctrl
[linux-2.6-block.git] / arch / arm / boot / dts / am437x-gp-evm.dts
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11e2191c
LV		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
c540b476 15#include <dt-bindings/pwm/pwm.h>
51724dbb 16#include <dt-bindings/gpio/gpio.h>
11e2191c
LV		 17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
c540b476 21
0bacb529
SP		 22 aliases {
23 display0 = &lcd0;
24 };
25
390810a9 26 evm_v3_3d: fixedregulator-v3_3d {
506be3fb 27 compatible = "regulator-fixed";
390810a9 28 regulator-name = "evm_v3_3d";
506be3fb
B		 29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 enable-active-high;
32 };
33
b2873bfa
DG		 34 vtt_fixed: fixedregulator-vtt {
35 compatible = "regulator-fixed";
36 regulator-name = "vtt_fixed";
37 regulator-min-microvolt = <1500000>;
38 regulator-max-microvolt = <1500000>;
39 regulator-always-on;
40 regulator-boot-on;
41 enable-active-high;
42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
43 };
44
b6bbf598
ER		 45 vmmcwl_fixed: fixedregulator-mmcwl {
46 compatible = "regulator-fixed";
47 regulator-name = "vmmcwl_fixed";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
51 enable-active-high;
52 };
53
c540b476
SP		 54 backlight {
55 compatible = "pwm-backlight";
56 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
57 brightness-levels = <0 51 53 56 62 75 101 152 255>;
58 default-brightness-level = <8>;
59 };
51724dbb
SP		 60
61 matrix_keypad: matrix_keypad@0 {
62 compatible = "gpio-matrix-keypad";
63 debounce-delay-ms = <5>;
64 col-scan-delay-us = <2>;
65
66 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
67 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
68 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
69
70 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
71 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
72
73 linux,keymap = <0x00000201 /* P1 */
74 0x00010202 /* P2 */
75 0x01000067 /* UP */
76 0x0101006a /* RIGHT */
77 0x02000069 /* LEFT */
78 0x0201006c>; /* DOWN */
79 };
0bacb529
SP		 80
81 lcd0: display {
82 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
83 label = "lcd";
84
0bacb529
SP		 85 panel-timing {
86 clock-frequency = <33000000>;
87 hactive = <800>;
88 vactive = <480>;
89 hfront-porch = <210>;
90 hback-porch = <16>;
91 hsync-len = <30>;
92 vback-porch = <10>;
93 vfront-porch = <22>;
94 vsync-len = <13>;
95 hsync-active = <0>;
96 vsync-active = <0>;
97 de-active = <1>;
98 pixelclk-active = <1>;
99 };
100
101 port {
102 lcd_in: endpoint {
103 remote-endpoint = <&dpi_out>;
104 };
105 };
106 };
3aa59200
LP		 107
108 /* fixed 12MHz oscillator */
109 refclk: oscillator {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <12000000>;
113 };
114
cf9a4850
PU		 115 sound0: sound@0 {
116 compatible = "simple-audio-card";
117 simple-audio-card,name = "AM437x-GP-EVM";
118 simple-audio-card,widgets =
119 "Headphone", "Headphone Jack",
120 "Line", "Line In";
121 simple-audio-card,routing =
122 "Headphone Jack", "HPLOUT",
123 "Headphone Jack", "HPROUT",
124 "LINE1L", "Line In",
125 "LINE1R", "Line In";
126 simple-audio-card,format = "dsp_b";
127 simple-audio-card,bitclock-master = <&sound0_master>;
128 simple-audio-card,frame-master = <&sound0_master>;
129 simple-audio-card,bitclock-inversion;
130
131 simple-audio-card,cpu {
132 sound-dai = <&mcasp1>;
133 system-clock-frequency = <12000000>;
134 };
135
136 sound0_master: simple-audio-card,codec {
137 sound-dai = <&tlv320aic3106>;
138 system-clock-frequency = <12000000>;
139 };
140 };
11e2191c
LV		 141};
142
143&am43xx_pinmux {
b6bbf598
ER		 144 pinctrl-names = "default", "sleep";
145 pinctrl-0 = <&wlan_pins_default>;
146 pinctrl-1 = <&wlan_pins_sleep>;
147
11e2191c
LV		 148 i2c0_pins: i2c0_pins {
149 pinctrl-single,pins = <
150 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
151 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
152 >;
153 };
154
155 i2c1_pins: i2c1_pins {
156 pinctrl-single,pins = <
157 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
158 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
159 >;
160 };
c540b476 161
506be3fb
B		 162 mmc1_pins: pinmux_mmc1_pins {
163 pinctrl-single,pins = <
164 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
165 >;
166 };
167
c540b476
SP		 168 ecap0_pins: backlight_pins {
169 pinctrl-single,pins = <
170 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
171 >;
172 };
0ebc1e25
SN		 173
174 pixcir_ts_pins: pixcir_ts_pins {
175 pinctrl-single,pins = <
176 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
177 >;
178 };
7b25babf
M		 179
180 cpsw_default: cpsw_default {
181 pinctrl-single,pins = <
182 /* Slave 1 */
183 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
184 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
185 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
186 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
187 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
188 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
189 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
190 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
191 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
192 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
193 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
194 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
195 >;
196 };
197
198 cpsw_sleep: cpsw_sleep {
199 pinctrl-single,pins = <
200 /* Slave 1 reset value */
201 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
205 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
209 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
211 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
212 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
213 >;
214 };
215
216 davinci_mdio_default: davinci_mdio_default {
217 pinctrl-single,pins = <
218 /* MDIO */
219 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
220 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
221 >;
222 };
223
224 davinci_mdio_sleep: davinci_mdio_sleep {
225 pinctrl-single,pins = <
226 /* MDIO reset value */
227 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 >;
230 };
99ffa642
PG		 231
232 nand_flash_x8: nand_flash_x8 {
233 pinctrl-single,pins = <
234 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
235 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
236 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
237 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
238 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
239 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
240 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
241 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
242 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
243 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
244 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
245 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
246 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
247 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
248 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
249 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
250 >;
251 };
0bacb529
SP		 252
253 dss_pins: dss_pins {
254 pinctrl-single,pins = <
255 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
256 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
257 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
258 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
259 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
260 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
261 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
262 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
263 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
264 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
265 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
266 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
267 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
268 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
269 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
270 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
271 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
272 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
273 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
274 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
275 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
276 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
277 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
278 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
279 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
280 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
281 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
282 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
283
284 >;
285 };
286
593113e7 287 display_mux_pins: display_mux_pins {
0bacb529
SP		 288 pinctrl-single,pins = <
289 /* GPIO 5_8 to select LCD / HDMI */
290 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
291 >;
292 };
4b1ce235
M		 293
294 dcan0_default: dcan0_default_pins {
295 pinctrl-single,pins = <
296 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
297 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
298 >;
299 };
300
301 dcan1_default: dcan1_default_pins {
302 pinctrl-single,pins = <
303 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
304 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
305 >;
306 };
c788a7f4
BP		 307
308 vpfe0_pins_default: vpfe0_pins_default {
309 pinctrl-single,pins = <
310 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
311 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
312 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
313 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
314 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
315 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
316 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
317 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
318 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
319 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
320 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
321 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
322 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
323 >;
324 };
325
326 vpfe0_pins_sleep: vpfe0_pins_sleep {
327 pinctrl-single,pins = <
328 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
329 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
330 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
331 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
332 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
333 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
334 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
335 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
336 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
337 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
338 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
339 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
340 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
341 >;
342 };
343
344 vpfe1_pins_default: vpfe1_pins_default {
345 pinctrl-single,pins = <
346 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
347 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
348 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
349 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
350 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
351 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
352 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
353 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
354 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
355 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
356 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
357 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
358 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
359 >;
360 };
361
362 vpfe1_pins_sleep: vpfe1_pins_sleep {
363 pinctrl-single,pins = <
364 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
365 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
366 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
367 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
368 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
369 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
370 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
371 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
372 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
373 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
374 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
375 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
376 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
377 >;
378 };
b6bbf598
ER		 379
380 mmc3_pins_default: pinmux_mmc3_pins_default {
381 pinctrl-single,pins = <
382 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
383 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
384 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
385 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
386 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
387 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
388 >;
389 };
390
391 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
392 pinctrl-single,pins = <
393 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
394 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
395 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
396 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
397 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
398 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
399 >;
400 };
401
402 wlan_pins_default: pinmux_wlan_pins_default {
403 pinctrl-single,pins = <
404 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
405 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
406 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
407 >;
408 };
409
410 wlan_pins_sleep: pinmux_wlan_pins_sleep {
411 pinctrl-single,pins = <
412 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
413 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
414 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
415 >;
416 };
417
418 uart3_pins: uart3_pins {
419 pinctrl-single,pins = <
420 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
421 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
422 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
423 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
424 >;
425 };
d3d92af1
PU		 426
427 mcasp1_pins: mcasp1_pins {
428 pinctrl-single,pins = <
429 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
430 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
431 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
432 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
433 >;
434 };
435
436 mcasp1_sleep_pins: mcasp1_sleep_pins {
437 pinctrl-single,pins = <
438 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
439 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
440 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
441 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
442 >;
443 };
11e2191c
LV		 444};
445
446&i2c0 {
1fc98144
K		 447 status = "okay";
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c0_pins>;
93166413 450 clock-frequency = <100000>;
0e2da5e6
K		 451
452 tps65218: tps65218@24 {
453 reg = <0x24>;
454 compatible = "ti,tps65218";
455 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
0e2da5e6
K		 456 interrupt-controller;
457 #interrupt-cells = <2>;
458
459 dcdc1: regulator-dcdc1 {
460 compatible = "ti,tps65218-dcdc1";
461 regulator-name = "vdd_core";
462 regulator-min-microvolt = <912000>;
463 regulator-max-microvolt = <1144000>;
464 regulator-boot-on;
465 regulator-always-on;
466 };
467
468 dcdc2: regulator-dcdc2 {
469 compatible = "ti,tps65218-dcdc2";
470 regulator-name = "vdd_mpu";
471 regulator-min-microvolt = <912000>;
472 regulator-max-microvolt = <1378000>;
473 regulator-boot-on;
474 regulator-always-on;
475 };
476
477 dcdc3: regulator-dcdc3 {
478 compatible = "ti,tps65218-dcdc3";
479 regulator-name = "vdcdc3";
3015ddbd
K		 480 regulator-min-microvolt = <1500000>;
481 regulator-max-microvolt = <1500000>;
0e2da5e6
K		 482 regulator-boot-on;
483 regulator-always-on;
484 };
485 dcdc5: regulator-dcdc5 {
486 compatible = "ti,tps65218-dcdc5";
487 regulator-name = "v1_0bat";
488 regulator-min-microvolt = <1000000>;
489 regulator-max-microvolt = <1000000>;
490 };
491
492 dcdc6: regulator-dcdc6 {
493 compatible = "ti,tps65218-dcdc6";
494 regulator-name = "v1_8bat";
495 regulator-min-microvolt = <1800000>;
496 regulator-max-microvolt = <1800000>;
497 };
498
499 ldo1: regulator-ldo1 {
500 compatible = "ti,tps65218-ldo1";
501 regulator-min-microvolt = <1800000>;
502 regulator-max-microvolt = <1800000>;
503 regulator-boot-on;
504 regulator-always-on;
505 };
506 };
3aa59200
LP		 507
508 ov2659@30 {
509 compatible = "ovti,ov2659";
510 reg = <0x30>;
511
512 clocks = <&refclk 0>;
513 clock-names = "xvclk";
514
515 port {
516 ov2659_0: endpoint {
517 remote-endpoint = <&vpfe1_ep>;
518 link-frequencies = /bits/ 64 <70000000>;
519 };
520 };
521 };
11e2191c
LV		 522};
523
524&i2c1 {
1fc98144
K		 525 status = "okay";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c1_pins>;
0ebc1e25
SN		 528 pixcir_ts@5c {
529 compatible = "pixcir,pixcir_tangoc";
530 pinctrl-names = "default";
531 pinctrl-0 = <&pixcir_ts_pins>;
532 reg = <0x5c>;
533 interrupt-parent = <&gpio3>;
534 interrupts = <22 0>;
535
536 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
537
f048615e
RQ		 538 touchscreen-size-x = <1024>;
539 touchscreen-size-y = <600>;
0ebc1e25 540 };
3aa59200
LP		 541
542 ov2659@30 {
543 compatible = "ovti,ov2659";
544 reg = <0x30>;
545
546 clocks = <&refclk 0>;
547 clock-names = "xvclk";
548
549 port {
550 ov2659_1: endpoint {
551 remote-endpoint = <&vpfe0_ep>;
552 link-frequencies = /bits/ 64 <70000000>;
553 };
554 };
555 };
6076b159
PU		 556
557 tlv320aic3106: tlv320aic3106@1b {
cf9a4850 558 #sound-dai-cells = <0>;
6076b159
PU		 559 compatible = "ti,tlv320aic3106";
560 reg = <0x1b>;
561 status = "okay";
562
563 /* Regulators */
564 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
565 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
566 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
567 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
568 };
11e2191c 569};
c540b476
SP		 570
571&epwmss0 {
572 status = "okay";
573};
574
0f39f7b9
V		 575&tscadc {
576 status = "okay";
577
578 adc {
579 ti,adc-channels = <0 1 2 3 4 5 6 7>;
580 };
581};
582
c540b476
SP		 583&ecap0 {
584 status = "okay";
585 pinctrl-names = "default";
586 pinctrl-0 = <&ecap0_pins>;
587};
d3d46cca 588
506be3fb
B		 589&gpio0 {
590 status = "okay";
591};
592
b6bbf598
ER		 593&gpio1 {
594 status = "okay";
595};
596
d3d46cca
SP		 597&gpio3 {
598 status = "okay";
599};
600
601&gpio4 {
602 status = "okay";
603};
506be3fb 604
1ff3859e 605&gpio5 {
593113e7
PU		 606 pinctrl-names = "default";
607 pinctrl-0 = <&display_mux_pins>;
1ff3859e
DG		 608 status = "okay";
609 ti,no-reset-on-init;
593113e7
PU		 610
611 p8 {
612 /*
613 * SelLCDorHDMI selects between display and audio paths:
614 * Low: HDMI display with audio via HDMI
615 * High: LCD display with analog audio via aic3111 codec
616 */
617 gpio-hog;
618 gpios = <8 GPIO_ACTIVE_HIGH>;
619 output-high;
620 line-name = "SelLCDorHDMI";
621 };
1ff3859e
DG		 622};
623
506be3fb
B		 624&mmc1 {
625 status = "okay";
390810a9 626 vmmc-supply = <&evm_v3_3d>;
506be3fb
B		 627 bus-width = <4>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&mmc1_pins>;
630 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
631};
b5820d3a 632
b6bbf598
ER		 633&mmc3 {
634 status = "okay";
635 /* these are on the crossbar and are outlined in the
636 xbar-event-map element */
637 dmas = <&edma 30
638 &edma 31>;
639 dma-names = "tx", "rx";
640 vmmc-supply = <&vmmcwl_fixed>;
641 bus-width = <4>;
642 pinctrl-names = "default", "sleep";
643 pinctrl-0 = <&mmc3_pins_default>;
644 pinctrl-1 = <&mmc3_pins_sleep>;
645 cap-power-off-card;
646 keep-power-in-suspend;
647 ti,non-removable;
648
649 #address-cells = <1>;
650 #size-cells = <0>;
651 wlcore: wlcore@0 {
652 compatible = "ti,wl1835";
653 reg = <2>;
654 interrupt-parent = <&gpio1>;
655 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
656 };
657};
658
659&edma {
660 ti,edma-xbar-event-map = /bits/ 16 <1 30
661 2 31>;
662};
663
664&uart3 {
665 status = "okay";
666 pinctrl-names = "default";
667 pinctrl-0 = <&uart3_pins>;
668};
669
b5820d3a
GC		 670&usb2_phy1 {
671 status = "okay";
672};
673
674&usb1 {
675 dr_mode = "peripheral";
676 status = "okay";
677};
678
679&usb2_phy2 {
680 status = "okay";
681};
682
683&usb2 {
684 dr_mode = "host";
685 status = "okay";
686};
7b25babf
M		 687
688&mac {
689 slaves = <1>;
690 pinctrl-names = "default", "sleep";
691 pinctrl-0 = <&cpsw_default>;
692 pinctrl-1 = <&cpsw_sleep>;
693 status = "okay";
694};
695
696&davinci_mdio {
697 pinctrl-names = "default", "sleep";
698 pinctrl-0 = <&davinci_mdio_default>;
699 pinctrl-1 = <&davinci_mdio_sleep>;
700 status = "okay";
701};
702
703&cpsw_emac0 {
704 phy_id = <&davinci_mdio>, <0>;
705 phy-mode = "rgmii";
706};
99ffa642
PG		 707
708&elm {
709 status = "okay";
710};
711
712&gpmc {
713 status = "okay";
714 pinctrl-names = "default";
715 pinctrl-0 = <&nand_flash_x8>;
716 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
717 nand@0,0 {
718 reg = <0 0 4>; /* device IO registers */
6b869110 719 ti,nand-ecc-opt = "bch16";
99ffa642
PG		 720 ti,elm-id = <&elm>;
721 nand-bus-width = <8>;
722 gpmc,device-width = <1>;
723 gpmc,sync-clk-ps = <0>;
724 gpmc,cs-on-ns = <0>;
725 gpmc,cs-rd-off-ns = <40>;
726 gpmc,cs-wr-off-ns = <40>;
727 gpmc,adv-on-ns = <0>;
728 gpmc,adv-rd-off-ns = <25>;
729 gpmc,adv-wr-off-ns = <25>;
730 gpmc,we-on-ns = <0>;
731 gpmc,we-off-ns = <20>;
732 gpmc,oe-on-ns = <3>;
733 gpmc,oe-off-ns = <30>;
734 gpmc,access-ns = <30>;
735 gpmc,rd-cycle-ns = <40>;
736 gpmc,wr-cycle-ns = <40>;
737 gpmc,wait-pin = <0>;
99ffa642
PG		 738 gpmc,bus-turnaround-ns = <0>;
739 gpmc,cycle2cycle-delay-ns = <0>;
740 gpmc,clk-activation-ns = <0>;
741 gpmc,wait-monitoring-ns = <0>;
742 gpmc,wr-access-ns = <40>;
743 gpmc,wr-data-mux-bus-ns = <0>;
744 /* MTD partition table */
745 /* All SPL-* partitions are sized to minimal length
746 * which can be independently programmable. For
747 * NAND flash this is equal to size of erase-block */
748 #address-cells = <1>;
749 #size-cells = <1>;
750 partition@0 {
751 label = "NAND.SPL";
752 reg = <0x00000000 0x00040000>;
753 };
754 partition@1 {
755 label = "NAND.SPL.backup1";
756 reg = <0x00040000 0x00040000>;
757 };
758 partition@2 {
759 label = "NAND.SPL.backup2";
760 reg = <0x00080000 0x00040000>;
761 };
762 partition@3 {
763 label = "NAND.SPL.backup3";
764 reg = <0x000c0000 0x00040000>;
765 };
766 partition@4 {
767 label = "NAND.u-boot-spl-os";
768 reg = <0x00100000 0x00080000>;
769 };
770 partition@5 {
771 label = "NAND.u-boot";
772 reg = <0x00180000 0x00100000>;
773 };
774 partition@6 {
775 label = "NAND.u-boot-env";
776 reg = <0x00280000 0x00040000>;
777 };
778 partition@7 {
779 label = "NAND.u-boot-env.backup1";
780 reg = <0x002c0000 0x00040000>;
781 };
782 partition@8 {
783 label = "NAND.kernel";
784 reg = <0x00300000 0x00700000>;
785 };
786 partition@9 {
787 label = "NAND.file-system";
788 reg = <0x00a00000 0x1f600000>;
789 };
790 };
791};
0bacb529
SP		 792
793&dss {
794 status = "ok";
795
796 pinctrl-names = "default";
797 pinctrl-0 = <&dss_pins>;
798
799 port {
800 dpi_out: endpoint@0 {
801 remote-endpoint = <&lcd_in>;
802 data-lines = <24>;
803 };
804 };
805};
4b1ce235
M		 806
807&dcan0 {
808 pinctrl-names = "default";
809 pinctrl-0 = <&dcan0_default>;
810 status = "okay";
811};
812
813&dcan1 {
814 pinctrl-names = "default";
815 pinctrl-0 = <&dcan1_default>;
816 status = "okay";
817};
c788a7f4
BP		 818
819&vpfe0 {
820 status = "okay";
821 pinctrl-names = "default", "sleep";
822 pinctrl-0 = <&vpfe0_pins_default>;
823 pinctrl-1 = <&vpfe0_pins_sleep>;
824
825 port {
826 vpfe0_ep: endpoint {
3aa59200 827 remote-endpoint = <&ov2659_1>;
c788a7f4
BP		 828 ti,am437x-vpfe-interface = <0>;
829 bus-width = <8>;
830 hsync-active = <0>;
831 vsync-active = <0>;
832 };
833 };
834};
835
836&vpfe1 {
837 status = "okay";
838 pinctrl-names = "default", "sleep";
839 pinctrl-0 = <&vpfe1_pins_default>;
840 pinctrl-1 = <&vpfe1_pins_sleep>;
841
842 port {
843 vpfe1_ep: endpoint {
3aa59200 844 remote-endpoint = <&ov2659_0>;
c788a7f4
BP		 845 ti,am437x-vpfe-interface = <0>;
846 bus-width = <8>;
847 hsync-active = <0>;
848 vsync-active = <0>;
849 };
850 };
851};
d3d92af1
PU		 852
853&mcasp1 {
cf9a4850 854 #sound-dai-cells = <0>;
d3d92af1
PU		 855 pinctrl-names = "default", "sleep";
856 pinctrl-0 = <&mcasp1_pins>;
857 pinctrl-1 = <&mcasp1_sleep_pins>;
858
859 status = "okay";
860
861 op-mode = <0>; /* MCASP_IIS_MODE */
862 tdm-slots = <2>;
863 /* 4 serializers */
864 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
865 0 0 1 2
866 >;
867 tx-num-evt = <32>;
868 rx-num-evt = <32>;
869};
Linux 6.x block layer and io_uring tree(s)