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Merge branch 'pull/v3.18/for-dt-pinctrl-updates' of https://github.com/nmenon/linux...
[linux-2.6-block.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&gic>;
19
20
21 aliases {
6a968678
NM		 22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
6cfd8117 25 serial0 = &uart0;
9e3269b8
LV		 26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
6cfd8117
AM		 28 };
29
30 cpus {
738c7409
AM		 31 #address-cells = <1>;
32 #size-cells = <0>;
08ecb28a 33 cpu: cpu@0 {
6cfd8117 34 compatible = "arm,cortex-a9";
738c7409
AM		 35 device_type = "cpu";
36 reg = <0>;
8d766fa2
NM		 37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 42 };
43 };
44
45 gic: interrupt-controller@48241000 {
46 compatible = "arm,cortex-a9-gic";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0x48241000 0x1000>,
50 <0x48240100 0x0100>;
51 };
52
9e3269b8
LV		 53 l2-cache-controller@48242000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x48242000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
60 am43xx_pinmux: pinmux@44e10800 {
d8c5bab6 61 compatible = "ti,am437-padconf", "pinctrl-single";
9e3269b8
LV		 62 reg = <0x44e10800 0x31c>;
63 #address-cells = <1>;
64 #size-cells = <0>;
d8c5bab6
NM		 65 #interrupt-cells = <1>;
66 interrupt-controller;
9e3269b8
LV		 67 pinctrl-single,register-width = <32>;
68 pinctrl-single,function-mask = <0xffffffff>;
69 };
70
6cfd8117 71 ocp {
2eeddb8a 72 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
9e3269b8 76 ti,hwmods = "l3_main";
2eeddb8a
AM		 77 reg = <0x44000000 0x400000
78 0x44800000 0x400000>;
79 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 81
6a679208
TK		 82 prcm: prcm@44df0000 {
83 compatible = "ti,am4-prcm";
84 reg = <0x44df0000 0x11000>;
85
86 prcm_clocks: clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90
91 prcm_clockdomains: clockdomains {
92 };
93 };
94
95 scrm: scrm@44e10000 {
96 compatible = "ti,am4-scrm";
97 reg = <0x44e10000 0x2000>;
98
99 scrm_clocks: clocks {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 };
103
104 scrm_clockdomains: clockdomains {
105 };
106 };
107
9e3269b8
LV		 108 edma: edma@49000000 {
109 compatible = "ti,edma3";
110 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
111 reg = <0x49000000 0x10000>,
112 <0x44e10f90 0x10>;
113 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
116 #dma-cells = <1>;
9e3269b8 117 };
6cfd8117
AM		 118
119 uart0: serial@44e09000 {
120 compatible = "ti,am4372-uart","ti,omap2-uart";
121 reg = <0x44e09000 0x2000>;
122 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 123 ti,hwmods = "uart1";
124 };
125
126 uart1: serial@48022000 {
127 compatible = "ti,am4372-uart","ti,omap2-uart";
128 reg = <0x48022000 0x2000>;
129 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
130 ti,hwmods = "uart2";
131 status = "disabled";
132 };
133
134 uart2: serial@48024000 {
135 compatible = "ti,am4372-uart","ti,omap2-uart";
136 reg = <0x48024000 0x2000>;
137 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
138 ti,hwmods = "uart3";
139 status = "disabled";
140 };
141
142 uart3: serial@481a6000 {
143 compatible = "ti,am4372-uart","ti,omap2-uart";
144 reg = <0x481a6000 0x2000>;
145 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
146 ti,hwmods = "uart4";
147 status = "disabled";
148 };
149
150 uart4: serial@481a8000 {
151 compatible = "ti,am4372-uart","ti,omap2-uart";
152 reg = <0x481a8000 0x2000>;
153 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
154 ti,hwmods = "uart5";
155 status = "disabled";
156 };
157
158 uart5: serial@481aa000 {
159 compatible = "ti,am4372-uart","ti,omap2-uart";
160 reg = <0x481aa000 0x2000>;
161 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
162 ti,hwmods = "uart6";
163 status = "disabled";
6cfd8117
AM		 164 };
165
9e3269b8
LV		 166 mailbox: mailbox@480C8000 {
167 compatible = "ti,omap4-mailbox";
168 reg = <0x480C8000 0x200>;
169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
170 ti,hwmods = "mailbox";
171 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <8>;
9e3269b8
LV		 173 };
174
6cfd8117
AM		 175 timer1: timer@44e31000 {
176 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
177 reg = <0x44e31000 0x400>;
178 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
179 ti,timer-alwon;
73456012 180 ti,hwmods = "timer1";
6cfd8117
AM		 181 };
182
183 timer2: timer@48040000 {
184 compatible = "ti,am4372-timer","ti,am335x-timer";
185 reg = <0x48040000 0x400>;
186 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 187 ti,hwmods = "timer2";
188 };
189
190 timer3: timer@48042000 {
191 compatible = "ti,am4372-timer","ti,am335x-timer";
192 reg = <0x48042000 0x400>;
193 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
194 ti,hwmods = "timer3";
195 status = "disabled";
196 };
197
198 timer4: timer@48044000 {
199 compatible = "ti,am4372-timer","ti,am335x-timer";
200 reg = <0x48044000 0x400>;
201 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
202 ti,timer-pwm;
203 ti,hwmods = "timer4";
204 status = "disabled";
205 };
206
207 timer5: timer@48046000 {
208 compatible = "ti,am4372-timer","ti,am335x-timer";
209 reg = <0x48046000 0x400>;
210 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
211 ti,timer-pwm;
212 ti,hwmods = "timer5";
213 status = "disabled";
214 };
215
216 timer6: timer@48048000 {
217 compatible = "ti,am4372-timer","ti,am335x-timer";
218 reg = <0x48048000 0x400>;
219 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
220 ti,timer-pwm;
221 ti,hwmods = "timer6";
222 status = "disabled";
223 };
224
225 timer7: timer@4804a000 {
226 compatible = "ti,am4372-timer","ti,am335x-timer";
227 reg = <0x4804a000 0x400>;
228 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
229 ti,timer-pwm;
230 ti,hwmods = "timer7";
231 status = "disabled";
232 };
233
234 timer8: timer@481c1000 {
235 compatible = "ti,am4372-timer","ti,am335x-timer";
236 reg = <0x481c1000 0x400>;
237 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
238 ti,hwmods = "timer8";
239 status = "disabled";
240 };
241
242 timer9: timer@4833d000 {
243 compatible = "ti,am4372-timer","ti,am335x-timer";
244 reg = <0x4833d000 0x400>;
245 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
246 ti,hwmods = "timer9";
247 status = "disabled";
248 };
249
250 timer10: timer@4833f000 {
251 compatible = "ti,am4372-timer","ti,am335x-timer";
252 reg = <0x4833f000 0x400>;
253 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
254 ti,hwmods = "timer10";
255 status = "disabled";
256 };
257
258 timer11: timer@48341000 {
259 compatible = "ti,am4372-timer","ti,am335x-timer";
260 reg = <0x48341000 0x400>;
261 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
262 ti,hwmods = "timer11";
263 status = "disabled";
6cfd8117
AM		 264 };
265
266 counter32k: counter@44e86000 {
267 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
268 reg = <0x44e86000 0x40>;
73456012
AM		 269 ti,hwmods = "counter_32k";
270 };
271
08ecb28a 272 rtc: rtc@44e3e000 {
73456012
AM		 273 compatible = "ti,am4372-rtc","ti,da830-rtc";
274 reg = <0x44e3e000 0x1000>;
275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
277 ti,hwmods = "rtc";
278 status = "disabled";
279 };
280
08ecb28a 281 wdt: wdt@44e35000 {
73456012
AM		 282 compatible = "ti,am4372-wdt","ti,omap3-wdt";
283 reg = <0x44e35000 0x1000>;
284 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
285 ti,hwmods = "wd_timer2";
73456012
AM		 286 };
287
288 gpio0: gpio@44e07000 {
289 compatible = "ti,am4372-gpio","ti,omap4-gpio";
290 reg = <0x44e07000 0x1000>;
291 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 ti,hwmods = "gpio1";
297 status = "disabled";
298 };
299
300 gpio1: gpio@4804c000 {
301 compatible = "ti,am4372-gpio","ti,omap4-gpio";
302 reg = <0x4804c000 0x1000>;
303 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 ti,hwmods = "gpio2";
309 status = "disabled";
310 };
311
312 gpio2: gpio@481ac000 {
313 compatible = "ti,am4372-gpio","ti,omap4-gpio";
314 reg = <0x481ac000 0x1000>;
315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 ti,hwmods = "gpio3";
321 status = "disabled";
322 };
323
324 gpio3: gpio@481ae000 {
325 compatible = "ti,am4372-gpio","ti,omap4-gpio";
326 reg = <0x481ae000 0x1000>;
327 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 ti,hwmods = "gpio4";
333 status = "disabled";
334 };
335
336 gpio4: gpio@48320000 {
337 compatible = "ti,am4372-gpio","ti,omap4-gpio";
338 reg = <0x48320000 0x1000>;
339 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 ti,hwmods = "gpio5";
345 status = "disabled";
346 };
347
348 gpio5: gpio@48322000 {
349 compatible = "ti,am4372-gpio","ti,omap4-gpio";
350 reg = <0x48322000 0x1000>;
351 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 ti,hwmods = "gpio6";
357 status = "disabled";
358 };
359
fd4a8a68
SA		 360 hwspinlock: spinlock@480ca000 {
361 compatible = "ti,omap4-hwspinlock";
362 reg = <0x480ca000 0x1000>;
363 ti,hwmods = "spinlock";
364 #hwlock-cells = <1>;
365 };
366
73456012
AM		 367 i2c0: i2c@44e0b000 {
368 compatible = "ti,am4372-i2c","ti,omap4-i2c";
369 reg = <0x44e0b000 0x1000>;
370 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "i2c1";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376
377 i2c1: i2c@4802a000 {
378 compatible = "ti,am4372-i2c","ti,omap4-i2c";
379 reg = <0x4802a000 0x1000>;
380 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "i2c2";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
386
387 i2c2: i2c@4819c000 {
388 compatible = "ti,am4372-i2c","ti,omap4-i2c";
389 reg = <0x4819c000 0x1000>;
390 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
391 ti,hwmods = "i2c3";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 };
396
397 spi0: spi@48030000 {
398 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
399 reg = <0x48030000 0x400>;
400 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401 ti,hwmods = "spi0";
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
406
9e3269b8
LV		 407 mmc1: mmc@48060000 {
408 compatible = "ti,omap4-hsmmc";
409 reg = <0x48060000 0x1000>;
410 ti,hwmods = "mmc1";
411 ti,dual-volt;
412 ti,needs-special-reset;
413 dmas = <&edma 24
414 &edma 25>;
415 dma-names = "tx", "rx";
416 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
417 status = "disabled";
418 };
419
420 mmc2: mmc@481d8000 {
421 compatible = "ti,omap4-hsmmc";
422 reg = <0x481d8000 0x1000>;
423 ti,hwmods = "mmc2";
424 ti,needs-special-reset;
425 dmas = <&edma 2
426 &edma 3>;
427 dma-names = "tx", "rx";
428 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
429 status = "disabled";
430 };
431
432 mmc3: mmc@47810000 {
433 compatible = "ti,omap4-hsmmc";
434 reg = <0x47810000 0x1000>;
435 ti,hwmods = "mmc3";
436 ti,needs-special-reset;
437 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
438 status = "disabled";
439 };
440
73456012
AM		 441 spi1: spi@481a0000 {
442 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
443 reg = <0x481a0000 0x400>;
444 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
445 ti,hwmods = "spi1";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
451 spi2: spi@481a2000 {
452 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
453 reg = <0x481a2000 0x400>;
454 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
455 ti,hwmods = "spi2";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460
461 spi3: spi@481a4000 {
462 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
463 reg = <0x481a4000 0x400>;
464 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
465 ti,hwmods = "spi3";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
471 spi4: spi@48345000 {
472 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
473 reg = <0x48345000 0x400>;
474 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
475 ti,hwmods = "spi4";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
481 mac: ethernet@4a100000 {
482 compatible = "ti,am4372-cpsw","ti,cpsw";
483 reg = <0x4a100000 0x800
484 0x4a101200 0x100>;
485 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
486 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
487 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
488 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 489 #address-cells = <1>;
490 #size-cells = <1>;
73456012 491 ti,hwmods = "cpgmac0";
de21b26e
GC		 492 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
493 clock-names = "fck", "cpts";
73456012 494 status = "disabled";
9e3269b8
LV		 495 cpdma_channels = <8>;
496 ale_entries = <1024>;
497 bd_ram_size = <0x2000>;
498 no_bd_ram = <0>;
499 rx_descs = <64>;
500 mac_control = <0x20>;
501 slaves = <2>;
502 active_slave = <0>;
503 cpts_clock_mult = <0x80000000>;
504 cpts_clock_shift = <29>;
505 ranges;
506
507 davinci_mdio: mdio@4a101000 {
508 compatible = "ti,am4372-mdio","ti,davinci_mdio";
509 reg = <0x4a101000 0x100>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 ti,hwmods = "davinci_mdio";
513 bus_freq = <1000000>;
514 status = "disabled";
515 };
516
517 cpsw_emac0: slave@4a100200 {
518 /* Filled in by U-Boot */
519 mac-address = [ 00 00 00 00 00 00 ];
520 };
521
522 cpsw_emac1: slave@4a100300 {
523 /* Filled in by U-Boot */
524 mac-address = [ 00 00 00 00 00 00 ];
525 };
a9682cfb
M		 526
527 phy_sel: cpsw-phy-sel@44e10650 {
528 compatible = "ti,am43xx-cpsw-phy-sel";
529 reg= <0x44e10650 0x4>;
530 reg-names = "gmii-sel";
531 };
73456012
AM		 532 };
533
534 epwmss0: epwmss@48300000 {
535 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
536 reg = <0x48300000 0x10>;
9e3269b8
LV		 537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges;
73456012
AM		 540 ti,hwmods = "epwmss0";
541 status = "disabled";
9e3269b8
LV		 542
543 ecap0: ecap@48300100 {
544 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 545 #pwm-cells = <3>;
9e3269b8
LV		 546 reg = <0x48300100 0x80>;
547 ti,hwmods = "ecap0";
548 status = "disabled";
549 };
550
551 ehrpwm0: ehrpwm@48300200 {
552 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 553 #pwm-cells = <3>;
9e3269b8
LV		 554 reg = <0x48300200 0x80>;
555 ti,hwmods = "ehrpwm0";
556 status = "disabled";
557 };
73456012
AM		 558 };
559
560 epwmss1: epwmss@48302000 {
561 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
562 reg = <0x48302000 0x10>;
9e3269b8
LV		 563 #address-cells = <1>;
564 #size-cells = <1>;
565 ranges;
73456012
AM		 566 ti,hwmods = "epwmss1";
567 status = "disabled";
9e3269b8
LV		 568
569 ecap1: ecap@48302100 {
570 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 571 #pwm-cells = <3>;
9e3269b8
LV		 572 reg = <0x48302100 0x80>;
573 ti,hwmods = "ecap1";
574 status = "disabled";
575 };
576
577 ehrpwm1: ehrpwm@48302200 {
578 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 579 #pwm-cells = <3>;
9e3269b8
LV		 580 reg = <0x48302200 0x80>;
581 ti,hwmods = "ehrpwm1";
582 status = "disabled";
583 };
73456012
AM		 584 };
585
586 epwmss2: epwmss@48304000 {
587 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
588 reg = <0x48304000 0x10>;
9e3269b8
LV		 589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges;
73456012
AM		 592 ti,hwmods = "epwmss2";
593 status = "disabled";
9e3269b8
LV		 594
595 ecap2: ecap@48304100 {
596 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
aa842305 597 #pwm-cells = <3>;
9e3269b8
LV		 598 reg = <0x48304100 0x80>;
599 ti,hwmods = "ecap2";
600 status = "disabled";
601 };
602
603 ehrpwm2: ehrpwm@48304200 {
604 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 605 #pwm-cells = <3>;
9e3269b8
LV		 606 reg = <0x48304200 0x80>;
607 ti,hwmods = "ehrpwm2";
608 status = "disabled";
609 };
73456012
AM		 610 };
611
612 epwmss3: epwmss@48306000 {
613 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
614 reg = <0x48306000 0x10>;
9e3269b8
LV		 615 #address-cells = <1>;
616 #size-cells = <1>;
617 ranges;
73456012
AM		 618 ti,hwmods = "epwmss3";
619 status = "disabled";
9e3269b8
LV		 620
621 ehrpwm3: ehrpwm@48306200 {
622 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 623 #pwm-cells = <3>;
9e3269b8
LV		 624 reg = <0x48306200 0x80>;
625 ti,hwmods = "ehrpwm3";
626 status = "disabled";
627 };
73456012
AM		 628 };
629
630 epwmss4: epwmss@48308000 {
631 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
632 reg = <0x48308000 0x10>;
9e3269b8
LV		 633 #address-cells = <1>;
634 #size-cells = <1>;
635 ranges;
73456012
AM		 636 ti,hwmods = "epwmss4";
637 status = "disabled";
9e3269b8
LV		 638
639 ehrpwm4: ehrpwm@48308200 {
640 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 641 #pwm-cells = <3>;
9e3269b8
LV		 642 reg = <0x48308200 0x80>;
643 ti,hwmods = "ehrpwm4";
644 status = "disabled";
645 };
73456012
AM		 646 };
647
648 epwmss5: epwmss@4830a000 {
649 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
650 reg = <0x4830a000 0x10>;
9e3269b8
LV		 651 #address-cells = <1>;
652 #size-cells = <1>;
653 ranges;
73456012
AM		 654 ti,hwmods = "epwmss5";
655 status = "disabled";
9e3269b8
LV		 656
657 ehrpwm5: ehrpwm@4830a200 {
658 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
aa842305 659 #pwm-cells = <3>;
9e3269b8
LV		 660 reg = <0x4830a200 0x80>;
661 ti,hwmods = "ehrpwm5";
662 status = "disabled";
663 };
664 };
665
666 sham: sham@53100000 {
667 compatible = "ti,omap5-sham";
668 ti,hwmods = "sham";
669 reg = <0x53100000 0x300>;
670 dmas = <&edma 36>;
671 dma-names = "rx";
672 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 673 };
6e70a510
JF		 674
675 aes: aes@53501000 {
676 compatible = "ti,omap4-aes";
677 ti,hwmods = "aes";
678 reg = <0x53501000 0xa0>;
679 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 680 dmas = <&edma 6
681 &edma 5>;
682 dma-names = "tx", "rx";
6e70a510 683 };
099f3a85
JF		 684
685 des: des@53701000 {
686 compatible = "ti,omap4-des";
687 ti,hwmods = "des";
688 reg = <0x53701000 0xa0>;
689 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 690 dmas = <&edma 34
691 &edma 33>;
692 dma-names = "tx", "rx";
099f3a85 693 };
9e3269b8 694
b9c95bf4
PU		 695 mcasp0: mcasp@48038000 {
696 compatible = "ti,am33xx-mcasp-audio";
697 ti,hwmods = "mcasp0";
698 reg = <0x48038000 0x2000>,
699 <0x46000000 0x400000>;
700 reg-names = "mpu", "dat";
701 interrupts = <80>, <81>;
ae107d06 702 interrupt-names = "tx", "rx";
b9c95bf4
PU		 703 status = "disabled";
704 dmas = <&edma 8>,
705 <&edma 9>;
706 dma-names = "tx", "rx";
707 };
708
709 mcasp1: mcasp@4803C000 {
710 compatible = "ti,am33xx-mcasp-audio";
711 ti,hwmods = "mcasp1";
712 reg = <0x4803C000 0x2000>,
713 <0x46400000 0x400000>;
714 reg-names = "mpu", "dat";
715 interrupts = <82>, <83>;
ae107d06 716 interrupt-names = "tx", "rx";
b9c95bf4
PU		 717 status = "disabled";
718 dmas = <&edma 10>,
719 <&edma 11>;
720 dma-names = "tx", "rx";
721 };
f68e355c
PG		 722
723 elm: elm@48080000 {
724 compatible = "ti,am3352-elm";
725 reg = <0x48080000 0x2000>;
726 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
727 ti,hwmods = "elm";
728 clocks = <&l4ls_gclk>;
729 clock-names = "fck";
730 status = "disabled";
731 };
732
733 gpmc: gpmc@50000000 {
734 compatible = "ti,am3352-gpmc";
735 ti,hwmods = "gpmc";
736 clocks = <&l3s_gclk>;
737 clock-names = "fck";
738 reg = <0x50000000 0x2000>;
739 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
740 gpmc,num-cs = <7>;
741 gpmc,num-waitpins = <2>;
742 #address-cells = <2>;
743 #size-cells = <1>;
744 status = "disabled";
745 };
a0ae47ea
GC		 746
747 am43xx_control_usb2phy1: control-phy@44e10620 {
748 compatible = "ti,control-phy-usb2-am437";
749 reg = <0x44e10620 0x4>;
750 reg-names = "power";
751 };
752
753 am43xx_control_usb2phy2: control-phy@0x44e10628 {
754 compatible = "ti,control-phy-usb2-am437";
755 reg = <0x44e10628 0x4>;
756 reg-names = "power";
757 };
758
759 ocp2scp0: ocp2scp@483a8000 {
760 compatible = "ti,omap-ocp2scp";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges;
764 ti,hwmods = "ocp2scp0";
765
766 usb2_phy1: phy@483a8000 {
767 compatible = "ti,am437x-usb2";
768 reg = <0x483a8000 0x8000>;
769 ctrl-module = <&am43xx_control_usb2phy1>;
770 clocks = <&usb_phy0_always_on_clk32k>,
771 <&usb_otg_ss0_refclk960m>;
772 clock-names = "wkupclk", "refclk";
773 #phy-cells = <0>;
774 status = "disabled";
775 };
776 };
777
778 ocp2scp1: ocp2scp@483e8000 {
779 compatible = "ti,omap-ocp2scp";
780 #address-cells = <1>;
781 #size-cells = <1>;
782 ranges;
783 ti,hwmods = "ocp2scp1";
784
785 usb2_phy2: phy@483e8000 {
786 compatible = "ti,am437x-usb2";
787 reg = <0x483e8000 0x8000>;
788 ctrl-module = <&am43xx_control_usb2phy2>;
789 clocks = <&usb_phy1_always_on_clk32k>,
790 <&usb_otg_ss1_refclk960m>;
791 clock-names = "wkupclk", "refclk";
792 #phy-cells = <0>;
793 status = "disabled";
794 };
795 };
796
797 dwc3_1: omap_dwc3@48380000 {
798 compatible = "ti,am437x-dwc3";
799 ti,hwmods = "usb_otg_ss0";
800 reg = <0x48380000 0x10000>;
801 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
802 #address-cells = <1>;
803 #size-cells = <1>;
804 utmi-mode = <1>;
805 ranges;
806
807 usb1: usb@48390000 {
808 compatible = "synopsys,dwc3";
809 reg = <0x48390000 0x17000>;
810 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
811 phys = <&usb2_phy1>;
812 phy-names = "usb2-phy";
813 maximum-speed = "high-speed";
814 dr_mode = "otg";
815 status = "disabled";
816 };
817 };
818
819 dwc3_2: omap_dwc3@483c0000 {
820 compatible = "ti,am437x-dwc3";
821 ti,hwmods = "usb_otg_ss1";
822 reg = <0x483c0000 0x10000>;
823 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
824 #address-cells = <1>;
825 #size-cells = <1>;
826 utmi-mode = <1>;
827 ranges;
828
829 usb2: usb@483d0000 {
830 compatible = "synopsys,dwc3";
831 reg = <0x483d0000 0x17000>;
832 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
833 phys = <&usb2_phy2>;
834 phy-names = "usb2-phy";
835 maximum-speed = "high-speed";
836 dr_mode = "otg";
837 status = "disabled";
838 };
839 };
2a1a5043
SP		 840
841 qspi: qspi@47900000 {
842 compatible = "ti,am4372-qspi";
843 reg = <0x47900000 0x100>;
844 #address-cells = <1>;
845 #size-cells = <0>;
846 ti,hwmods = "qspi";
847 interrupts = <0 138 0x4>;
848 num-cs = <4>;
849 status = "disabled";
850 };
741cac5f
SP		 851
852 hdq: hdq@48347000 {
853 compatible = "ti,am43xx-hdq";
854 reg = <0x48347000 0x1000>;
855 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&func_12m_clk>;
857 clock-names = "fck";
858 ti,hwmods = "hdq1w";
859 status = "disabled";
860 };
8c793367
SP		 861
862 dss: dss@4832a000 {
863 compatible = "ti,omap3-dss";
864 reg = <0x4832a000 0x200>;
865 status = "disabled";
866 ti,hwmods = "dss_core";
867 clocks = <&disp_clk>;
868 clock-names = "fck";
869 #address-cells = <1>;
870 #size-cells = <1>;
871 ranges;
872
08ecb28a 873 dispc: dispc@4832a400 {
8c793367
SP		 874 compatible = "ti,omap3-dispc";
875 reg = <0x4832a400 0x400>;
876 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
877 ti,hwmods = "dss_dispc";
878 clocks = <&disp_clk>;
879 clock-names = "fck";
880 };
881
882 rfbi: rfbi@4832a800 {
883 compatible = "ti,omap3-rfbi";
884 reg = <0x4832a800 0x100>;
885 ti,hwmods = "dss_rfbi";
886 clocks = <&disp_clk>;
887 clock-names = "fck";
888 };
889 };
6cfd8117
AM		 890 };
891};
6a679208
TK		 892
893/include/ "am43xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)