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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[linux-2.6-block.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
6cfd8117
AM		 14/ {
15 compatible = "ti,am4372", "ti,am43";
7136d457 16 interrupt-parent = <&wakeupgen>;
75813028
JMC		 17 #address-cells = <1>;
18 #size-cells = <1>;
ce95077d 19 chosen { };
6cfd8117 20
9194cf4d 21 memory@0 {
75813028
JMC		 22 device_type = "memory";
23 reg = <0 0>;
24 };
6cfd8117
AM		 25
26 aliases {
6a968678
NM		 27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
6cfd8117 30 serial0 = &uart0;
71256d9d
SN		 31 serial1 = &uart1;
32 serial2 = &uart2;
33 serial3 = &uart3;
34 serial4 = &uart4;
35 serial5 = &uart5;
9e3269b8
LV		 36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
e05edea4 38 spi0 = &qspi;
6cfd8117
AM		 39 };
40
41 cpus {
738c7409
AM		 42 #address-cells = <1>;
43 #size-cells = <0>;
08ecb28a 44 cpu: cpu@0 {
6cfd8117 45 compatible = "arm,cortex-a9";
738c7409
AM		 46 device_type = "cpu";
47 reg = <0>;
8d766fa2
NM		 48
49 clocks = <&dpll_mpu_ck>;
50 clock-names = "cpu";
51
6da9c792
DG		 52 operating-points-v2 = <&cpu0_opp_table>;
53 ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
54 ti,syscon-rev = <&scm_conf 0x600>;
55
8d766fa2 56 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 57 };
58 };
59
6da9c792
DG		 60 cpu0_opp_table: opp_table0 {
61 compatible = "operating-points-v2";
62
63 opp50@300000000 {
64 opp-hz = /bits/ 64 <300000000>;
65 opp-microvolt = <950000 931000 969000>;
66 opp-supported-hw = <0xFF 0x01>;
67 opp-suspend;
68 };
69
70 opp100@600000000 {
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <1100000 1078000 1122000>;
73 opp-supported-hw = <0xFF 0x04>;
74 };
75
76 opp120@720000000 {
77 opp-hz = /bits/ 64 <720000000>;
78 opp-microvolt = <1200000 1176000 1224000>;
79 opp-supported-hw = <0xFF 0x08>;
80 };
81
82 oppturbo@800000000 {
83 opp-hz = /bits/ 64 <800000000>;
84 opp-microvolt = <1260000 1234800 1285200>;
85 opp-supported-hw = <0xFF 0x10>;
86 };
87
88 oppnitro@1000000000 {
89 opp-hz = /bits/ 64 <1000000000>;
90 opp-microvolt = <1325000 1298500 1351500>;
91 opp-supported-hw = <0xFF 0x20>;
92 };
93 };
94
6cfd8117
AM		 95 gic: interrupt-controller@48241000 {
96 compatible = "arm,cortex-a9-gic";
97 interrupt-controller;
98 #interrupt-cells = <3>;
99 reg = <0x48241000 0x1000>,
100 <0x48240100 0x0100>;
7136d457
MZ		 101 interrupt-parent = <&gic>;
102 };
103
104 wakeupgen: interrupt-controller@48281000 {
105 compatible = "ti,omap4-wugen-mpu";
106 interrupt-controller;
107 #interrupt-cells = <3>;
108 reg = <0x48281000 0x1000>;
109 interrupt-parent = <&gic>;
6cfd8117
AM		 110 };
111
8cbd4c2f
FB		 112 scu: scu@48240000 {
113 compatible = "arm,cortex-a9-scu";
114 reg = <0x48240000 0x100>;
115 };
116
117 global_timer: timer@48240200 {
118 compatible = "arm,cortex-a9-global-timer";
119 reg = <0x48240200 0x100>;
84fb225a 120 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 121 interrupt-parent = <&gic>;
14054fb1 122 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 123 };
124
125 local_timer: timer@48240600 {
126 compatible = "arm,cortex-a9-twd-timer";
127 reg = <0x48240600 0x100>;
84fb225a 128 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 129 interrupt-parent = <&gic>;
14054fb1 130 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 131 };
132
9e3269b8
LV		 133 l2-cache-controller@48242000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x48242000 0x1000>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
f515f814 140 ocp@44000000 {
2eeddb8a 141 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges;
9e3269b8 145 ti,hwmods = "l3_main";
2eeddb8a
AM		 146 reg = <0x44000000 0x400000
147 0x44800000 0x400000>;
148 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 150
83a5d6c9
TK		 151 l4_wkup: l4_wkup@44c00000 {
152 compatible = "ti,am4-l4-wkup", "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges = <0 0x44c00000 0x287000>;
6a679208 156
34020422
SA		 157 wkup_m3: wkup_m3@100000 {
158 compatible = "ti,am4372-wkup-m3";
159 reg = <0x100000 0x4000>,
160 <0x180000 0x2000>;
161 reg-names = "umem", "dmem";
162 ti,hwmods = "wkup_m3";
163 ti,pm-firmware = "am335x-pm-firmware.elf";
164 };
165
83a5d6c9
TK		 166 prcm: prcm@1f0000 {
167 compatible = "ti,am4-prcm";
168 reg = <0x1f0000 0x11000>;
6e487001 169 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6a679208 170
83a5d6c9
TK		 171 prcm_clocks: clocks {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
6a679208 175
83a5d6c9
TK		 176 prcm_clockdomains: clockdomains {
177 };
6a679208
TK		 178 };
179
83a5d6c9
TK		 180 scm: scm@210000 {
181 compatible = "ti,am4-scm", "simple-bus";
182 reg = <0x210000 0x4000>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 ranges = <0 0x210000 0x4000>;
186
187 am43xx_pinmux: pinmux@800 {
188 compatible = "ti,am437-padconf",
189 "pinctrl-single";
190 reg = <0x800 0x31c>;
191 #address-cells = <1>;
192 #size-cells = <0>;
be76fd31 193 #pinctrl-cells = <1>;
83a5d6c9
TK		 194 #interrupt-cells = <1>;
195 interrupt-controller;
196 pinctrl-single,register-width = <32>;
197 pinctrl-single,function-mask = <0xffffffff>;
198 };
199
200 scm_conf: scm_conf@0 {
201 compatible = "syscon";
202 reg = <0x0 0x800>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205
206 scm_clocks: clocks {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 };
210 };
211
c9ab94df
SA		 212 wkup_m3_ipc: wkup_m3_ipc@1324 {
213 compatible = "ti,am4372-wkup-m3-ipc";
214 reg = <0x1324 0x44>;
215 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
216 ti,rproc = <&wkup_m3>;
217 mboxes = <&mailbox &mbox_wkupm3>;
218 };
219
cce1ee00
PU		 220 edma_xbar: dma-router@f90 {
221 compatible = "ti,am335x-edma-crossbar";
222 reg = <0xf90 0x40>;
223 #dma-cells = <3>;
224 dma-requests = <64>;
225 dma-masters = <&edma>;
226 };
227
83a5d6c9
TK		 228 scm_clockdomains: clockdomains {
229 };
6a679208
TK		 230 };
231 };
232
fff75ee1
DG		 233 emif: emif@4c000000 {
234 compatible = "ti,emif-am4372";
235 reg = <0x4c000000 0x1000000>;
236 ti,hwmods = "emif";
237 };
238
9e3269b8 239 edma: edma@49000000 {
cce1ee00
PU		 240 compatible = "ti,edma3-tpcc";
241 ti,hwmods = "tpcc";
242 reg = <0x49000000 0x10000>;
243 reg-names = "edma3_cc";
9e3269b8 244 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
cce1ee00
PU		 245 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a5206553 247 interrupt-names = "edma3_ccint", "edma3_mperr",
cce1ee00
PU		 248 "edma3_ccerrint";
249 dma-requests = <64>;
250 #dma-cells = <2>;
251
252 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
253 <&edma_tptc2 0>;
254
d41676dd 255 ti,edma-memcpy-channels = <58 59>;
cce1ee00
PU		 256 };
257
258 edma_tptc0: tptc@49800000 {
259 compatible = "ti,edma3-tptc";
260 ti,hwmods = "tptc0";
261 reg = <0x49800000 0x100000>;
262 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "edma3_tcerrint";
264 };
265
266 edma_tptc1: tptc@49900000 {
267 compatible = "ti,edma3-tptc";
268 ti,hwmods = "tptc1";
269 reg = <0x49900000 0x100000>;
270 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "edma3_tcerrint";
272 };
273
274 edma_tptc2: tptc@49a00000 {
275 compatible = "ti,edma3-tptc";
276 ti,hwmods = "tptc2";
277 reg = <0x49a00000 0x100000>;
278 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-names = "edma3_tcerrint";
9e3269b8 280 };
6cfd8117
AM		 281
282 uart0: serial@44e09000 {
283 compatible = "ti,am4372-uart","ti,omap2-uart";
284 reg = <0x44e09000 0x2000>;
285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 286 ti,hwmods = "uart1";
287 };
288
289 uart1: serial@48022000 {
290 compatible = "ti,am4372-uart","ti,omap2-uart";
291 reg = <0x48022000 0x2000>;
292 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
293 ti,hwmods = "uart2";
294 status = "disabled";
295 };
296
297 uart2: serial@48024000 {
298 compatible = "ti,am4372-uart","ti,omap2-uart";
299 reg = <0x48024000 0x2000>;
300 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "uart3";
302 status = "disabled";
303 };
304
305 uart3: serial@481a6000 {
306 compatible = "ti,am4372-uart","ti,omap2-uart";
307 reg = <0x481a6000 0x2000>;
308 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "uart4";
310 status = "disabled";
311 };
312
313 uart4: serial@481a8000 {
314 compatible = "ti,am4372-uart","ti,omap2-uart";
315 reg = <0x481a8000 0x2000>;
316 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
317 ti,hwmods = "uart5";
318 status = "disabled";
319 };
320
321 uart5: serial@481aa000 {
322 compatible = "ti,am4372-uart","ti,omap2-uart";
323 reg = <0x481aa000 0x2000>;
324 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
325 ti,hwmods = "uart6";
326 status = "disabled";
6cfd8117
AM		 327 };
328
9e3269b8
LV		 329 mailbox: mailbox@480C8000 {
330 compatible = "ti,omap4-mailbox";
331 reg = <0x480C8000 0x200>;
332 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
333 ti,hwmods = "mailbox";
24df0453 334 #mbox-cells = <1>;
9e3269b8
LV		 335 ti,mbox-num-users = <4>;
336 ti,mbox-num-fifos = <8>;
d27704d1 337 mbox_wkupm3: wkup_m3 {
cf19f3ab 338 ti,mbox-send-noirq;
d27704d1
SA		 339 ti,mbox-tx = <0 0 0>;
340 ti,mbox-rx = <0 0 3>;
341 };
9e3269b8
LV		 342 };
343
6cfd8117
AM		 344 timer1: timer@44e31000 {
345 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
346 reg = <0x44e31000 0x400>;
347 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
348 ti,timer-alwon;
73456012 349 ti,hwmods = "timer1";
6cfd8117
AM		 350 };
351
352 timer2: timer@48040000 {
353 compatible = "ti,am4372-timer","ti,am335x-timer";
354 reg = <0x48040000 0x400>;
355 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 356 ti,hwmods = "timer2";
357 };
358
359 timer3: timer@48042000 {
360 compatible = "ti,am4372-timer","ti,am335x-timer";
361 reg = <0x48042000 0x400>;
362 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
363 ti,hwmods = "timer3";
364 status = "disabled";
365 };
366
367 timer4: timer@48044000 {
368 compatible = "ti,am4372-timer","ti,am335x-timer";
369 reg = <0x48044000 0x400>;
370 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
371 ti,timer-pwm;
372 ti,hwmods = "timer4";
373 status = "disabled";
374 };
375
376 timer5: timer@48046000 {
377 compatible = "ti,am4372-timer","ti,am335x-timer";
378 reg = <0x48046000 0x400>;
379 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
380 ti,timer-pwm;
381 ti,hwmods = "timer5";
382 status = "disabled";
383 };
384
385 timer6: timer@48048000 {
386 compatible = "ti,am4372-timer","ti,am335x-timer";
387 reg = <0x48048000 0x400>;
388 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
389 ti,timer-pwm;
390 ti,hwmods = "timer6";
391 status = "disabled";
392 };
393
394 timer7: timer@4804a000 {
395 compatible = "ti,am4372-timer","ti,am335x-timer";
396 reg = <0x4804a000 0x400>;
397 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
398 ti,timer-pwm;
399 ti,hwmods = "timer7";
400 status = "disabled";
401 };
402
403 timer8: timer@481c1000 {
404 compatible = "ti,am4372-timer","ti,am335x-timer";
405 reg = <0x481c1000 0x400>;
406 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
407 ti,hwmods = "timer8";
408 status = "disabled";
409 };
410
411 timer9: timer@4833d000 {
412 compatible = "ti,am4372-timer","ti,am335x-timer";
413 reg = <0x4833d000 0x400>;
414 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
415 ti,hwmods = "timer9";
416 status = "disabled";
417 };
418
419 timer10: timer@4833f000 {
420 compatible = "ti,am4372-timer","ti,am335x-timer";
421 reg = <0x4833f000 0x400>;
422 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
423 ti,hwmods = "timer10";
424 status = "disabled";
425 };
426
427 timer11: timer@48341000 {
428 compatible = "ti,am4372-timer","ti,am335x-timer";
429 reg = <0x48341000 0x400>;
430 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
431 ti,hwmods = "timer11";
432 status = "disabled";
6cfd8117
AM		 433 };
434
435 counter32k: counter@44e86000 {
436 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
437 reg = <0x44e86000 0x40>;
73456012
AM		 438 ti,hwmods = "counter_32k";
439 };
440
08ecb28a 441 rtc: rtc@44e3e000 {
05743b3a
K		 442 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
443 "ti,da830-rtc";
73456012
AM		 444 reg = <0x44e3e000 0x1000>;
445 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
447 ti,hwmods = "rtc";
fff51e77
K		 448 clocks = <&clk_32768_ck>;
449 clock-names = "int-clk";
73456012
AM		 450 status = "disabled";
451 };
452
08ecb28a 453 wdt: wdt@44e35000 {
73456012
AM		 454 compatible = "ti,am4372-wdt","ti,omap3-wdt";
455 reg = <0x44e35000 0x1000>;
456 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
457 ti,hwmods = "wd_timer2";
73456012
AM		 458 };
459
460 gpio0: gpio@44e07000 {
461 compatible = "ti,am4372-gpio","ti,omap4-gpio";
462 reg = <0x44e07000 0x1000>;
463 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
464 gpio-controller;
465 #gpio-cells = <2>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
468 ti,hwmods = "gpio1";
469 status = "disabled";
470 };
471
472 gpio1: gpio@4804c000 {
473 compatible = "ti,am4372-gpio","ti,omap4-gpio";
474 reg = <0x4804c000 0x1000>;
475 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
480 ti,hwmods = "gpio2";
481 status = "disabled";
482 };
483
484 gpio2: gpio@481ac000 {
485 compatible = "ti,am4372-gpio","ti,omap4-gpio";
486 reg = <0x481ac000 0x1000>;
487 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 ti,hwmods = "gpio3";
493 status = "disabled";
494 };
495
496 gpio3: gpio@481ae000 {
497 compatible = "ti,am4372-gpio","ti,omap4-gpio";
498 reg = <0x481ae000 0x1000>;
499 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
500 gpio-controller;
501 #gpio-cells = <2>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
504 ti,hwmods = "gpio4";
505 status = "disabled";
506 };
507
508 gpio4: gpio@48320000 {
509 compatible = "ti,am4372-gpio","ti,omap4-gpio";
510 reg = <0x48320000 0x1000>;
511 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
512 gpio-controller;
513 #gpio-cells = <2>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 ti,hwmods = "gpio5";
517 status = "disabled";
518 };
519
520 gpio5: gpio@48322000 {
521 compatible = "ti,am4372-gpio","ti,omap4-gpio";
522 reg = <0x48322000 0x1000>;
523 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 ti,hwmods = "gpio6";
529 status = "disabled";
530 };
531
fd4a8a68
SA		 532 hwspinlock: spinlock@480ca000 {
533 compatible = "ti,omap4-hwspinlock";
534 reg = <0x480ca000 0x1000>;
535 ti,hwmods = "spinlock";
536 #hwlock-cells = <1>;
537 };
538
73456012
AM		 539 i2c0: i2c@44e0b000 {
540 compatible = "ti,am4372-i2c","ti,omap4-i2c";
541 reg = <0x44e0b000 0x1000>;
542 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
543 ti,hwmods = "i2c1";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548
549 i2c1: i2c@4802a000 {
550 compatible = "ti,am4372-i2c","ti,omap4-i2c";
551 reg = <0x4802a000 0x1000>;
552 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "i2c2";
554 #address-cells = <1>;
555 #size-cells = <0>;
556 status = "disabled";
557 };
558
559 i2c2: i2c@4819c000 {
560 compatible = "ti,am4372-i2c","ti,omap4-i2c";
561 reg = <0x4819c000 0x1000>;
562 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "i2c3";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 status = "disabled";
567 };
568
569 spi0: spi@48030000 {
570 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
571 reg = <0x48030000 0x400>;
572 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
573 ti,hwmods = "spi0";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 status = "disabled";
577 };
578
9e3269b8
LV		 579 mmc1: mmc@48060000 {
580 compatible = "ti,omap4-hsmmc";
581 reg = <0x48060000 0x1000>;
582 ti,hwmods = "mmc1";
583 ti,dual-volt;
584 ti,needs-special-reset;
cce1ee00
PU		 585 dmas = <&edma 24 0>,
586 <&edma 25 0>;
9e3269b8
LV		 587 dma-names = "tx", "rx";
588 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
589 status = "disabled";
590 };
591
592 mmc2: mmc@481d8000 {
593 compatible = "ti,omap4-hsmmc";
594 reg = <0x481d8000 0x1000>;
595 ti,hwmods = "mmc2";
596 ti,needs-special-reset;
cce1ee00
PU		 597 dmas = <&edma 2 0>,
598 <&edma 3 0>;
9e3269b8
LV		 599 dma-names = "tx", "rx";
600 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
601 status = "disabled";
602 };
603
604 mmc3: mmc@47810000 {
605 compatible = "ti,omap4-hsmmc";
606 reg = <0x47810000 0x1000>;
607 ti,hwmods = "mmc3";
608 ti,needs-special-reset;
609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
610 status = "disabled";
611 };
612
73456012
AM		 613 spi1: spi@481a0000 {
614 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
615 reg = <0x481a0000 0x400>;
616 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
617 ti,hwmods = "spi1";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 status = "disabled";
621 };
622
623 spi2: spi@481a2000 {
624 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
625 reg = <0x481a2000 0x400>;
626 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
627 ti,hwmods = "spi2";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
633 spi3: spi@481a4000 {
634 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
635 reg = <0x481a4000 0x400>;
636 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
637 ti,hwmods = "spi3";
638 #address-cells = <1>;
639 #size-cells = <0>;
640 status = "disabled";
641 };
642
643 spi4: spi@48345000 {
644 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
645 reg = <0x48345000 0x400>;
646 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
647 ti,hwmods = "spi4";
648 #address-cells = <1>;
649 #size-cells = <0>;
650 status = "disabled";
651 };
652
653 mac: ethernet@4a100000 {
654 compatible = "ti,am4372-cpsw","ti,cpsw";
655 reg = <0x4a100000 0x800
656 0x4a101200 0x100>;
657 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
658 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
659 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
660 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 661 #address-cells = <1>;
662 #size-cells = <1>;
73456012 663 ti,hwmods = "cpgmac0";
dff8a207
K		 664 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
665 <&dpll_clksel_mac_clk>;
666 clock-names = "fck", "cpts", "50mclk";
667 assigned-clocks = <&dpll_clksel_mac_clk>;
668 assigned-clock-rates = <50000000>;
73456012 669 status = "disabled";
9e3269b8
LV		 670 cpdma_channels = <8>;
671 ale_entries = <1024>;
672 bd_ram_size = <0x2000>;
9e3269b8
LV		 673 mac_control = <0x20>;
674 slaves = <2>;
675 active_slave = <0>;
676 cpts_clock_mult = <0x80000000>;
677 cpts_clock_shift = <29>;
678 ranges;
cec42849 679 syscon = <&scm_conf>;
9e3269b8
LV		 680
681 davinci_mdio: mdio@4a101000 {
9efd1a6f 682 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
9e3269b8
LV		 683 reg = <0x4a101000 0x100>;
684 #address-cells = <1>;
685 #size-cells = <0>;
686 ti,hwmods = "davinci_mdio";
687 bus_freq = <1000000>;
688 status = "disabled";
689 };
690
691 cpsw_emac0: slave@4a100200 {
692 /* Filled in by U-Boot */
693 mac-address = [ 00 00 00 00 00 00 ];
694 };
695
696 cpsw_emac1: slave@4a100300 {
697 /* Filled in by U-Boot */
698 mac-address = [ 00 00 00 00 00 00 ];
699 };
a9682cfb
M		 700
701 phy_sel: cpsw-phy-sel@44e10650 {
702 compatible = "ti,am43xx-cpsw-phy-sel";
703 reg= <0x44e10650 0x4>;
704 reg-names = "gmii-sel";
705 };
73456012
AM		 706 };
707
708 epwmss0: epwmss@48300000 {
709 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
710 reg = <0x48300000 0x10>;
9e3269b8
LV		 711 #address-cells = <1>;
712 #size-cells = <1>;
713 ranges;
73456012
AM		 714 ti,hwmods = "epwmss0";
715 status = "disabled";
9e3269b8
LV		 716
717 ecap0: ecap@48300100 {
229110c1
FCJ		 718 compatible = "ti,am4372-ecap",
719 "ti,am3352-ecap",
720 "ti,am33xx-ecap";
aa842305 721 #pwm-cells = <3>;
9e3269b8 722 reg = <0x48300100 0x80>;
229110c1
FCJ		 723 clocks = <&l4ls_gclk>;
724 clock-names = "fck";
9e3269b8
LV		 725 status = "disabled";
726 };
727
dce2a652 728 ehrpwm0: pwm@48300200 {
229110c1
FCJ		 729 compatible = "ti,am4372-ehrpwm",
730 "ti,am3352-ehrpwm",
731 "ti,am33xx-ehrpwm";
aa842305 732 #pwm-cells = <3>;
9e3269b8 733 reg = <0x48300200 0x80>;
229110c1
FCJ		 734 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
735 clock-names = "tbclk", "fck";
9e3269b8
LV		 736 status = "disabled";
737 };
73456012
AM		 738 };
739
740 epwmss1: epwmss@48302000 {
741 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
742 reg = <0x48302000 0x10>;
9e3269b8
LV		 743 #address-cells = <1>;
744 #size-cells = <1>;
745 ranges;
73456012
AM		 746 ti,hwmods = "epwmss1";
747 status = "disabled";
9e3269b8
LV		 748
749 ecap1: ecap@48302100 {
229110c1
FCJ		 750 compatible = "ti,am4372-ecap",
751 "ti,am3352-ecap",
752 "ti,am33xx-ecap";
aa842305 753 #pwm-cells = <3>;
9e3269b8 754 reg = <0x48302100 0x80>;
229110c1
FCJ		 755 clocks = <&l4ls_gclk>;
756 clock-names = "fck";
9e3269b8
LV		 757 status = "disabled";
758 };
759
dce2a652 760 ehrpwm1: pwm@48302200 {
229110c1
FCJ		 761 compatible = "ti,am4372-ehrpwm",
762 "ti,am3352-ehrpwm",
763 "ti,am33xx-ehrpwm";
aa842305 764 #pwm-cells = <3>;
9e3269b8 765 reg = <0x48302200 0x80>;
229110c1
FCJ		 766 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
767 clock-names = "tbclk", "fck";
9e3269b8
LV		 768 status = "disabled";
769 };
73456012
AM		 770 };
771
772 epwmss2: epwmss@48304000 {
773 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
774 reg = <0x48304000 0x10>;
9e3269b8
LV		 775 #address-cells = <1>;
776 #size-cells = <1>;
777 ranges;
73456012
AM		 778 ti,hwmods = "epwmss2";
779 status = "disabled";
9e3269b8
LV		 780
781 ecap2: ecap@48304100 {
229110c1
FCJ		 782 compatible = "ti,am4372-ecap",
783 "ti,am3352-ecap",
784 "ti,am33xx-ecap";
aa842305 785 #pwm-cells = <3>;
9e3269b8 786 reg = <0x48304100 0x80>;
229110c1
FCJ		 787 clocks = <&l4ls_gclk>;
788 clock-names = "fck";
9e3269b8
LV		 789 status = "disabled";
790 };
791
dce2a652 792 ehrpwm2: pwm@48304200 {
229110c1
FCJ		 793 compatible = "ti,am4372-ehrpwm",
794 "ti,am3352-ehrpwm",
795 "ti,am33xx-ehrpwm";
aa842305 796 #pwm-cells = <3>;
9e3269b8 797 reg = <0x48304200 0x80>;
229110c1
FCJ		 798 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
799 clock-names = "tbclk", "fck";
9e3269b8
LV		 800 status = "disabled";
801 };
73456012
AM		 802 };
803
804 epwmss3: epwmss@48306000 {
805 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
806 reg = <0x48306000 0x10>;
9e3269b8
LV		 807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges;
73456012
AM		 810 ti,hwmods = "epwmss3";
811 status = "disabled";
9e3269b8 812
dce2a652 813 ehrpwm3: pwm@48306200 {
229110c1
FCJ		 814 compatible = "ti,am4372-ehrpwm",
815 "ti,am3352-ehrpwm",
816 "ti,am33xx-ehrpwm";
aa842305 817 #pwm-cells = <3>;
9e3269b8 818 reg = <0x48306200 0x80>;
229110c1
FCJ		 819 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
820 clock-names = "tbclk", "fck";
9e3269b8
LV		 821 status = "disabled";
822 };
73456012
AM		 823 };
824
825 epwmss4: epwmss@48308000 {
826 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
827 reg = <0x48308000 0x10>;
9e3269b8
LV		 828 #address-cells = <1>;
829 #size-cells = <1>;
830 ranges;
73456012
AM		 831 ti,hwmods = "epwmss4";
832 status = "disabled";
9e3269b8 833
dce2a652 834 ehrpwm4: pwm@48308200 {
229110c1
FCJ		 835 compatible = "ti,am4372-ehrpwm",
836 "ti,am3352-ehrpwm",
837 "ti,am33xx-ehrpwm";
aa842305 838 #pwm-cells = <3>;
9e3269b8 839 reg = <0x48308200 0x80>;
229110c1
FCJ		 840 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
841 clock-names = "tbclk", "fck";
9e3269b8
LV		 842 status = "disabled";
843 };
73456012
AM		 844 };
845
846 epwmss5: epwmss@4830a000 {
847 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
848 reg = <0x4830a000 0x10>;
9e3269b8
LV		 849 #address-cells = <1>;
850 #size-cells = <1>;
851 ranges;
73456012
AM		 852 ti,hwmods = "epwmss5";
853 status = "disabled";
9e3269b8 854
dce2a652 855 ehrpwm5: pwm@4830a200 {
229110c1
FCJ		 856 compatible = "ti,am4372-ehrpwm",
857 "ti,am3352-ehrpwm",
858 "ti,am33xx-ehrpwm";
aa842305 859 #pwm-cells = <3>;
9e3269b8 860 reg = <0x4830a200 0x80>;
229110c1
FCJ		 861 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
862 clock-names = "tbclk", "fck";
9e3269b8
LV		 863 status = "disabled";
864 };
865 };
866
0f39f7b9
V		 867 tscadc: tscadc@44e0d000 {
868 compatible = "ti,am3359-tscadc";
869 reg = <0x44e0d000 0x1000>;
870 ti,hwmods = "adc_tsc";
871 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&adc_tsc_fck>;
873 clock-names = "fck";
874 status = "disabled";
b6a4280a
M		 875 dmas = <&edma 53 0>, <&edma 57 0>;
876 dma-names = "fifo0", "fifo1";
0f39f7b9
V		 877
878 tsc {
879 compatible = "ti,am3359-tsc";
880 };
881
882 adc {
883 #io-channel-cells = <1>;
884 compatible = "ti,am3359-adc";
885 };
886
887 };
888
9e3269b8
LV		 889 sham: sham@53100000 {
890 compatible = "ti,omap5-sham";
891 ti,hwmods = "sham";
892 reg = <0x53100000 0x300>;
cce1ee00 893 dmas = <&edma 36 0>;
9e3269b8
LV		 894 dma-names = "rx";
895 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 896 };
6e70a510
JF		 897
898 aes: aes@53501000 {
899 compatible = "ti,omap4-aes";
900 ti,hwmods = "aes";
901 reg = <0x53501000 0xa0>;
902 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 903 dmas = <&edma 6 0>,
904 <&edma 5 0>;
9e3269b8 905 dma-names = "tx", "rx";
6e70a510 906 };
099f3a85
JF		 907
908 des: des@53701000 {
909 compatible = "ti,omap4-des";
910 ti,hwmods = "des";
911 reg = <0x53701000 0xa0>;
912 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 913 dmas = <&edma 34 0>,
914 <&edma 33 0>;
9e3269b8 915 dma-names = "tx", "rx";
099f3a85 916 };
9e3269b8 917
52c7c913
LV		 918 rng: rng@48310000 {
919 compatible = "ti,omap4-rng";
920 ti,hwmods = "rng";
921 reg = <0x48310000 0x2000>;
922 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
923 };
924
b9c95bf4
PU		 925 mcasp0: mcasp@48038000 {
926 compatible = "ti,am33xx-mcasp-audio";
927 ti,hwmods = "mcasp0";
928 reg = <0x48038000 0x2000>,
929 <0x46000000 0x400000>;
930 reg-names = "mpu", "dat";
931 interrupts = <80>, <81>;
ae107d06 932 interrupt-names = "tx", "rx";
b9c95bf4 933 status = "disabled";
cce1ee00
PU		 934 dmas = <&edma 8 2>,
935 <&edma 9 2>;
b9c95bf4
PU		 936 dma-names = "tx", "rx";
937 };
938
939 mcasp1: mcasp@4803C000 {
940 compatible = "ti,am33xx-mcasp-audio";
941 ti,hwmods = "mcasp1";
942 reg = <0x4803C000 0x2000>,
943 <0x46400000 0x400000>;
944 reg-names = "mpu", "dat";
945 interrupts = <82>, <83>;
ae107d06 946 interrupt-names = "tx", "rx";
b9c95bf4 947 status = "disabled";
cce1ee00
PU		 948 dmas = <&edma 10 2>,
949 <&edma 11 2>;
b9c95bf4
PU		 950 dma-names = "tx", "rx";
951 };
f68e355c
PG		 952
953 elm: elm@48080000 {
954 compatible = "ti,am3352-elm";
955 reg = <0x48080000 0x2000>;
956 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
957 ti,hwmods = "elm";
958 clocks = <&l4ls_gclk>;
959 clock-names = "fck";
960 status = "disabled";
961 };
962
963 gpmc: gpmc@50000000 {
964 compatible = "ti,am3352-gpmc";
965 ti,hwmods = "gpmc";
883cbc90 966 dmas = <&edma 52 0>;
201c7e33 967 dma-names = "rxtx";
f68e355c
PG		 968 clocks = <&l3s_gclk>;
969 clock-names = "fck";
970 reg = <0x50000000 0x2000>;
971 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
972 gpmc,num-cs = <7>;
973 gpmc,num-waitpins = <2>;
974 #address-cells = <2>;
975 #size-cells = <1>;
be3f39c8
RQ		 976 interrupt-controller;
977 #interrupt-cells = <2>;
9e08c2da
RQ		 978 gpio-controller;
979 #gpio-cells = <2>;
f68e355c
PG		 980 status = "disabled";
981 };
a0ae47ea 982
a0ae47ea 983 ocp2scp0: ocp2scp@483a8000 {
20431db9 984 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 985 #address-cells = <1>;
986 #size-cells = <1>;
987 ranges;
988 ti,hwmods = "ocp2scp0";
989
990 usb2_phy1: phy@483a8000 {
991 compatible = "ti,am437x-usb2";
992 reg = <0x483a8000 0x8000>;
2338c76a 993 syscon-phy-power = <&scm_conf 0x620>;
a0ae47ea
GC		 994 clocks = <&usb_phy0_always_on_clk32k>,
995 <&usb_otg_ss0_refclk960m>;
996 clock-names = "wkupclk", "refclk";
997 #phy-cells = <0>;
998 status = "disabled";
999 };
1000 };
1001
1002 ocp2scp1: ocp2scp@483e8000 {
20431db9 1003 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 1004 #address-cells = <1>;
1005 #size-cells = <1>;
1006 ranges;
1007 ti,hwmods = "ocp2scp1";
1008
1009 usb2_phy2: phy@483e8000 {
1010 compatible = "ti,am437x-usb2";
1011 reg = <0x483e8000 0x8000>;
2338c76a 1012 syscon-phy-power = <&scm_conf 0x628>;
a0ae47ea
GC		 1013 clocks = <&usb_phy1_always_on_clk32k>,
1014 <&usb_otg_ss1_refclk960m>;
1015 clock-names = "wkupclk", "refclk";
1016 #phy-cells = <0>;
1017 status = "disabled";
1018 };
1019 };
1020
1021 dwc3_1: omap_dwc3@48380000 {
1022 compatible = "ti,am437x-dwc3";
1023 ti,hwmods = "usb_otg_ss0";
1024 reg = <0x48380000 0x10000>;
1025 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 utmi-mode = <1>;
1029 ranges;
1030
1031 usb1: usb@48390000 {
1032 compatible = "synopsys,dwc3";
4b143f0f 1033 reg = <0x48390000 0x10000>;
1d20e4bf
FB		 1034 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "peripheral",
1038 "host",
1039 "otg";
a0ae47ea
GC		 1040 phys = <&usb2_phy1>;
1041 phy-names = "usb2-phy";
1042 maximum-speed = "high-speed";
1043 dr_mode = "otg";
1044 status = "disabled";
60f0e628
FB		 1045 snps,dis_u3_susphy_quirk;
1046 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1047 };
1048 };
1049
1050 dwc3_2: omap_dwc3@483c0000 {
1051 compatible = "ti,am437x-dwc3";
1052 ti,hwmods = "usb_otg_ss1";
1053 reg = <0x483c0000 0x10000>;
1054 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1055 #address-cells = <1>;
1056 #size-cells = <1>;
1057 utmi-mode = <1>;
1058 ranges;
1059
1060 usb2: usb@483d0000 {
1061 compatible = "synopsys,dwc3";
4b143f0f 1062 reg = <0x483d0000 0x10000>;
1d20e4bf
FB		 1063 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1066 interrupt-names = "peripheral",
1067 "host",
1068 "otg";
a0ae47ea
GC		 1069 phys = <&usb2_phy2>;
1070 phy-names = "usb2-phy";
1071 maximum-speed = "high-speed";
1072 dr_mode = "otg";
1073 status = "disabled";
60f0e628
FB		 1074 snps,dis_u3_susphy_quirk;
1075 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1076 };
1077 };
2a1a5043
SP		 1078
1079 qspi: qspi@47900000 {
1080 compatible = "ti,am4372-qspi";
2acb6c3e
V		 1081 reg = <0x47900000 0x100>,
1082 <0x30000000 0x4000000>;
1083 reg-names = "qspi_base", "qspi_mmap";
2a1a5043
SP		 1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 ti,hwmods = "qspi";
1087 interrupts = <0 138 0x4>;
1088 num-cs = <4>;
1089 status = "disabled";
1090 };
741cac5f
SP		 1091
1092 hdq: hdq@48347000 {
a895b8a0 1093 compatible = "ti,am4372-hdq";
741cac5f
SP		 1094 reg = <0x48347000 0x1000>;
1095 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&func_12m_clk>;
1097 clock-names = "fck";
1098 ti,hwmods = "hdq1w";
1099 status = "disabled";
1100 };
8c793367
SP		 1101
1102 dss: dss@4832a000 {
1103 compatible = "ti,omap3-dss";
1104 reg = <0x4832a000 0x200>;
1105 status = "disabled";
1106 ti,hwmods = "dss_core";
1107 clocks = <&disp_clk>;
1108 clock-names = "fck";
1109 #address-cells = <1>;
1110 #size-cells = <1>;
1111 ranges;
1112
08ecb28a 1113 dispc: dispc@4832a400 {
8c793367
SP		 1114 compatible = "ti,omap3-dispc";
1115 reg = <0x4832a400 0x400>;
1116 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1117 ti,hwmods = "dss_dispc";
1118 clocks = <&disp_clk>;
1119 clock-names = "fck";
1120 };
1121
1122 rfbi: rfbi@4832a800 {
1123 compatible = "ti,omap3-rfbi";
1124 reg = <0x4832a800 0x100>;
1125 ti,hwmods = "dss_rfbi";
1126 clocks = <&disp_clk>;
1127 clock-names = "fck";
22a5dc10 1128 status = "disabled";
8c793367
SP		 1129 };
1130 };
8b9a2810
RN		 1131
1132 ocmcram: ocmcram@40300000 {
1133 compatible = "mmio-sram";
1134 reg = <0x40300000 0x40000>; /* 256k */
1135 };
9e63b0d4
RQ		 1136
1137 dcan0: can@481cc000 {
1138 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1139 ti,hwmods = "d_can0";
1140 clocks = <&dcan0_fck>;
1141 clock-names = "fck";
1142 reg = <0x481cc000 0x2000>;
83a5d6c9 1143 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 1144 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1145 status = "disabled";
1146 };
1147
1148 dcan1: can@481d0000 {
1149 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1150 ti,hwmods = "d_can1";
1151 clocks = <&dcan1_fck>;
1152 clock-names = "fck";
1153 reg = <0x481d0000 0x2000>;
83a5d6c9 1154 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 1155 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1156 status = "disabled";
1157 };
9d0df0a6
BP		 1158
1159 vpfe0: vpfe@48326000 {
1160 compatible = "ti,am437x-vpfe";
1161 reg = <0x48326000 0x2000>;
1162 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1163 ti,hwmods = "vpfe0";
1164 status = "disabled";
1165 };
1166
1167 vpfe1: vpfe@48328000 {
1168 compatible = "ti,am437x-vpfe";
1169 reg = <0x48328000 0x2000>;
1170 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1171 ti,hwmods = "vpfe1";
1172 status = "disabled";
1173 };
6cfd8117
AM		 1174 };
1175};
6a679208
TK		 1176
1177/include/ "am43xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)