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Linux 4.10-rc1
[linux-2.6-block.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
6cfd8117
AM		 14/ {
15 compatible = "ti,am4372", "ti,am43";
7136d457 16 interrupt-parent = <&wakeupgen>;
75813028
JMC		 17 #address-cells = <1>;
18 #size-cells = <1>;
6cfd8117 19
9194cf4d 20 memory@0 {
75813028
JMC		 21 device_type = "memory";
22 reg = <0 0>;
23 };
6cfd8117
AM		 24
25 aliases {
6a968678
NM		 26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
6cfd8117 29 serial0 = &uart0;
71256d9d
SN		 30 serial1 = &uart1;
31 serial2 = &uart2;
32 serial3 = &uart3;
33 serial4 = &uart4;
34 serial5 = &uart5;
9e3269b8
LV		 35 ethernet0 = &cpsw_emac0;
36 ethernet1 = &cpsw_emac1;
e05edea4 37 spi0 = &qspi;
6cfd8117
AM		 38 };
39
40 cpus {
738c7409
AM		 41 #address-cells = <1>;
42 #size-cells = <0>;
08ecb28a 43 cpu: cpu@0 {
6cfd8117 44 compatible = "arm,cortex-a9";
738c7409
AM		 45 device_type = "cpu";
46 reg = <0>;
8d766fa2
NM		 47
48 clocks = <&dpll_mpu_ck>;
49 clock-names = "cpu";
50
6da9c792
DG		 51 operating-points-v2 = <&cpu0_opp_table>;
52 ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
53 ti,syscon-rev = <&scm_conf 0x600>;
54
8d766fa2 55 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 56 };
57 };
58
6da9c792
DG		 59 cpu0_opp_table: opp_table0 {
60 compatible = "operating-points-v2";
61
62 opp50@300000000 {
63 opp-hz = /bits/ 64 <300000000>;
64 opp-microvolt = <950000 931000 969000>;
65 opp-supported-hw = <0xFF 0x01>;
66 opp-suspend;
67 };
68
69 opp100@600000000 {
70 opp-hz = /bits/ 64 <600000000>;
71 opp-microvolt = <1100000 1078000 1122000>;
72 opp-supported-hw = <0xFF 0x04>;
73 };
74
75 opp120@720000000 {
76 opp-hz = /bits/ 64 <720000000>;
77 opp-microvolt = <1200000 1176000 1224000>;
78 opp-supported-hw = <0xFF 0x08>;
79 };
80
81 oppturbo@800000000 {
82 opp-hz = /bits/ 64 <800000000>;
83 opp-microvolt = <1260000 1234800 1285200>;
84 opp-supported-hw = <0xFF 0x10>;
85 };
86
87 oppnitro@1000000000 {
88 opp-hz = /bits/ 64 <1000000000>;
89 opp-microvolt = <1325000 1298500 1351500>;
90 opp-supported-hw = <0xFF 0x20>;
91 };
92 };
93
6cfd8117
AM		 94 gic: interrupt-controller@48241000 {
95 compatible = "arm,cortex-a9-gic";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = <0x48241000 0x1000>,
99 <0x48240100 0x0100>;
7136d457
MZ		 100 interrupt-parent = <&gic>;
101 };
102
103 wakeupgen: interrupt-controller@48281000 {
104 compatible = "ti,omap4-wugen-mpu";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 reg = <0x48281000 0x1000>;
108 interrupt-parent = <&gic>;
6cfd8117
AM		 109 };
110
8cbd4c2f
FB		 111 scu: scu@48240000 {
112 compatible = "arm,cortex-a9-scu";
113 reg = <0x48240000 0x100>;
114 };
115
116 global_timer: timer@48240200 {
117 compatible = "arm,cortex-a9-global-timer";
118 reg = <0x48240200 0x100>;
84fb225a 119 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 120 interrupt-parent = <&gic>;
14054fb1 121 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 122 };
123
124 local_timer: timer@48240600 {
125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x48240600 0x100>;
84fb225a 127 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 128 interrupt-parent = <&gic>;
14054fb1 129 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 130 };
131
9e3269b8
LV		 132 l2-cache-controller@48242000 {
133 compatible = "arm,pl310-cache";
134 reg = <0x48242000 0x1000>;
135 cache-unified;
136 cache-level = <2>;
137 };
138
f515f814 139 ocp@44000000 {
2eeddb8a 140 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges;
9e3269b8 144 ti,hwmods = "l3_main";
2eeddb8a
AM		 145 reg = <0x44000000 0x400000
146 0x44800000 0x400000>;
147 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 149
83a5d6c9
TK		 150 l4_wkup: l4_wkup@44c00000 {
151 compatible = "ti,am4-l4-wkup", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0 0x44c00000 0x287000>;
6a679208 155
34020422
SA		 156 wkup_m3: wkup_m3@100000 {
157 compatible = "ti,am4372-wkup-m3";
158 reg = <0x100000 0x4000>,
159 <0x180000 0x2000>;
160 reg-names = "umem", "dmem";
161 ti,hwmods = "wkup_m3";
162 ti,pm-firmware = "am335x-pm-firmware.elf";
163 };
164
83a5d6c9
TK		 165 prcm: prcm@1f0000 {
166 compatible = "ti,am4-prcm";
167 reg = <0x1f0000 0x11000>;
6e487001 168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6a679208 169
83a5d6c9
TK		 170 prcm_clocks: clocks {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
6a679208 174
83a5d6c9
TK		 175 prcm_clockdomains: clockdomains {
176 };
6a679208
TK		 177 };
178
83a5d6c9
TK		 179 scm: scm@210000 {
180 compatible = "ti,am4-scm", "simple-bus";
181 reg = <0x210000 0x4000>;
182 #address-cells = <1>;
183 #size-cells = <1>;
184 ranges = <0 0x210000 0x4000>;
185
186 am43xx_pinmux: pinmux@800 {
187 compatible = "ti,am437-padconf",
188 "pinctrl-single";
189 reg = <0x800 0x31c>;
190 #address-cells = <1>;
191 #size-cells = <0>;
be76fd31 192 #pinctrl-cells = <1>;
83a5d6c9
TK		 193 #interrupt-cells = <1>;
194 interrupt-controller;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0xffffffff>;
197 };
198
199 scm_conf: scm_conf@0 {
200 compatible = "syscon";
201 reg = <0x0 0x800>;
202 #address-cells = <1>;
203 #size-cells = <1>;
204
205 scm_clocks: clocks {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
209 };
210
c9ab94df
SA		 211 wkup_m3_ipc: wkup_m3_ipc@1324 {
212 compatible = "ti,am4372-wkup-m3-ipc";
213 reg = <0x1324 0x44>;
214 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
215 ti,rproc = <&wkup_m3>;
216 mboxes = <&mailbox &mbox_wkupm3>;
217 };
218
cce1ee00
PU		 219 edma_xbar: dma-router@f90 {
220 compatible = "ti,am335x-edma-crossbar";
221 reg = <0xf90 0x40>;
222 #dma-cells = <3>;
223 dma-requests = <64>;
224 dma-masters = <&edma>;
225 };
226
83a5d6c9
TK		 227 scm_clockdomains: clockdomains {
228 };
6a679208
TK		 229 };
230 };
231
fff75ee1
DG		 232 emif: emif@4c000000 {
233 compatible = "ti,emif-am4372";
234 reg = <0x4c000000 0x1000000>;
235 ti,hwmods = "emif";
236 };
237
9e3269b8 238 edma: edma@49000000 {
cce1ee00
PU		 239 compatible = "ti,edma3-tpcc";
240 ti,hwmods = "tpcc";
241 reg = <0x49000000 0x10000>;
242 reg-names = "edma3_cc";
9e3269b8 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
cce1ee00
PU		 244 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a5206553 246 interrupt-names = "edma3_ccint", "edma3_mperr",
cce1ee00
PU		 247 "edma3_ccerrint";
248 dma-requests = <64>;
249 #dma-cells = <2>;
250
251 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
252 <&edma_tptc2 0>;
253
d41676dd 254 ti,edma-memcpy-channels = <58 59>;
cce1ee00
PU		 255 };
256
257 edma_tptc0: tptc@49800000 {
258 compatible = "ti,edma3-tptc";
259 ti,hwmods = "tptc0";
260 reg = <0x49800000 0x100000>;
261 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-names = "edma3_tcerrint";
263 };
264
265 edma_tptc1: tptc@49900000 {
266 compatible = "ti,edma3-tptc";
267 ti,hwmods = "tptc1";
268 reg = <0x49900000 0x100000>;
269 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-names = "edma3_tcerrint";
271 };
272
273 edma_tptc2: tptc@49a00000 {
274 compatible = "ti,edma3-tptc";
275 ti,hwmods = "tptc2";
276 reg = <0x49a00000 0x100000>;
277 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-names = "edma3_tcerrint";
9e3269b8 279 };
6cfd8117
AM		 280
281 uart0: serial@44e09000 {
282 compatible = "ti,am4372-uart","ti,omap2-uart";
283 reg = <0x44e09000 0x2000>;
284 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 285 ti,hwmods = "uart1";
286 };
287
288 uart1: serial@48022000 {
289 compatible = "ti,am4372-uart","ti,omap2-uart";
290 reg = <0x48022000 0x2000>;
291 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
292 ti,hwmods = "uart2";
293 status = "disabled";
294 };
295
296 uart2: serial@48024000 {
297 compatible = "ti,am4372-uart","ti,omap2-uart";
298 reg = <0x48024000 0x2000>;
299 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
300 ti,hwmods = "uart3";
301 status = "disabled";
302 };
303
304 uart3: serial@481a6000 {
305 compatible = "ti,am4372-uart","ti,omap2-uart";
306 reg = <0x481a6000 0x2000>;
307 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
308 ti,hwmods = "uart4";
309 status = "disabled";
310 };
311
312 uart4: serial@481a8000 {
313 compatible = "ti,am4372-uart","ti,omap2-uart";
314 reg = <0x481a8000 0x2000>;
315 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
316 ti,hwmods = "uart5";
317 status = "disabled";
318 };
319
320 uart5: serial@481aa000 {
321 compatible = "ti,am4372-uart","ti,omap2-uart";
322 reg = <0x481aa000 0x2000>;
323 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
324 ti,hwmods = "uart6";
325 status = "disabled";
6cfd8117
AM		 326 };
327
9e3269b8
LV		 328 mailbox: mailbox@480C8000 {
329 compatible = "ti,omap4-mailbox";
330 reg = <0x480C8000 0x200>;
331 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
332 ti,hwmods = "mailbox";
24df0453 333 #mbox-cells = <1>;
9e3269b8
LV		 334 ti,mbox-num-users = <4>;
335 ti,mbox-num-fifos = <8>;
d27704d1 336 mbox_wkupm3: wkup_m3 {
cf19f3ab 337 ti,mbox-send-noirq;
d27704d1
SA		 338 ti,mbox-tx = <0 0 0>;
339 ti,mbox-rx = <0 0 3>;
340 };
9e3269b8
LV		 341 };
342
6cfd8117
AM		 343 timer1: timer@44e31000 {
344 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
345 reg = <0x44e31000 0x400>;
346 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
347 ti,timer-alwon;
73456012 348 ti,hwmods = "timer1";
6cfd8117
AM		 349 };
350
351 timer2: timer@48040000 {
352 compatible = "ti,am4372-timer","ti,am335x-timer";
353 reg = <0x48040000 0x400>;
354 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 355 ti,hwmods = "timer2";
356 };
357
358 timer3: timer@48042000 {
359 compatible = "ti,am4372-timer","ti,am335x-timer";
360 reg = <0x48042000 0x400>;
361 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
362 ti,hwmods = "timer3";
363 status = "disabled";
364 };
365
366 timer4: timer@48044000 {
367 compatible = "ti,am4372-timer","ti,am335x-timer";
368 reg = <0x48044000 0x400>;
369 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
370 ti,timer-pwm;
371 ti,hwmods = "timer4";
372 status = "disabled";
373 };
374
375 timer5: timer@48046000 {
376 compatible = "ti,am4372-timer","ti,am335x-timer";
377 reg = <0x48046000 0x400>;
378 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
379 ti,timer-pwm;
380 ti,hwmods = "timer5";
381 status = "disabled";
382 };
383
384 timer6: timer@48048000 {
385 compatible = "ti,am4372-timer","ti,am335x-timer";
386 reg = <0x48048000 0x400>;
387 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
388 ti,timer-pwm;
389 ti,hwmods = "timer6";
390 status = "disabled";
391 };
392
393 timer7: timer@4804a000 {
394 compatible = "ti,am4372-timer","ti,am335x-timer";
395 reg = <0x4804a000 0x400>;
396 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
397 ti,timer-pwm;
398 ti,hwmods = "timer7";
399 status = "disabled";
400 };
401
402 timer8: timer@481c1000 {
403 compatible = "ti,am4372-timer","ti,am335x-timer";
404 reg = <0x481c1000 0x400>;
405 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "timer8";
407 status = "disabled";
408 };
409
410 timer9: timer@4833d000 {
411 compatible = "ti,am4372-timer","ti,am335x-timer";
412 reg = <0x4833d000 0x400>;
413 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "timer9";
415 status = "disabled";
416 };
417
418 timer10: timer@4833f000 {
419 compatible = "ti,am4372-timer","ti,am335x-timer";
420 reg = <0x4833f000 0x400>;
421 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
422 ti,hwmods = "timer10";
423 status = "disabled";
424 };
425
426 timer11: timer@48341000 {
427 compatible = "ti,am4372-timer","ti,am335x-timer";
428 reg = <0x48341000 0x400>;
429 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
430 ti,hwmods = "timer11";
431 status = "disabled";
6cfd8117
AM		 432 };
433
434 counter32k: counter@44e86000 {
435 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
436 reg = <0x44e86000 0x40>;
73456012
AM		 437 ti,hwmods = "counter_32k";
438 };
439
08ecb28a 440 rtc: rtc@44e3e000 {
05743b3a
K		 441 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
442 "ti,da830-rtc";
73456012
AM		 443 reg = <0x44e3e000 0x1000>;
444 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
446 ti,hwmods = "rtc";
fff51e77
K		 447 clocks = <&clk_32768_ck>;
448 clock-names = "int-clk";
73456012
AM		 449 status = "disabled";
450 };
451
08ecb28a 452 wdt: wdt@44e35000 {
73456012
AM		 453 compatible = "ti,am4372-wdt","ti,omap3-wdt";
454 reg = <0x44e35000 0x1000>;
455 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
456 ti,hwmods = "wd_timer2";
73456012
AM		 457 };
458
459 gpio0: gpio@44e07000 {
460 compatible = "ti,am4372-gpio","ti,omap4-gpio";
461 reg = <0x44e07000 0x1000>;
462 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 ti,hwmods = "gpio1";
468 status = "disabled";
469 };
470
471 gpio1: gpio@4804c000 {
472 compatible = "ti,am4372-gpio","ti,omap4-gpio";
473 reg = <0x4804c000 0x1000>;
474 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
475 gpio-controller;
476 #gpio-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 ti,hwmods = "gpio2";
480 status = "disabled";
481 };
482
483 gpio2: gpio@481ac000 {
484 compatible = "ti,am4372-gpio","ti,omap4-gpio";
485 reg = <0x481ac000 0x1000>;
486 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
487 gpio-controller;
488 #gpio-cells = <2>;
489 interrupt-controller;
490 #interrupt-cells = <2>;
491 ti,hwmods = "gpio3";
492 status = "disabled";
493 };
494
495 gpio3: gpio@481ae000 {
496 compatible = "ti,am4372-gpio","ti,omap4-gpio";
497 reg = <0x481ae000 0x1000>;
498 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
499 gpio-controller;
500 #gpio-cells = <2>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 ti,hwmods = "gpio4";
504 status = "disabled";
505 };
506
507 gpio4: gpio@48320000 {
508 compatible = "ti,am4372-gpio","ti,omap4-gpio";
509 reg = <0x48320000 0x1000>;
510 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
511 gpio-controller;
512 #gpio-cells = <2>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 ti,hwmods = "gpio5";
516 status = "disabled";
517 };
518
519 gpio5: gpio@48322000 {
520 compatible = "ti,am4372-gpio","ti,omap4-gpio";
521 reg = <0x48322000 0x1000>;
522 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
523 gpio-controller;
524 #gpio-cells = <2>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 ti,hwmods = "gpio6";
528 status = "disabled";
529 };
530
fd4a8a68
SA		 531 hwspinlock: spinlock@480ca000 {
532 compatible = "ti,omap4-hwspinlock";
533 reg = <0x480ca000 0x1000>;
534 ti,hwmods = "spinlock";
535 #hwlock-cells = <1>;
536 };
537
73456012
AM		 538 i2c0: i2c@44e0b000 {
539 compatible = "ti,am4372-i2c","ti,omap4-i2c";
540 reg = <0x44e0b000 0x1000>;
541 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "i2c1";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 status = "disabled";
546 };
547
548 i2c1: i2c@4802a000 {
549 compatible = "ti,am4372-i2c","ti,omap4-i2c";
550 reg = <0x4802a000 0x1000>;
551 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
552 ti,hwmods = "i2c2";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
557
558 i2c2: i2c@4819c000 {
559 compatible = "ti,am4372-i2c","ti,omap4-i2c";
560 reg = <0x4819c000 0x1000>;
561 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "i2c3";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 status = "disabled";
566 };
567
568 spi0: spi@48030000 {
569 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
570 reg = <0x48030000 0x400>;
571 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "spi0";
573 #address-cells = <1>;
574 #size-cells = <0>;
575 status = "disabled";
576 };
577
9e3269b8
LV		 578 mmc1: mmc@48060000 {
579 compatible = "ti,omap4-hsmmc";
580 reg = <0x48060000 0x1000>;
581 ti,hwmods = "mmc1";
582 ti,dual-volt;
583 ti,needs-special-reset;
cce1ee00
PU		 584 dmas = <&edma 24 0>,
585 <&edma 25 0>;
9e3269b8
LV		 586 dma-names = "tx", "rx";
587 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
588 status = "disabled";
589 };
590
591 mmc2: mmc@481d8000 {
592 compatible = "ti,omap4-hsmmc";
593 reg = <0x481d8000 0x1000>;
594 ti,hwmods = "mmc2";
595 ti,needs-special-reset;
cce1ee00
PU		 596 dmas = <&edma 2 0>,
597 <&edma 3 0>;
9e3269b8
LV		 598 dma-names = "tx", "rx";
599 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
600 status = "disabled";
601 };
602
603 mmc3: mmc@47810000 {
604 compatible = "ti,omap4-hsmmc";
605 reg = <0x47810000 0x1000>;
606 ti,hwmods = "mmc3";
607 ti,needs-special-reset;
608 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
609 status = "disabled";
610 };
611
73456012
AM		 612 spi1: spi@481a0000 {
613 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
614 reg = <0x481a0000 0x400>;
615 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
616 ti,hwmods = "spi1";
617 #address-cells = <1>;
618 #size-cells = <0>;
619 status = "disabled";
620 };
621
622 spi2: spi@481a2000 {
623 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
624 reg = <0x481a2000 0x400>;
625 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
626 ti,hwmods = "spi2";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 status = "disabled";
630 };
631
632 spi3: spi@481a4000 {
633 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
634 reg = <0x481a4000 0x400>;
635 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
636 ti,hwmods = "spi3";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "disabled";
640 };
641
642 spi4: spi@48345000 {
643 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
644 reg = <0x48345000 0x400>;
645 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
646 ti,hwmods = "spi4";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 status = "disabled";
650 };
651
652 mac: ethernet@4a100000 {
653 compatible = "ti,am4372-cpsw","ti,cpsw";
654 reg = <0x4a100000 0x800
655 0x4a101200 0x100>;
656 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
657 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
658 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
659 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 660 #address-cells = <1>;
661 #size-cells = <1>;
73456012 662 ti,hwmods = "cpgmac0";
dff8a207
K		 663 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
664 <&dpll_clksel_mac_clk>;
665 clock-names = "fck", "cpts", "50mclk";
666 assigned-clocks = <&dpll_clksel_mac_clk>;
667 assigned-clock-rates = <50000000>;
73456012 668 status = "disabled";
9e3269b8
LV		 669 cpdma_channels = <8>;
670 ale_entries = <1024>;
671 bd_ram_size = <0x2000>;
672 no_bd_ram = <0>;
9e3269b8
LV		 673 mac_control = <0x20>;
674 slaves = <2>;
675 active_slave = <0>;
676 cpts_clock_mult = <0x80000000>;
677 cpts_clock_shift = <29>;
678 ranges;
cec42849 679 syscon = <&scm_conf>;
9e3269b8
LV		 680
681 davinci_mdio: mdio@4a101000 {
9efd1a6f 682 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
9e3269b8
LV		 683 reg = <0x4a101000 0x100>;
684 #address-cells = <1>;
685 #size-cells = <0>;
686 ti,hwmods = "davinci_mdio";
687 bus_freq = <1000000>;
688 status = "disabled";
689 };
690
691 cpsw_emac0: slave@4a100200 {
692 /* Filled in by U-Boot */
693 mac-address = [ 00 00 00 00 00 00 ];
694 };
695
696 cpsw_emac1: slave@4a100300 {
697 /* Filled in by U-Boot */
698 mac-address = [ 00 00 00 00 00 00 ];
699 };
a9682cfb
M		 700
701 phy_sel: cpsw-phy-sel@44e10650 {
702 compatible = "ti,am43xx-cpsw-phy-sel";
703 reg= <0x44e10650 0x4>;
704 reg-names = "gmii-sel";
705 };
73456012
AM		 706 };
707
708 epwmss0: epwmss@48300000 {
709 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
710 reg = <0x48300000 0x10>;
9e3269b8
LV		 711 #address-cells = <1>;
712 #size-cells = <1>;
713 ranges;
73456012
AM		 714 ti,hwmods = "epwmss0";
715 status = "disabled";
9e3269b8
LV		 716
717 ecap0: ecap@48300100 {
229110c1
FCJ		 718 compatible = "ti,am4372-ecap",
719 "ti,am3352-ecap",
720 "ti,am33xx-ecap";
aa842305 721 #pwm-cells = <3>;
9e3269b8 722 reg = <0x48300100 0x80>;
229110c1
FCJ		 723 clocks = <&l4ls_gclk>;
724 clock-names = "fck";
9e3269b8
LV		 725 status = "disabled";
726 };
727
dce2a652 728 ehrpwm0: pwm@48300200 {
229110c1
FCJ		 729 compatible = "ti,am4372-ehrpwm",
730 "ti,am3352-ehrpwm",
731 "ti,am33xx-ehrpwm";
aa842305 732 #pwm-cells = <3>;
9e3269b8 733 reg = <0x48300200 0x80>;
229110c1
FCJ		 734 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
735 clock-names = "tbclk", "fck";
9e3269b8
LV		 736 status = "disabled";
737 };
73456012
AM		 738 };
739
740 epwmss1: epwmss@48302000 {
741 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
742 reg = <0x48302000 0x10>;
9e3269b8
LV		 743 #address-cells = <1>;
744 #size-cells = <1>;
745 ranges;
73456012
AM		 746 ti,hwmods = "epwmss1";
747 status = "disabled";
9e3269b8
LV		 748
749 ecap1: ecap@48302100 {
229110c1
FCJ		 750 compatible = "ti,am4372-ecap",
751 "ti,am3352-ecap",
752 "ti,am33xx-ecap";
aa842305 753 #pwm-cells = <3>;
9e3269b8 754 reg = <0x48302100 0x80>;
229110c1
FCJ		 755 clocks = <&l4ls_gclk>;
756 clock-names = "fck";
9e3269b8
LV		 757 status = "disabled";
758 };
759
dce2a652 760 ehrpwm1: pwm@48302200 {
229110c1
FCJ		 761 compatible = "ti,am4372-ehrpwm",
762 "ti,am3352-ehrpwm",
763 "ti,am33xx-ehrpwm";
aa842305 764 #pwm-cells = <3>;
9e3269b8 765 reg = <0x48302200 0x80>;
229110c1
FCJ		 766 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
767 clock-names = "tbclk", "fck";
9e3269b8
LV		 768 status = "disabled";
769 };
73456012
AM		 770 };
771
772 epwmss2: epwmss@48304000 {
773 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
774 reg = <0x48304000 0x10>;
9e3269b8
LV		 775 #address-cells = <1>;
776 #size-cells = <1>;
777 ranges;
73456012
AM		 778 ti,hwmods = "epwmss2";
779 status = "disabled";
9e3269b8
LV		 780
781 ecap2: ecap@48304100 {
229110c1
FCJ		 782 compatible = "ti,am4372-ecap",
783 "ti,am3352-ecap",
784 "ti,am33xx-ecap";
aa842305 785 #pwm-cells = <3>;
9e3269b8 786 reg = <0x48304100 0x80>;
229110c1
FCJ		 787 clocks = <&l4ls_gclk>;
788 clock-names = "fck";
9e3269b8
LV		 789 status = "disabled";
790 };
791
dce2a652 792 ehrpwm2: pwm@48304200 {
229110c1
FCJ		 793 compatible = "ti,am4372-ehrpwm",
794 "ti,am3352-ehrpwm",
795 "ti,am33xx-ehrpwm";
aa842305 796 #pwm-cells = <3>;
9e3269b8 797 reg = <0x48304200 0x80>;
229110c1
FCJ		 798 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
799 clock-names = "tbclk", "fck";
9e3269b8
LV		 800 status = "disabled";
801 };
73456012
AM		 802 };
803
804 epwmss3: epwmss@48306000 {
805 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
806 reg = <0x48306000 0x10>;
9e3269b8
LV		 807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges;
73456012
AM		 810 ti,hwmods = "epwmss3";
811 status = "disabled";
9e3269b8 812
dce2a652 813 ehrpwm3: pwm@48306200 {
229110c1
FCJ		 814 compatible = "ti,am4372-ehrpwm",
815 "ti,am3352-ehrpwm",
816 "ti,am33xx-ehrpwm";
aa842305 817 #pwm-cells = <3>;
9e3269b8 818 reg = <0x48306200 0x80>;
229110c1
FCJ		 819 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
820 clock-names = "tbclk", "fck";
9e3269b8
LV		 821 status = "disabled";
822 };
73456012
AM		 823 };
824
825 epwmss4: epwmss@48308000 {
826 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
827 reg = <0x48308000 0x10>;
9e3269b8
LV		 828 #address-cells = <1>;
829 #size-cells = <1>;
830 ranges;
73456012
AM		 831 ti,hwmods = "epwmss4";
832 status = "disabled";
9e3269b8 833
dce2a652 834 ehrpwm4: pwm@48308200 {
229110c1
FCJ		 835 compatible = "ti,am4372-ehrpwm",
836 "ti,am3352-ehrpwm",
837 "ti,am33xx-ehrpwm";
aa842305 838 #pwm-cells = <3>;
9e3269b8 839 reg = <0x48308200 0x80>;
229110c1
FCJ		 840 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
841 clock-names = "tbclk", "fck";
9e3269b8
LV		 842 status = "disabled";
843 };
73456012
AM		 844 };
845
846 epwmss5: epwmss@4830a000 {
847 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
848 reg = <0x4830a000 0x10>;
9e3269b8
LV		 849 #address-cells = <1>;
850 #size-cells = <1>;
851 ranges;
73456012
AM		 852 ti,hwmods = "epwmss5";
853 status = "disabled";
9e3269b8 854
dce2a652 855 ehrpwm5: pwm@4830a200 {
229110c1
FCJ		 856 compatible = "ti,am4372-ehrpwm",
857 "ti,am3352-ehrpwm",
858 "ti,am33xx-ehrpwm";
aa842305 859 #pwm-cells = <3>;
9e3269b8 860 reg = <0x4830a200 0x80>;
229110c1
FCJ		 861 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
862 clock-names = "tbclk", "fck";
9e3269b8
LV		 863 status = "disabled";
864 };
865 };
866
0f39f7b9
V		 867 tscadc: tscadc@44e0d000 {
868 compatible = "ti,am3359-tscadc";
869 reg = <0x44e0d000 0x1000>;
870 ti,hwmods = "adc_tsc";
871 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&adc_tsc_fck>;
873 clock-names = "fck";
874 status = "disabled";
b6a4280a
M		 875 dmas = <&edma 53 0>, <&edma 57 0>;
876 dma-names = "fifo0", "fifo1";
0f39f7b9
V		 877
878 tsc {
879 compatible = "ti,am3359-tsc";
880 };
881
882 adc {
883 #io-channel-cells = <1>;
884 compatible = "ti,am3359-adc";
885 };
886
887 };
888
9e3269b8
LV		 889 sham: sham@53100000 {
890 compatible = "ti,omap5-sham";
891 ti,hwmods = "sham";
892 reg = <0x53100000 0x300>;
cce1ee00 893 dmas = <&edma 36 0>;
9e3269b8
LV		 894 dma-names = "rx";
895 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 896 };
6e70a510
JF		 897
898 aes: aes@53501000 {
899 compatible = "ti,omap4-aes";
900 ti,hwmods = "aes";
901 reg = <0x53501000 0xa0>;
902 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 903 dmas = <&edma 6 0>,
904 <&edma 5 0>;
9e3269b8 905 dma-names = "tx", "rx";
6e70a510 906 };
099f3a85
JF		 907
908 des: des@53701000 {
909 compatible = "ti,omap4-des";
910 ti,hwmods = "des";
911 reg = <0x53701000 0xa0>;
912 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 913 dmas = <&edma 34 0>,
914 <&edma 33 0>;
9e3269b8 915 dma-names = "tx", "rx";
099f3a85 916 };
9e3269b8 917
52c7c913
LV		 918 rng: rng@48310000 {
919 compatible = "ti,omap4-rng";
920 ti,hwmods = "rng";
921 reg = <0x48310000 0x2000>;
922 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
923 };
924
b9c95bf4
PU		 925 mcasp0: mcasp@48038000 {
926 compatible = "ti,am33xx-mcasp-audio";
927 ti,hwmods = "mcasp0";
928 reg = <0x48038000 0x2000>,
929 <0x46000000 0x400000>;
930 reg-names = "mpu", "dat";
931 interrupts = <80>, <81>;
ae107d06 932 interrupt-names = "tx", "rx";
b9c95bf4 933 status = "disabled";
cce1ee00
PU		 934 dmas = <&edma 8 2>,
935 <&edma 9 2>;
b9c95bf4
PU		 936 dma-names = "tx", "rx";
937 };
938
939 mcasp1: mcasp@4803C000 {
940 compatible = "ti,am33xx-mcasp-audio";
941 ti,hwmods = "mcasp1";
942 reg = <0x4803C000 0x2000>,
943 <0x46400000 0x400000>;
944 reg-names = "mpu", "dat";
945 interrupts = <82>, <83>;
ae107d06 946 interrupt-names = "tx", "rx";
b9c95bf4 947 status = "disabled";
cce1ee00
PU		 948 dmas = <&edma 10 2>,
949 <&edma 11 2>;
b9c95bf4
PU		 950 dma-names = "tx", "rx";
951 };
f68e355c
PG		 952
953 elm: elm@48080000 {
954 compatible = "ti,am3352-elm";
955 reg = <0x48080000 0x2000>;
956 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
957 ti,hwmods = "elm";
958 clocks = <&l4ls_gclk>;
959 clock-names = "fck";
960 status = "disabled";
961 };
962
963 gpmc: gpmc@50000000 {
964 compatible = "ti,am3352-gpmc";
965 ti,hwmods = "gpmc";
883cbc90 966 dmas = <&edma 52 0>;
201c7e33 967 dma-names = "rxtx";
f68e355c
PG		 968 clocks = <&l3s_gclk>;
969 clock-names = "fck";
970 reg = <0x50000000 0x2000>;
971 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
972 gpmc,num-cs = <7>;
973 gpmc,num-waitpins = <2>;
974 #address-cells = <2>;
975 #size-cells = <1>;
be3f39c8
RQ		 976 interrupt-controller;
977 #interrupt-cells = <2>;
9e08c2da
RQ		 978 gpio-controller;
979 #gpio-cells = <2>;
f68e355c
PG		 980 status = "disabled";
981 };
a0ae47ea 982
a0ae47ea 983 ocp2scp0: ocp2scp@483a8000 {
20431db9 984 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 985 #address-cells = <1>;
986 #size-cells = <1>;
987 ranges;
988 ti,hwmods = "ocp2scp0";
989
990 usb2_phy1: phy@483a8000 {
991 compatible = "ti,am437x-usb2";
992 reg = <0x483a8000 0x8000>;
2338c76a 993 syscon-phy-power = <&scm_conf 0x620>;
a0ae47ea
GC		 994 clocks = <&usb_phy0_always_on_clk32k>,
995 <&usb_otg_ss0_refclk960m>;
996 clock-names = "wkupclk", "refclk";
997 #phy-cells = <0>;
998 status = "disabled";
999 };
1000 };
1001
1002 ocp2scp1: ocp2scp@483e8000 {
20431db9 1003 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 1004 #address-cells = <1>;
1005 #size-cells = <1>;
1006 ranges;
1007 ti,hwmods = "ocp2scp1";
1008
1009 usb2_phy2: phy@483e8000 {
1010 compatible = "ti,am437x-usb2";
1011 reg = <0x483e8000 0x8000>;
2338c76a 1012 syscon-phy-power = <&scm_conf 0x628>;
a0ae47ea
GC		 1013 clocks = <&usb_phy1_always_on_clk32k>,
1014 <&usb_otg_ss1_refclk960m>;
1015 clock-names = "wkupclk", "refclk";
1016 #phy-cells = <0>;
1017 status = "disabled";
1018 };
1019 };
1020
1021 dwc3_1: omap_dwc3@48380000 {
1022 compatible = "ti,am437x-dwc3";
1023 ti,hwmods = "usb_otg_ss0";
1024 reg = <0x48380000 0x10000>;
1025 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 utmi-mode = <1>;
1029 ranges;
1030
1031 usb1: usb@48390000 {
1032 compatible = "synopsys,dwc3";
4b143f0f 1033 reg = <0x48390000 0x10000>;
1d20e4bf
FB		 1034 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "peripheral",
1038 "host",
1039 "otg";
a0ae47ea
GC		 1040 phys = <&usb2_phy1>;
1041 phy-names = "usb2-phy";
1042 maximum-speed = "high-speed";
1043 dr_mode = "otg";
1044 status = "disabled";
60f0e628
FB		 1045 snps,dis_u3_susphy_quirk;
1046 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1047 };
1048 };
1049
1050 dwc3_2: omap_dwc3@483c0000 {
1051 compatible = "ti,am437x-dwc3";
1052 ti,hwmods = "usb_otg_ss1";
1053 reg = <0x483c0000 0x10000>;
1054 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1055 #address-cells = <1>;
1056 #size-cells = <1>;
1057 utmi-mode = <1>;
1058 ranges;
1059
1060 usb2: usb@483d0000 {
1061 compatible = "synopsys,dwc3";
4b143f0f 1062 reg = <0x483d0000 0x10000>;
1d20e4bf
FB		 1063 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1066 interrupt-names = "peripheral",
1067 "host",
1068 "otg";
a0ae47ea
GC		 1069 phys = <&usb2_phy2>;
1070 phy-names = "usb2-phy";
1071 maximum-speed = "high-speed";
1072 dr_mode = "otg";
1073 status = "disabled";
60f0e628
FB		 1074 snps,dis_u3_susphy_quirk;
1075 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1076 };
1077 };
2a1a5043
SP		 1078
1079 qspi: qspi@47900000 {
1080 compatible = "ti,am4372-qspi";
2acb6c3e
V		 1081 reg = <0x47900000 0x100>,
1082 <0x30000000 0x4000000>;
1083 reg-names = "qspi_base", "qspi_mmap";
2a1a5043
SP		 1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 ti,hwmods = "qspi";
1087 interrupts = <0 138 0x4>;
1088 num-cs = <4>;
1089 status = "disabled";
1090 };
741cac5f
SP		 1091
1092 hdq: hdq@48347000 {
a895b8a0 1093 compatible = "ti,am4372-hdq";
741cac5f
SP		 1094 reg = <0x48347000 0x1000>;
1095 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&func_12m_clk>;
1097 clock-names = "fck";
1098 ti,hwmods = "hdq1w";
1099 status = "disabled";
1100 };
8c793367
SP		 1101
1102 dss: dss@4832a000 {
1103 compatible = "ti,omap3-dss";
1104 reg = <0x4832a000 0x200>;
1105 status = "disabled";
1106 ti,hwmods = "dss_core";
1107 clocks = <&disp_clk>;
1108 clock-names = "fck";
1109 #address-cells = <1>;
1110 #size-cells = <1>;
1111 ranges;
1112
08ecb28a 1113 dispc: dispc@4832a400 {
8c793367
SP		 1114 compatible = "ti,omap3-dispc";
1115 reg = <0x4832a400 0x400>;
1116 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1117 ti,hwmods = "dss_dispc";
1118 clocks = <&disp_clk>;
1119 clock-names = "fck";
1120 };
1121
1122 rfbi: rfbi@4832a800 {
1123 compatible = "ti,omap3-rfbi";
1124 reg = <0x4832a800 0x100>;
1125 ti,hwmods = "dss_rfbi";
1126 clocks = <&disp_clk>;
1127 clock-names = "fck";
22a5dc10 1128 status = "disabled";
8c793367
SP		 1129 };
1130 };
8b9a2810
RN		 1131
1132 ocmcram: ocmcram@40300000 {
1133 compatible = "mmio-sram";
1134 reg = <0x40300000 0x40000>; /* 256k */
1135 };
9e63b0d4
RQ		 1136
1137 dcan0: can@481cc000 {
1138 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1139 ti,hwmods = "d_can0";
1140 clocks = <&dcan0_fck>;
1141 clock-names = "fck";
1142 reg = <0x481cc000 0x2000>;
83a5d6c9 1143 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 1144 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1145 status = "disabled";
1146 };
1147
1148 dcan1: can@481d0000 {
1149 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1150 ti,hwmods = "d_can1";
1151 clocks = <&dcan1_fck>;
1152 clock-names = "fck";
1153 reg = <0x481d0000 0x2000>;
83a5d6c9 1154 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 1155 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1156 status = "disabled";
1157 };
9d0df0a6
BP		 1158
1159 vpfe0: vpfe@48326000 {
1160 compatible = "ti,am437x-vpfe";
1161 reg = <0x48326000 0x2000>;
1162 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1163 ti,hwmods = "vpfe0";
1164 status = "disabled";
1165 };
1166
1167 vpfe1: vpfe@48328000 {
1168 compatible = "ti,am437x-vpfe";
1169 reg = <0x48328000 0x2000>;
1170 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1171 ti,hwmods = "vpfe1";
1172 status = "disabled";
1173 };
6cfd8117
AM		 1174 };
1175};
6a679208
TK		 1176
1177/include/ "am43xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)