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a0158185 TL |
1 | /* |
2 | * Device Tree Source for am3517 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include "omap3.dtsi" | |
12 | ||
13 | / { | |
14 | aliases { | |
15 | serial3 = &uart4; | |
a5e743c4 | 16 | can = &hecc; |
a0158185 TL |
17 | }; |
18 | ||
f515f814 | 19 | ocp@68000000 { |
a0158185 TL |
20 | am35x_otg_hs: am35x_otg_hs@5c040000 { |
21 | compatible = "ti,omap3-musb"; | |
22 | ti,hwmods = "am35x_otg_hs"; | |
23 | status = "disabled"; | |
24 | reg = <0x5c040000 0x1000>; | |
25 | interrupts = <71>; | |
26 | interrupt-names = "mc"; | |
27 | }; | |
28 | ||
29 | davinci_emac: ethernet@0x5c000000 { | |
30 | compatible = "ti,am3517-emac"; | |
31 | ti,hwmods = "davinci_emac"; | |
32 | status = "disabled"; | |
33 | reg = <0x5c000000 0x30000>; | |
34 | interrupts = <67 68 69 70>; | |
b8845074 | 35 | syscon = <&scm_conf>; |
a0158185 TL |
36 | ti,davinci-ctrl-reg-offset = <0x10000>; |
37 | ti,davinci-ctrl-mod-reg-offset = <0>; | |
38 | ti,davinci-ctrl-ram-offset = <0x20000>; | |
39 | ti,davinci-ctrl-ram-size = <0x2000>; | |
40 | ti,davinci-rmii-en = /bits/ 8 <1>; | |
41 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
42 | }; | |
43 | ||
44 | davinci_mdio: ethernet@0x5c030000 { | |
45 | compatible = "ti,davinci_mdio"; | |
46 | ti,hwmods = "davinci_mdio"; | |
47 | status = "disabled"; | |
48 | reg = <0x5c030000 0x1000>; | |
49 | bus_freq = <1000000>; | |
50 | #address-cells = <1>; | |
51 | #size-cells = <0>; | |
52 | }; | |
53 | ||
54 | uart4: serial@4809e000 { | |
55 | compatible = "ti,omap3-uart"; | |
56 | ti,hwmods = "uart4"; | |
57 | status = "disabled"; | |
58 | reg = <0x4809e000 0x400>; | |
59 | interrupts = <84>; | |
60 | dmas = <&sdma 55 &sdma 54>; | |
61 | dma-names = "tx", "rx"; | |
62 | clock-frequency = <48000000>; | |
63 | }; | |
32ace039 AS |
64 | |
65 | omap3_pmx_core2: pinmux@480025d8 { | |
66 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
67 | reg = <0x480025d8 0x24>; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <0>; | |
be76fd31 | 70 | #pinctrl-cells = <1>; |
32ace039 AS |
71 | #interrupt-cells = <1>; |
72 | interrupt-controller; | |
73 | pinctrl-single,register-width = <16>; | |
74 | pinctrl-single,function-mask = <0xff1f>; | |
75 | }; | |
a5e743c4 YY |
76 | |
77 | hecc: can@5c050000 { | |
78 | compatible = "ti,am3517-hecc"; | |
79 | status = "disabled"; | |
80 | reg = <0x5c050000 0x80>, | |
81 | <0x5c053000 0x180>, | |
82 | <0x5c052000 0x200>; | |
83 | reg-names = "hecc", "hecc-ram", "mbx"; | |
84 | interrupts = <24>; | |
85 | clocks = <&hecc_ck>; | |
86 | }; | |
a0158185 TL |
87 | }; |
88 | }; | |
fdff8a1f | 89 | |
4c051603 SA |
90 | &iva { |
91 | status = "disabled"; | |
92 | }; | |
93 | ||
94 | &mailbox { | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | &mmu_isp { | |
99 | status = "disabled"; | |
100 | }; | |
101 | ||
102 | &smartreflex_mpu_iva { | |
103 | status = "disabled"; | |
104 | }; | |
105 | ||
fdff8a1f TK |
106 | /include/ "am35xx-clocks.dtsi" |
107 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |