[linux-2.6-block.git] / arch / arm / boot / dts / am33xx.dtsi

/*
 * Device Tree Source for AM33XX SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>

/ {
	compatible = "ti,am33xx";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		d-can0 = &dcan0;
		d-can1 = &dcan1;
		usb0 = &usb0;
		usb1 = &usb1;
		phy0 = &usb0_phy;
		phy1 = &usb1_phy;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
		spi0 = &spi0;
		spi1 = &spi1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a8";
			enable-method = "ti,am3352";
			device_type = "cpu";
			reg = <0>;

			operating-points-v2 = <&cpu0_opp_table>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
			cpu-idle-states = <&mpu_gate>;
		};

		idle-states {
			mpu_gate: mpu_gate {
				compatible = "arm,idle-state";
				entry-latency-us = <40>;
				exit-latency-us = <90>;
				min-residency-us = <300>;
				ti,idle-wkup-m3;
			};
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		/*
		 * The three following nodes are marked with opp-suspend
		 * because the can not be enabled simultaneously on a
		 * single SoC.
		 */
		opp50-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <950000 931000 969000>;
			opp-supported-hw = <0x06 0x0010>;
			opp-suspend;
		};

		opp100-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x01 0x00FF>;
			opp-suspend;
		};

		opp100-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x06 0x0020>;
			opp-suspend;
		};

		opp100-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		opp100-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x06 0x0040>;
		};

		opp120-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		opp120-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0x06 0x0080>;
		};

		oppturbo-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		oppturbo-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0x06 0x0100>;
		};

		oppnitro-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1325000 1298500 1351500>;
			opp-supported-hw = <0x04 0x0200>;
		};
	};

	target-module@4b000000 {
		compatible = "ti,sysc-omap4-simple", "ti,sysc";
		clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
		clock-names = "fck";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x4b000000 0x1000000>;

		pmu@0 {
			compatible = "arm,cortex-a8-pmu";
			interrupts = <3>;
			reg = <0 0x1000000>;
			ti,hwmods = "debugss";
		};
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
			pm-sram = <&pm_sram_code
				   &pm_sram_data>;
		};
	};

	/*
	 * XXX: Use a flat representation of the AM33XX interconnect.
	 * The real AM33XX interconnect network is quite complex. Since
	 * it will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp: ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		l4_wkup: interconnect@44c00000 {
		};
		l4_per: interconnect@48000000 {
		};
		l4_fw: interconnect@47c00000 {
		};
		l4_fast: interconnect@4a000000 {
		};
		l4_mpuss: interconnect@4b140000 {
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,am33xx-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x48200000 0x1000>;
		};

		target-module@49000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49000000 0x4>;
			reg-names = "rev";
			clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49000000 0x10000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x10000>;
				reg-names = "edma3_cc";
				interrupts = <12 13 14>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
					   <&edma_tptc2 0>;

				ti,edma-memcpy-channels = <20 21>;
			};
		};

		target-module@49800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49800000 0x4>,
			      <0x49800010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49800000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <112>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49900000 0x4>,
			      <0x49900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49900000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <113>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49a00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49a00000 0x4>,
			      <0x49a00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49a00000 0x100000>;

			edma_tptc2: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <114>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@47810000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x478102fc 0x4>,
			      <0x47810110 0x4>,
			      <0x47810114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47810000 0x1000>;

			mmc3: mmc@0 {
				compatible = "ti,am335-sdhci";
				ti,needs-special-reset;
				interrupts = <29>;
				reg = <0x0 0x1000>;
				status = "disabled";
			};
		};

		usb: target-module@47400000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x47400000 0x4>,
			      <0x47400010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
					 SYSC_OMAP4_SOFTRESET)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47400000 0x8000>;

			usb0_phy: usb-phy@1300 {
				compatible = "ti,am335x-usb-phy";
				reg = <0x1300 0x100>;
				reg-names = "phy";
				ti,ctrl_mod = <&usb_ctrl_mod>;
				#phy-cells = <0>;
			};

			usb0: usb@1400 {
				compatible = "ti,musb-am33xx";
				reg = <0x1400 0x400>,
				      <0x1000 0x200>;
				reg-names = "mc", "control";

				interrupts = <18>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb0_phy>;

				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
					&cppi41dma  2 0 &cppi41dma  3 0
					&cppi41dma  4 0 &cppi41dma  5 0
					&cppi41dma  6 0 &cppi41dma  7 0
					&cppi41dma  8 0 &cppi41dma  9 0
					&cppi41dma 10 0 &cppi41dma 11 0
					&cppi41dma 12 0 &cppi41dma 13 0
					&cppi41dma 14 0 &cppi41dma  0 1
					&cppi41dma  1 1 &cppi41dma  2 1
					&cppi41dma  3 1 &cppi41dma  4 1
					&cppi41dma  5 1 &cppi41dma  6 1
					&cppi41dma  7 1 &cppi41dma  8 1
					&cppi41dma  9 1 &cppi41dma 10 1
					&cppi41dma 11 1 &cppi41dma 12 1
					&cppi41dma 13 1 &cppi41dma 14 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			usb1_phy: usb-phy@1b00 {
				compatible = "ti,am335x-usb-phy";
				reg = <0x1b00 0x100>;
				reg-names = "phy";
				ti,ctrl_mod = <&usb_ctrl_mod>;
				#phy-cells = <0>;
			};

			usb1: usb@1800 {
				compatible = "ti,musb-am33xx";
				reg = <0x1c00 0x400>,
				      <0x1800 0x200>;
				reg-names = "mc", "control";
				interrupts = <19>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb1_phy>;

				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
					&cppi41dma 17 0 &cppi41dma 18 0
					&cppi41dma 19 0 &cppi41dma 20 0
					&cppi41dma 21 0 &cppi41dma 22 0
					&cppi41dma 23 0 &cppi41dma 24 0
					&cppi41dma 25 0 &cppi41dma 26 0
					&cppi41dma 27 0 &cppi41dma 28 0
					&cppi41dma 29 0 &cppi41dma 15 1
					&cppi41dma 16 1 &cppi41dma 17 1
					&cppi41dma 18 1 &cppi41dma 19 1
					&cppi41dma 20 1 &cppi41dma 21 1
					&cppi41dma 22 1 &cppi41dma 23 1
					&cppi41dma 24 1 &cppi41dma 25 1
					&cppi41dma 26 1 &cppi41dma 27 1
					&cppi41dma 28 1 &cppi41dma 29 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			cppi41dma: dma-controller@2000 {
				compatible = "ti,am3359-cppi41";
				reg =  <0x0000 0x1000>,
				       <0x2000 0x1000>,
				       <0x3000 0x1000>,
				       <0x4000 0x4000>;
				reg-names = "glue", "controller", "scheduler", "queuemgr";
				interrupts = <17>;
				interrupt-names = "glue";
				#dma-cells = <2>;
				#dma-channels = <30>;
				#dma-requests = <256>;
			};
		};

		ocmcram: sram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x10000>; /* 64k */
			ranges = <0x0 0x40300000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			pm_sram_code: pm-code-sram@0 {
				compatible = "ti,sram";
				reg = <0x0 0x1000>;
				protect-exec;
			};

			pm_sram_data: pm-data-sram@1000 {
				compatible = "ti,sram";
				reg = <0x1000 0x1000>;
				pool;
			};
		};

		emif: emif@4c000000 {
			compatible = "ti,emif-am3352";
			reg = <0x4c000000 0x1000000>;
			ti,hwmods = "emif";
			interrupts = <101>;
			sram = <&pm_sram_code
				&pm_sram_data>;
			ti,no-idle;
		};

		target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000000 4>,
			      <0x50000010 4>,
			      <0x50000014 4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
				 <0x00000000 0x00000000 0x40000000>; /* data */

			gpmc: gpmc@50000000 {
				compatible = "ti,am3352-gpmc";
				reg = <0x50000000 0x2000>;
				interrupts = <100>;
				dmas = <&edma 52 0>;
				dma-names = "rxtx";
				gpmc,num-cs = <7>;
				gpmc,num-waitpins = <2>;
				#address-cells = <2>;
				#size-cells = <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		sham_target: target-module@53100000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x53100100 0x4>,
			      <0x53100110 0x4>,
			      <0x53100114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53100000 0x1000>;

			sham: sham@0 {
				compatible = "ti,omap4-sham";
				reg = <0 0x200>;
				interrupts = <109>;
				dmas = <&edma 36 0>;
				dma-names = "rx";
			};
		};

		aes_target: target-module@53500000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x53500080 0x4>,
			      <0x53500084 0x4>,
			      <0x53500088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53500000 0x1000>;

			aes: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <103>;
				dmas = <&edma 6 0>,
				       <&edma 5 0>;
				dma-names = "tx", "rx";
			};
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5600fe00 0x4>,
			      <0x5600fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
			clock-names = "fck";
			power-domains = <&prm_gfx>;
			resets = <&prm_gfx 0>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x1000000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};
};

#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"

&prcm {
	prm_per: prm@c00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xc00 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_wkup: prm@d00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xd00 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_mpu: prm@e00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xe00 0x100>;
		#power-domain-cells = <0>;
	};

	prm_device: prm@f00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xf00 0x100>;
		#reset-cells = <1>;
	};

	prm_rtc: prm@1000 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1000 0x100>;
		#power-domain-cells = <0>;
	};

	prm_gfx: prm@1100 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1100 0x100>;
		#power-domain-cells = <0>;
		#reset-cells = <1>;
	};

	prm_cefuse: prm@1200 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1200 0x100>;
		#power-domain-cells = <0>;
	};
};

/* Preferred always-on timer for clocksource */
&timer1_target {
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
		 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
	clock-names = "fck", "ick";
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer1_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
		 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
	clock-names = "fck", "ick";
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer2_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};
Commit	Line	Data
5fc0b42a AC	1	/*
	2	* Device Tree Source for AM33XX SoC
	3	*
75f66813	4	* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5fc0b42a AC	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
87fc89ce	11	#include <dt-bindings/bus/ti-sysc.h>
e94233c2	12	#include <dt-bindings/gpio/gpio.h>
6a8a6b65	13	#include <dt-bindings/pinctrl/am33xx.h>
0537634f	14	#include <dt-bindings/clock/am3.h>
e94233c2	15
5fc0b42a AC	16	/ {
5fc0b42a AC	17	compatible = "ti,am33xx";
4c94ac29	18	interrupt-parent = <&intc>;
f8bf0161 JMC	19	#address-cells = <1>;
f8bf0161 JMC	20	#size-cells = <1>;
1d8d6d3f	21	chosen { };
5fc0b42a AC	22
5fc0b42a AC	23	aliases {
6a968678 NM	24	i2c0 = &i2c0;
	25	i2c1 = &i2c1;
	26	i2c2 = &i2c2;
dde3b0d6 VH	27	serial0 = &uart0;
	28	serial1 = &uart1;
	29	serial2 = &uart2;
	30	serial3 = &uart3;
	31	serial4 = &uart4;
	32	serial5 = &uart5;
19054d0a FB	33	d-can0 = &dcan0;
19054d0a FB	34	d-can1 = &dcan1;
97238b35 SAS	35	usb0 = &usb0;
	36	usb1 = &usb1;
	37	phy0 = &usb0_phy;
	38	phy1 = &usb1_phy;
8170056d DM	39	ethernet0 = &cpsw_emac0;
8170056d DM	40	ethernet1 = &cpsw_emac1;
cddfae25 SM	41	spi0 = &spi0;
cddfae25 SM	42	spi1 = &spi1;
5fc0b42a AC	43	};
	44
	45	cpus {
2e0d513f LP	46	#address-cells = <1>;
2e0d513f LP	47	#size-cells = <0>;
5fc0b42a AC	48	cpu@0 {
5fc0b42a AC	49	compatible = "arm,cortex-a8";
c3e6fcca	50	enable-method = "ti,am3352";
2e0d513f LP	51	device_type = "cpu";
2e0d513f LP	52	reg = <0>;
efeedcf2	53
72ac40fc	54	operating-points-v2 = <&cpu0_opp_table>;
8d766fa2 NM	55
	56	clocks = <&dpll_mpu_ck>;
	57	clock-names = "cpu";
	58
efeedcf2	59	clock-latency = <300000>; /* From omap-cpufreq driver */
c3e6fcca DG	60	cpu-idle-states = <&mpu_gate>;
	61	};
	62
	63	idle-states {
	64	mpu_gate: mpu_gate {
	65	compatible = "arm,idle-state";
	66	entry-latency-us = <40>;
	67	exit-latency-us = <90>;
	68	min-residency-us = <300>;
	69	ti,idle-wkup-m3;
	70	};
5fc0b42a AC	71	};
	72	};
	73
72ac40fc DG	74	cpu0_opp_table: opp-table {
	75	compatible = "operating-points-v2-ti-cpu";
	76	syscon = <&scm_conf>;
	77
	78	/*
	79	* The three following nodes are marked with opp-suspend
	80	* because the can not be enabled simultaneously on a
	81	* single SoC.
	82	*/
b9cb2ba7	83	opp50-300000000 {
72ac40fc DG	84	opp-hz = /bits/ 64 <300000000>;
	85	opp-microvolt = <950000 931000 969000>;
	86	opp-supported-hw = <0x06 0x0010>;
	87	opp-suspend;
	88	};
	89
b9cb2ba7	90	opp100-275000000 {
72ac40fc DG	91	opp-hz = /bits/ 64 <275000000>;
	92	opp-microvolt = <1100000 1078000 1122000>;
	93	opp-supported-hw = <0x01 0x00FF>;
	94	opp-suspend;
	95	};
	96
b9cb2ba7	97	opp100-300000000 {
72ac40fc DG	98	opp-hz = /bits/ 64 <300000000>;
	99	opp-microvolt = <1100000 1078000 1122000>;
	100	opp-supported-hw = <0x06 0x0020>;
	101	opp-suspend;
	102	};
	103
b9cb2ba7	104	opp100-500000000 {
72ac40fc DG	105	opp-hz = /bits/ 64 <500000000>;
	106	opp-microvolt = <1100000 1078000 1122000>;
	107	opp-supported-hw = <0x01 0xFFFF>;
	108	};
	109
b9cb2ba7	110	opp100-600000000 {
72ac40fc DG	111	opp-hz = /bits/ 64 <600000000>;
	112	opp-microvolt = <1100000 1078000 1122000>;
	113	opp-supported-hw = <0x06 0x0040>;
	114	};
	115
b9cb2ba7	116	opp120-600000000 {
72ac40fc DG	117	opp-hz = /bits/ 64 <600000000>;
	118	opp-microvolt = <1200000 1176000 1224000>;
	119	opp-supported-hw = <0x01 0xFFFF>;
	120	};
	121
b9cb2ba7	122	opp120-720000000 {
72ac40fc DG	123	opp-hz = /bits/ 64 <720000000>;
	124	opp-microvolt = <1200000 1176000 1224000>;
	125	opp-supported-hw = <0x06 0x0080>;
	126	};
	127
b9cb2ba7	128	oppturbo-720000000 {
72ac40fc DG	129	opp-hz = /bits/ 64 <720000000>;
	130	opp-microvolt = <1260000 1234800 1285200>;
	131	opp-supported-hw = <0x01 0xFFFF>;
	132	};
	133
b9cb2ba7	134	oppturbo-800000000 {
72ac40fc DG	135	opp-hz = /bits/ 64 <800000000>;
	136	opp-microvolt = <1260000 1234800 1285200>;
	137	opp-supported-hw = <0x06 0x0100>;
	138	};
	139
b9cb2ba7	140	oppnitro-1000000000 {
72ac40fc DG	141	opp-hz = /bits/ 64 <1000000000>;
	142	opp-microvolt = <1325000 1298500 1351500>;
	143	opp-supported-hw = <0x04 0x0200>;
	144	};
	145	};
	146
e990ebae TL	147	target-module@4b000000 {
	148	compatible = "ti,sysc-omap4-simple", "ti,sysc";
	149	clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
	150	clock-names = "fck";
	151	#address-cells = <1>;
	152	#size-cells = <1>;
	153	ranges = <0x0 0x4b000000 0x1000000>;
	154
	155	pmu@0 {
	156	compatible = "arm,cortex-a8-pmu";
	157	interrupts = <3>;
	158	reg = <0 0x1000000>;
	159	ti,hwmods = "debugss";
	160	};
6797cdbe AB	161	};
6797cdbe AB	162
5fc0b42a	163	/*
5c5be9db	164	* The soc node represents the soc top level view. It is used for IPs
5fc0b42a AC	165	* that are not memory mapped in the MPU view or for the MPU itself.
	166	*/
	167	soc {
	168	compatible = "ti,omap-infra";
	169	mpu {
	170	compatible = "ti,omap3-mpu";
	171	ti,hwmods = "mpu";
a77419a2 DG	172	pm-sram = <&pm_sram_code
a77419a2 DG	173	&pm_sram_data>;
5fc0b42a AC	174	};
	175	};
	176
	177	/*
	178	* XXX: Use a flat representation of the AM33XX interconnect.
b7ab524b GU	179	* The real AM33XX interconnect network is quite complex. Since
b7ab524b GU	180	* it will not bring real advantage to represent that in DT
5fc0b42a AC	181	* for the moment, just use a fake OCP bus entry to represent
	182	* the whole bus hierarchy.
	183	*/
03e23ca9	184	ocp: ocp {
5fc0b42a AC	185	compatible = "simple-bus";
	186	#address-cells = <1>;
	187	#size-cells = <1>;
	188	ranges;
	189	ti,hwmods = "l3_main";
	190
87fc89ce	191	l4_wkup: interconnect@44c00000 {
87fc89ce TL	192	};
	193	l4_per: interconnect@48000000 {
	194	};
	195	l4_fw: interconnect@47c00000 {
	196	};
	197	l4_fast: interconnect@4a000000 {
	198	};
	199	l4_mpuss: interconnect@4b140000 {
ea291c98 TK	200	};
ea291c98 TK	201
5fc0b42a	202	intc: interrupt-controller@48200000 {
cab82b76	203	compatible = "ti,am33xx-intc";
5fc0b42a AC	204	interrupt-controller;
5fc0b42a AC	205	#interrupt-cells = <1>;
5fc0b42a AC	206	reg = <0x48200000 0x1000>;
	207	};
	208
ece27503 TL	209	target-module@49000000 {
ece27503 TL	210	compatible = "ti,sysc-omap4", "ti,sysc";
ece27503 TL	211	reg = <0x49000000 0x4>;
	212	reg-names = "rev";
	213	clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
	214	clock-names = "fck";
	215	#address-cells = <1>;
	216	#size-cells = <1>;
	217	ranges = <0x0 0x49000000 0x10000>;
	218
	219	edma: dma@0 {
	220	compatible = "ti,edma3-tpcc";
	221	reg = <0 0x10000>;
	222	reg-names = "edma3_cc";
	223	interrupts = <12 13 14>;
	224	interrupt-names = "edma3_ccint", "edma3_mperr",
	225	"edma3_ccerrint";
	226	dma-requests = <64>;
	227	#dma-cells = <2>;
	228
	229	ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
	230	<&edma_tptc2 0>;
	231
	232	ti,edma-memcpy-channels = <20 21>;
	233	};
b5e50906 PU	234	};
b5e50906 PU	235
9c1562ea TL	236	target-module@49800000 {
9c1562ea TL	237	compatible = "ti,sysc-omap4", "ti,sysc";
9c1562ea TL	238	reg = <0x49800000 0x4>,
	239	<0x49800010 0x4>;
	240	reg-names = "rev", "sysc";
	241	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	242	ti,sysc-midle = <SYSC_IDLE_FORCE>;
	243	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	244	<SYSC_IDLE_SMART>;
	245	clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
	246	clock-names = "fck";
	247	#address-cells = <1>;
	248	#size-cells = <1>;
	249	ranges = <0x0 0x49800000 0x100000>;
	250
	251	edma_tptc0: dma@0 {
	252	compatible = "ti,edma3-tptc";
	253	reg = <0 0x100000>;
	254	interrupts = <112>;
	255	interrupt-names = "edma3_tcerrint";
	256	};
b5e50906 PU	257	};
b5e50906 PU	258
1e666cb3 TL	259	target-module@49900000 {
1e666cb3 TL	260	compatible = "ti,sysc-omap4", "ti,sysc";
1e666cb3 TL	261	reg = <0x49900000 0x4>,
	262	<0x49900010 0x4>;
	263	reg-names = "rev", "sysc";
	264	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	265	ti,sysc-midle = <SYSC_IDLE_FORCE>;
	266	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	267	<SYSC_IDLE_SMART>;
	268	clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
	269	clock-names = "fck";
	270	#address-cells = <1>;
	271	#size-cells = <1>;
	272	ranges = <0x0 0x49900000 0x100000>;
	273
	274	edma_tptc1: dma@0 {
	275	compatible = "ti,edma3-tptc";
	276	reg = <0 0x100000>;
	277	interrupts = <113>;
	278	interrupt-names = "edma3_tcerrint";
	279	};
b5e50906 PU	280	};
b5e50906 PU	281
551e01ad TL	282	target-module@49a00000 {
551e01ad TL	283	compatible = "ti,sysc-omap4", "ti,sysc";
551e01ad TL	284	reg = <0x49a00000 0x4>,
	285	<0x49a00010 0x4>;
	286	reg-names = "rev", "sysc";
	287	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	288	ti,sysc-midle = <SYSC_IDLE_FORCE>;
	289	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	290	<SYSC_IDLE_SMART>;
	291	clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
	292	clock-names = "fck";
	293	#address-cells = <1>;
	294	#size-cells = <1>;
	295	ranges = <0x0 0x49a00000 0x100000>;
	296
	297	edma_tptc2: dma@0 {
	298	compatible = "ti,edma3-tptc";
	299	reg = <0 0x100000>;
	300	interrupts = <114>;
	301	interrupt-names = "edma3_tcerrint";
	302	};
505975d3 MP	303	};
505975d3 MP	304
5b63fb90 TL	305	target-module@47810000 {
5b63fb90 TL	306	compatible = "ti,sysc-omap2", "ti,sysc";
5b63fb90 TL	307	reg = <0x478102fc 0x4>,
	308	<0x47810110 0x4>,
	309	<0x47810114 0x4>;
	310	reg-names = "rev", "sysc", "syss";
	311	ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY \|
	312	SYSC_OMAP2_ENAWAKEUP \|
	313	SYSC_OMAP2_SOFTRESET \|
	314	SYSC_OMAP2_AUTOIDLE)>;
	315	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	316	<SYSC_IDLE_NO>,
	317	<SYSC_IDLE_SMART>;
	318	ti,syss-mask = <1>;
	319	clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
	320	clock-names = "fck";
	321	#address-cells = <1>;
	322	#size-cells = <1>;
	323	ranges = <0x0 0x47810000 0x1000>;
	324
	325	mmc3: mmc@0 {
0b4edf11	326	compatible = "ti,am335-sdhci";
5b63fb90 TL	327	ti,needs-special-reset;
	328	interrupts = <29>;
	329	reg = <0x0 0x1000>;
0b4edf11	330	status = "disabled";
5b63fb90	331	};
55b4452b MP	332	};
55b4452b MP	333
0782e857 TL	334	usb: target-module@47400000 {
	335	compatible = "ti,sysc-omap4", "ti,sysc";
	336	reg = <0x47400000 0x4>,
	337	<0x47400010 0x4>;
	338	reg-names = "rev", "sysc";
	339	ti,sysc-mask = <(SYSC_OMAP4_FREEEMU \|
9f872f92	340	SYSC_OMAP4_SOFTRESET)>;
0782e857 TL	341	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	342	<SYSC_IDLE_NO>,
	343	<SYSC_IDLE_SMART>;
	344	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	345	<SYSC_IDLE_NO>,
	346	<SYSC_IDLE_SMART>,
	347	<SYSC_IDLE_SMART_WKUP>;
	348	clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
	349	clock-names = "fck";
97238b35 SAS	350	#address-cells = <1>;
97238b35 SAS	351	#size-cells = <1>;
3f311e89	352	ranges = <0x0 0x47400000 0x8000>;
97238b35	353
0782e857	354	usb0_phy: usb-phy@1300 {
97238b35	355	compatible = "ti,am335x-usb-phy";
0782e857	356	reg = <0x1300 0x100>;
97238b35	357	reg-names = "phy";
e7243b76	358	ti,ctrl_mod = <&usb_ctrl_mod>;
f0e11ff8	359	#phy-cells = <0>;
97238b35 SAS	360	};
97238b35 SAS	361
0782e857	362	usb0: usb@1400 {
97238b35	363	compatible = "ti,musb-am33xx";
0782e857 TL	364	reg = <0x1400 0x400>,
0782e857 TL	365	<0x1000 0x200>;
c031a7d4 SAS	366	reg-names = "mc", "control";
	367
	368	interrupts = <18>;
	369	interrupt-names = "mc";
	370	dr_mode = "otg";
	371	mentor,multipoint = <1>;
	372	mentor,num-eps = <16>;
	373	mentor,ram-bits = <12>;
	374	mentor,power = <500>;
	375	phys = <&usb0_phy>;
9b3452d1 SAS	376
	377	dmas = <&cppi41dma 0 0 &cppi41dma 1 0
	378	&cppi41dma 2 0 &cppi41dma 3 0
	379	&cppi41dma 4 0 &cppi41dma 5 0
	380	&cppi41dma 6 0 &cppi41dma 7 0
	381	&cppi41dma 8 0 &cppi41dma 9 0
	382	&cppi41dma 10 0 &cppi41dma 11 0
	383	&cppi41dma 12 0 &cppi41dma 13 0
	384	&cppi41dma 14 0 &cppi41dma 0 1
	385	&cppi41dma 1 1 &cppi41dma 2 1
	386	&cppi41dma 3 1 &cppi41dma 4 1
	387	&cppi41dma 5 1 &cppi41dma 6 1
	388	&cppi41dma 7 1 &cppi41dma 8 1
	389	&cppi41dma 9 1 &cppi41dma 10 1
	390	&cppi41dma 11 1 &cppi41dma 12 1
	391	&cppi41dma 13 1 &cppi41dma 14 1>;
	392	dma-names =
	393	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	394	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	395	"rx14", "rx15",
	396	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	397	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	398	"tx14", "tx15";
97238b35 SAS	399	};
97238b35 SAS	400
0782e857	401	usb1_phy: usb-phy@1b00 {
97238b35	402	compatible = "ti,am335x-usb-phy";
0782e857	403	reg = <0x1b00 0x100>;
97238b35	404	reg-names = "phy";
e7243b76	405	ti,ctrl_mod = <&usb_ctrl_mod>;
f0e11ff8	406	#phy-cells = <0>;
97238b35 SAS	407	};
97238b35 SAS	408
0782e857	409	usb1: usb@1800 {
97238b35	410	compatible = "ti,musb-am33xx";
0782e857 TL	411	reg = <0x1c00 0x400>,
0782e857 TL	412	<0x1800 0x200>;
c031a7d4 SAS	413	reg-names = "mc", "control";
	414	interrupts = <19>;
	415	interrupt-names = "mc";
	416	dr_mode = "otg";
	417	mentor,multipoint = <1>;
	418	mentor,num-eps = <16>;
	419	mentor,ram-bits = <12>;
	420	mentor,power = <500>;
	421	phys = <&usb1_phy>;
9b3452d1 SAS	422
	423	dmas = <&cppi41dma 15 0 &cppi41dma 16 0
	424	&cppi41dma 17 0 &cppi41dma 18 0
	425	&cppi41dma 19 0 &cppi41dma 20 0
	426	&cppi41dma 21 0 &cppi41dma 22 0
	427	&cppi41dma 23 0 &cppi41dma 24 0
	428	&cppi41dma 25 0 &cppi41dma 26 0
	429	&cppi41dma 27 0 &cppi41dma 28 0
	430	&cppi41dma 29 0 &cppi41dma 15 1
	431	&cppi41dma 16 1 &cppi41dma 17 1
	432	&cppi41dma 18 1 &cppi41dma 19 1
	433	&cppi41dma 20 1 &cppi41dma 21 1
	434	&cppi41dma 22 1 &cppi41dma 23 1
	435	&cppi41dma 24 1 &cppi41dma 25 1
	436	&cppi41dma 26 1 &cppi41dma 27 1
	437	&cppi41dma 28 1 &cppi41dma 29 1>;
	438	dma-names =
	439	"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
	440	"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
	441	"rx14", "rx15",
	442	"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
	443	"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
	444	"tx14", "tx15";
97238b35	445	};
9b3452d1	446
0782e857	447	cppi41dma: dma-controller@2000 {
9b3452d1	448	compatible = "ti,am3359-cppi41";
0782e857 TL	449	reg = <0x0000 0x1000>,
	450	<0x2000 0x1000>,
	451	<0x3000 0x1000>,
	452	<0x4000 0x4000>;
3b6394b4	453	reg-names = "glue", "controller", "scheduler", "queuemgr";
9b3452d1 SAS	454	interrupts = <17>;
	455	interrupt-names = "glue";
	456	#dma-cells = <2>;
	457	#dma-channels = <30>;
	458	#dma-requests = <256>;
9b3452d1	459	};
35b47fbb	460	};
6be35c70	461
6ba6ed6c	462	ocmcram: sram@40300000 {
8b9a2810 RN	463	compatible = "mmio-sram";
8b9a2810 RN	464	reg = <0x40300000 0x10000>; /* 64k */
31ffe020 DG	465	ranges = <0x0 0x40300000 0x10000>;
	466	#address-cells = <1>;
	467	#size-cells = <1>;
	468
6ba6ed6c	469	pm_sram_code: pm-code-sram@0 {
31ffe020 DG	470	compatible = "ti,sram";
	471	reg = <0x0 0x1000>;
	472	protect-exec;
	473	};
	474
6ba6ed6c	475	pm_sram_data: pm-data-sram@1000 {
31ffe020 DG	476	compatible = "ti,sram";
	477	reg = <0x1000 0x1000>;
	478	pool;
	479	};
f6575c90 VB	480	};
f6575c90 VB	481
cd57dc5a TL	482	emif: emif@4c000000 {
	483	compatible = "ti,emif-am3352";
	484	reg = <0x4c000000 0x1000000>;
	485	ti,hwmods = "emif";
1f5ffc93	486	interrupts = <101>;
b08a966a DG	487	sram = <&pm_sram_code
b08a966a DG	488	&pm_sram_data>;
819cb953	489	ti,no-idle;
cd57dc5a TL	490	};
cd57dc5a TL	491
df7f2f95 TL	492	target-module@50000000 {
	493	compatible = "ti,sysc-omap2", "ti,sysc";
	494	reg = <0x50000000 4>,
	495	<0x50000010 4>,
	496	<0x50000014 4>;
	497	reg-names = "rev", "sysc", "syss";
	498	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	499	<SYSC_IDLE_NO>,
	500	<SYSC_IDLE_SMART>;
	501	ti,syss-mask = <1>;
	502	clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
	503	clock-names = "fck";
	504	#address-cells = <1>;
e45879ec	505	#size-cells = <1>;
df7f2f95 TL	506	ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
	507	<0x00000000 0x00000000 0x40000000>; /* data */
	508
	509	gpmc: gpmc@50000000 {
	510	compatible = "ti,am3352-gpmc";
	511	reg = <0x50000000 0x2000>;
	512	interrupts = <100>;
	513	dmas = <&edma 52 0>;
	514	dma-names = "rxtx";
	515	gpmc,num-cs = <7>;
	516	gpmc,num-waitpins = <2>;
	517	#address-cells = <2>;
	518	#size-cells = <1>;
	519	interrupt-controller;
	520	#interrupt-cells = <2>;
	521	gpio-controller;
	522	#gpio-cells = <2>;
	523	status = "disabled";
	524	};
e45879ec	525	};
f8302e1e	526
e36afc29 TL	527	sham_target: target-module@53100000 {
e36afc29 TL	528	compatible = "ti,sysc-omap3-sham", "ti,sysc";
e36afc29 TL	529	reg = <0x53100100 0x4>,
	530	<0x53100110 0x4>,
	531	<0x53100114 0x4>;
	532	reg-names = "rev", "sysc", "syss";
	533	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	534	SYSC_OMAP2_AUTOIDLE)>;
	535	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	536	<SYSC_IDLE_NO>,
	537	<SYSC_IDLE_SMART>;
	538	ti,syss-mask = <1>;
	539	/* Domains (P, C): per_pwrdm, l3_clkdm */
	540	clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
	541	clock-names = "fck";
	542	#address-cells = <1>;
	543	#size-cells = <1>;
	544	ranges = <0x0 0x53100000 0x1000>;
	545
	546	sham: sham@0 {
	547	compatible = "ti,omap4-sham";
	548	reg = <0 0x200>;
	549	interrupts = <109>;
	550	dmas = <&edma 36 0>;
	551	dma-names = "rx";
	552	};
f8302e1e	553	};
99919e5e	554
b4679c05 TL	555	aes_target: target-module@53500000 {
b4679c05 TL	556	compatible = "ti,sysc-omap2", "ti,sysc";
b4679c05 TL	557	reg = <0x53500080 0x4>,
	558	<0x53500084 0x4>,
	559	<0x53500088 0x4>;
	560	reg-names = "rev", "sysc", "syss";
	561	ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET \|
	562	SYSC_OMAP2_AUTOIDLE)>;
	563	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	564	<SYSC_IDLE_NO>,
	565	<SYSC_IDLE_SMART>,
	566	<SYSC_IDLE_SMART_WKUP>;
	567	ti,syss-mask = <1>;
	568	/* Domains (P, C): per_pwrdm, l3_clkdm */
	569	clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
	570	clock-names = "fck";
	571	#address-cells = <1>;
	572	#size-cells = <1>;
	573	ranges = <0x0 0x53500000 0x1000>;
	574
	575	aes: aes@0 {
	576	compatible = "ti,omap4-aes";
	577	reg = <0 0xa0>;
	578	interrupts = <103>;
	579	dmas = <&edma 6 0>,
	580	<&edma 5 0>;
	581	dma-names = "tx", "rx";
	582	};
99919e5e	583	};
c3fb99f4 TL	584
	585	target-module@56000000 {
	586	compatible = "ti,sysc-omap4", "ti,sysc";
	587	reg = <0x5600fe00 0x4>,
	588	<0x5600fe10 0x4>;
	589	reg-names = "rev", "sysc";
	590	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	591	<SYSC_IDLE_NO>,
	592	<SYSC_IDLE_SMART>;
	593	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	594	<SYSC_IDLE_NO>,
	595	<SYSC_IDLE_SMART>;
	596	clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
	597	clock-names = "fck";
587c437d	598	power-domains = <&prm_gfx>;
c3fb99f4 TL	599	resets = <&prm_gfx 0>;
	600	reset-names = "rstctrl";
	601	#address-cells = <1>;
	602	#size-cells = <1>;
	603	ranges = <0 0x56000000 0x1000000>;
	604
	605	/*
	606	* Closed source PowerVR driver, no child device
	607	* binding or driver in mainline
	608	*/
	609	};
5fc0b42a AC	610	};
5fc0b42a AC	611	};
ea291c98	612
87fc89ce	613	#include "am33xx-l4.dtsi"
0537634f	614	#include "am33xx-clocks.dtsi"
73e64a93 TK	615
	616	&prcm {
	617	prm_per: prm@c00 {
	618	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	619	reg = <0xc00 0x100>;
	620	#reset-cells = <1>;
1041b2d0	621	#power-domain-cells = <0>;
73e64a93 TK	622	};
	623
	624	prm_wkup: prm@d00 {
	625	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	626	reg = <0xd00 0x100>;
	627	#reset-cells = <1>;
1041b2d0 TK	628	#power-domain-cells = <0>;
	629	};
	630
	631	prm_mpu: prm@e00 {
	632	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	633	reg = <0xe00 0x100>;
	634	#power-domain-cells = <0>;
73e64a93 TK	635	};
	636
	637	prm_device: prm@f00 {
	638	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	639	reg = <0xf00 0x100>;
	640	#reset-cells = <1>;
	641	};
	642
1041b2d0 TK	643	prm_rtc: prm@1000 {
	644	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	645	reg = <0x1000 0x100>;
	646	#power-domain-cells = <0>;
	647	};
	648
73e64a93 TK	649	prm_gfx: prm@1100 {
	650	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	651	reg = <0x1100 0x100>;
587c437d	652	#power-domain-cells = <0>;
73e64a93 TK	653	#reset-cells = <1>;
73e64a93 TK	654	};
1041b2d0 TK	655
	656	prm_cefuse: prm@1200 {
	657	compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
	658	reg = <0x1200 0x100>;
	659	#power-domain-cells = <0>;
	660	};
73e64a93	661	};
e20ef23d TL	662
	663	/* Preferred always-on timer for clocksource */
	664	&timer1_target {
b7427dc4 TL	665	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
	666	<&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
	667	clock-names = "fck", "ick";
e20ef23d TL	668	ti,no-reset-on-init;
	669	ti,no-idle;
	670	timer@0 {
	671	assigned-clocks = <&timer1_fck>;
	672	assigned-clock-parents = <&sys_clkin_ck>;
	673	};
	674	};
	675
	676	/* Preferred timer for clockevent */
	677	&timer2_target {
b7427dc4 TL	678	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
	679	<&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
	680	clock-names = "fck", "ick";
e20ef23d TL	681	ti,no-reset-on-init;
	682	ti,no-idle;
	683	timer@0 {
	684	assigned-clocks = <&timer2_fck>;
	685	assigned-clock-parents = <&sys_clkin_ck>;
	686	};
	687	};