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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 TL |
23 | |
24 | #ifdef CONFIG_CPU_V6 | |
25 | .macro loadsp, rb | |
26 | .endm | |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
c633c3cf JCPV |
30 | #elif defined(CONFIG_CPU_XSCALE) |
31 | .macro loadsp, rb | |
32 | .endm | |
33 | .macro writeb, ch, rb | |
34 | mcr p14, 0, \ch, c8, c0, 0 | |
35 | .endm | |
7d95ded9 | 36 | #else |
1da177e4 LT |
37 | .macro loadsp, rb |
38 | .endm | |
224b5be6 | 39 | .macro writeb, ch, rb |
41a9e680 | 40 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 41 | .endm |
7d95ded9 TL |
42 | #endif |
43 | ||
5cd0c344 | 44 | #else |
224b5be6 | 45 | |
a09e64fb | 46 | #include <mach/debug-macro.S> |
224b5be6 | 47 | |
5cd0c344 RK |
48 | .macro writeb, ch, rb |
49 | senduart \ch, \rb | |
1da177e4 | 50 | .endm |
5cd0c344 | 51 | |
224b5be6 | 52 | #if defined(CONFIG_ARCH_SA1100) |
1da177e4 LT |
53 | .macro loadsp, rb |
54 | mov \rb, #0x80000000 @ physical base address | |
224b5be6 | 55 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 56 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 57 | #else |
1da177e4 | 58 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 59 | #endif |
1da177e4 | 60 | .endm |
1da177e4 | 61 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 62 | .macro loadsp, rb |
1da177e4 | 63 | mov \rb, #0x50000000 |
c7657846 | 64 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
1da177e4 | 65 | .endm |
1da177e4 | 66 | #else |
224b5be6 RK |
67 | .macro loadsp, rb |
68 | addruart \rb | |
69 | .endm | |
1da177e4 | 70 | #endif |
5cd0c344 | 71 | #endif |
1da177e4 LT |
72 | #endif |
73 | ||
74 | .macro kputc,val | |
75 | mov r0, \val | |
76 | bl putc | |
77 | .endm | |
78 | ||
79 | .macro kphex,val,len | |
80 | mov r0, \val | |
81 | mov r1, #\len | |
82 | bl phex | |
83 | .endm | |
84 | ||
85 | .macro debug_reloc_start | |
86 | #ifdef DEBUG | |
87 | kputc #'\n' | |
88 | kphex r6, 8 /* processor id */ | |
89 | kputc #':' | |
90 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 91 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
92 | kputc #':' |
93 | mrc p15, 0, r0, c1, c0 | |
94 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 95 | #endif |
1da177e4 LT |
96 | kputc #'\n' |
97 | kphex r5, 8 /* decompressed kernel start */ | |
98 | kputc #'-' | |
f4619025 | 99 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
100 | kputc #'>' |
101 | kphex r4, 8 /* kernel execution address */ | |
102 | kputc #'\n' | |
103 | #endif | |
104 | .endm | |
105 | ||
106 | .macro debug_reloc_end | |
107 | #ifdef DEBUG | |
108 | kphex r5, 8 /* end of kernel */ | |
109 | kputc #'\n' | |
110 | mov r0, r4 | |
111 | bl memdump /* dump 256 bytes at start of kernel */ | |
112 | #endif | |
113 | .endm | |
114 | ||
115 | .section ".start", #alloc, #execinstr | |
116 | /* | |
117 | * sort out different calling conventions | |
118 | */ | |
119 | .align | |
120 | start: | |
121 | .type start,#function | |
122 | .rept 8 | |
123 | mov r0, r0 | |
124 | .endr | |
125 | ||
126 | b 1f | |
127 | .word 0x016f2818 @ Magic numbers to help the loader | |
128 | .word start @ absolute load/run zImage address | |
129 | .word _edata @ zImage end address | |
130 | 1: mov r7, r1 @ save architecture ID | |
f4619025 | 131 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
132 | |
133 | #ifndef __ARM_ARCH_2__ | |
134 | /* | |
135 | * Booting from Angel - need to enter SVC mode and disable | |
136 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
137 | * We only do this if we were in user mode on entry. | |
138 | */ | |
139 | mrs r2, cpsr @ get current mode | |
140 | tst r2, #3 @ not user? | |
141 | bne not_angel | |
142 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
143 | swi 0x123456 @ angel_SWI_ARM | |
144 | not_angel: | |
145 | mrs r2, cpsr @ turn off interrupts to | |
146 | orr r2, r2, #0xc0 @ prevent angel from running | |
147 | msr cpsr_c, r2 | |
148 | #else | |
149 | teqp pc, #0x0c000003 @ turn off interrupts | |
150 | #endif | |
151 | ||
152 | /* | |
153 | * Note that some cache flushing and other stuff may | |
154 | * be needed here - is there an Angel SWI call for this? | |
155 | */ | |
156 | ||
157 | /* | |
158 | * some architecture specific code can be inserted | |
f4619025 | 159 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
160 | */ |
161 | ||
162 | .text | |
163 | adr r0, LC0 | |
164 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
165 | subs r0, r0, r1 @ calculate the delta offset | |
166 | ||
167 | @ if delta is zero, we are | |
168 | beq not_relocated @ running at the address we | |
169 | @ were linked at. | |
170 | ||
171 | /* | |
172 | * We're running at a different address. We need to fix | |
173 | * up various pointers: | |
174 | * r5 - zImage base address | |
175 | * r6 - GOT start | |
176 | * ip - GOT end | |
177 | */ | |
178 | add r5, r5, r0 | |
179 | add r6, r6, r0 | |
180 | add ip, ip, r0 | |
181 | ||
182 | #ifndef CONFIG_ZBOOT_ROM | |
183 | /* | |
184 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
185 | * we need to fix up pointers into the BSS region. | |
186 | * r2 - BSS start | |
187 | * r3 - BSS end | |
188 | * sp - stack pointer | |
189 | */ | |
190 | add r2, r2, r0 | |
191 | add r3, r3, r0 | |
192 | add sp, sp, r0 | |
193 | ||
194 | /* | |
195 | * Relocate all entries in the GOT table. | |
196 | */ | |
197 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
198 | add r1, r1, r0 @ table. This fixes up the | |
199 | str r1, [r6], #4 @ C references. | |
200 | cmp r6, ip | |
201 | blo 1b | |
202 | #else | |
203 | ||
204 | /* | |
205 | * Relocate entries in the GOT table. We only relocate | |
206 | * the entries that are outside the (relocated) BSS region. | |
207 | */ | |
208 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
209 | cmp r1, r2 @ entry < bss_start || | |
210 | cmphs r3, r1 @ _end < entry | |
211 | addlo r1, r1, r0 @ table. This fixes up the | |
212 | str r1, [r6], #4 @ C references. | |
213 | cmp r6, ip | |
214 | blo 1b | |
215 | #endif | |
216 | ||
217 | not_relocated: mov r0, #0 | |
218 | 1: str r0, [r2], #4 @ clear bss | |
219 | str r0, [r2], #4 | |
220 | str r0, [r2], #4 | |
221 | str r0, [r2], #4 | |
222 | cmp r2, r3 | |
223 | blo 1b | |
224 | ||
225 | /* | |
226 | * The C runtime environment should now be setup | |
227 | * sufficiently. Turn the cache on, set up some | |
228 | * pointers, and start decompressing. | |
229 | */ | |
230 | bl cache_on | |
231 | ||
232 | mov r1, sp @ malloc space above stack | |
233 | add r2, sp, #0x10000 @ 64k max | |
234 | ||
235 | /* | |
236 | * Check to see if we will overwrite ourselves. | |
237 | * r4 = final kernel address | |
238 | * r5 = start of this image | |
239 | * r2 = end of malloc space (and therefore this image) | |
240 | * We basically want: | |
241 | * r4 >= r2 -> OK | |
242 | * r4 + image length <= r5 -> OK | |
243 | */ | |
244 | cmp r4, r2 | |
245 | bhs wont_overwrite | |
2552fc27 LB |
246 | sub r3, sp, r5 @ > compressed kernel size |
247 | add r0, r4, r3, lsl #2 @ allow for 4x expansion | |
1da177e4 LT |
248 | cmp r0, r5 |
249 | bls wont_overwrite | |
250 | ||
251 | mov r5, r2 @ decompress after malloc space | |
252 | mov r0, r5 | |
253 | mov r3, r7 | |
254 | bl decompress_kernel | |
255 | ||
c7341d43 | 256 | add r0, r0, #127 + 128 @ alignment + stack |
1da177e4 LT |
257 | bic r0, r0, #127 @ align the kernel length |
258 | /* | |
259 | * r0 = decompressed kernel length | |
260 | * r1-r3 = unused | |
261 | * r4 = kernel execution address | |
262 | * r5 = decompressed kernel start | |
263 | * r6 = processor ID | |
264 | * r7 = architecture ID | |
f4619025 RK |
265 | * r8 = atags pointer |
266 | * r9-r14 = corrupted | |
1da177e4 LT |
267 | */ |
268 | add r1, r5, r0 @ end of decompressed kernel | |
269 | adr r2, reloc_start | |
270 | ldr r3, LC1 | |
271 | add r3, r2, r3 | |
f4619025 RK |
272 | 1: ldmia r2!, {r9 - r14} @ copy relocation code |
273 | stmia r1!, {r9 - r14} | |
274 | ldmia r2!, {r9 - r14} | |
275 | stmia r1!, {r9 - r14} | |
1da177e4 LT |
276 | cmp r2, r3 |
277 | blo 1b | |
c7341d43 | 278 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
279 | |
280 | bl cache_clean_flush | |
281 | add pc, r5, r0 @ call relocation code | |
282 | ||
283 | /* | |
284 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
285 | * | |
286 | * r4 = kernel execution address | |
287 | * r7 = architecture ID | |
288 | */ | |
289 | wont_overwrite: mov r0, r4 | |
290 | mov r3, r7 | |
291 | bl decompress_kernel | |
292 | b call_kernel | |
293 | ||
294 | .type LC0, #object | |
295 | LC0: .word LC0 @ r1 | |
296 | .word __bss_start @ r2 | |
297 | .word _end @ r3 | |
298 | .word zreladdr @ r4 | |
299 | .word _start @ r5 | |
300 | .word _got_start @ r6 | |
301 | .word _got_end @ ip | |
302 | .word user_stack+4096 @ sp | |
303 | LC1: .word reloc_end - reloc_start | |
304 | .size LC0, . - LC0 | |
305 | ||
306 | #ifdef CONFIG_ARCH_RPC | |
307 | .globl params | |
308 | params: ldr r0, =params_phys | |
309 | mov pc, lr | |
310 | .ltorg | |
311 | .align | |
312 | #endif | |
313 | ||
314 | /* | |
315 | * Turn on the cache. We need to setup some page tables so that we | |
316 | * can have both the I and D caches on. | |
317 | * | |
318 | * We place the page tables 16k down from the kernel execution address, | |
319 | * and we hope that nothing else is using it. If we're using it, we | |
320 | * will go pop! | |
321 | * | |
322 | * On entry, | |
323 | * r4 = kernel execution address | |
324 | * r6 = processor ID | |
325 | * r7 = architecture number | |
f4619025 RK |
326 | * r8 = atags pointer |
327 | * r9 = run-time address of "start" (???) | |
1da177e4 | 328 | * On exit, |
f4619025 | 329 | * r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 330 | * This routine must preserve: |
f4619025 | 331 | * r4, r5, r6, r7, r8 |
1da177e4 LT |
332 | */ |
333 | .align 5 | |
334 | cache_on: mov r3, #8 @ cache_on function | |
335 | b call_cache_fn | |
336 | ||
10c2df65 HC |
337 | /* |
338 | * Initialize the highest priority protection region, PR7 | |
339 | * to cover all 32bit address and cacheable and bufferable. | |
340 | */ | |
341 | __armv4_mpu_cache_on: | |
342 | mov r0, #0x3f @ 4G, the whole | |
343 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
344 | mcr p15, 0, r0, c6, c7, 1 | |
345 | ||
346 | mov r0, #0x80 @ PR7 | |
347 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
348 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
349 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
350 | ||
351 | mov r0, #0xc000 | |
352 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
353 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
354 | ||
355 | mov r0, #0 | |
356 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
357 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
358 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
359 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
360 | @ ...I .... ..D. WC.M | |
361 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
362 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
363 | ||
364 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
365 | ||
366 | mov r0, #0 | |
367 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
368 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
369 | mov pc, lr | |
370 | ||
371 | __armv3_mpu_cache_on: | |
372 | mov r0, #0x3f @ 4G, the whole | |
373 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
374 | ||
375 | mov r0, #0x80 @ PR7 | |
376 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
377 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
378 | ||
379 | mov r0, #0xc000 | |
380 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
381 | ||
382 | mov r0, #0 | |
383 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
384 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
385 | @ .... .... .... WC.M | |
386 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
387 | mov r0, #0 | |
388 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
389 | ||
390 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
391 | mov pc, lr | |
392 | ||
1da177e4 LT |
393 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
394 | bic r3, r3, #0xff @ Align the pointer | |
395 | bic r3, r3, #0x3f00 | |
396 | /* | |
397 | * Initialise the page tables, turning on the cacheable and bufferable | |
398 | * bits for the RAM area only. | |
399 | */ | |
400 | mov r0, r3 | |
f4619025 RK |
401 | mov r9, r0, lsr #18 |
402 | mov r9, r9, lsl #18 @ start of RAM | |
403 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
404 | mov r1, #0x12 |
405 | orr r1, r1, #3 << 10 | |
406 | add r2, r3, #16384 | |
265d5e48 | 407 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 408 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 409 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
410 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
411 | str r1, [r0], #4 @ 1:1 mapping | |
412 | add r1, r1, #1048576 | |
413 | teq r0, r2 | |
414 | bne 1b | |
415 | /* | |
416 | * If ever we are running from Flash, then we surely want the cache | |
417 | * to be enabled also for our execution instance... We map 2MB of it | |
418 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
419 | * If the execution is in RAM then we would only be duplicating the above. | |
420 | */ | |
421 | mov r1, #0x1e | |
422 | orr r1, r1, #3 << 10 | |
423 | mov r2, pc, lsr #20 | |
424 | orr r1, r1, r2, lsl #20 | |
425 | add r0, r3, r2, lsl #2 | |
426 | str r1, [r0], #4 | |
427 | add r1, r1, #1048576 | |
428 | str r1, [r0] | |
429 | mov pc, lr | |
93ed3970 | 430 | ENDPROC(__setup_mmu) |
1da177e4 | 431 | |
c76b6b41 | 432 | __armv4_mmu_cache_on: |
1da177e4 LT |
433 | mov r12, lr |
434 | bl __setup_mmu | |
435 | mov r0, #0 | |
436 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
437 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
438 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
439 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
440 | orr r0, r0, #0x0030 | |
c76b6b41 | 441 | bl __common_mmu_cache_on |
1da177e4 LT |
442 | mov r0, #0 |
443 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
444 | mov pc, r12 | |
445 | ||
7d09e854 CM |
446 | __armv7_mmu_cache_on: |
447 | mov r12, lr | |
448 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 | |
449 | tst r11, #0xf @ VMSA | |
450 | blne __setup_mmu | |
451 | mov r0, #0 | |
452 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
453 | tst r11, #0xf @ VMSA | |
454 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
455 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
456 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
457 | orr r0, r0, #0x003c @ write buffer | |
458 | orrne r0, r0, #1 @ MMU enabled | |
459 | movne r1, #-1 | |
460 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | |
461 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
462 | mcr p15, 0, r0, c1, c0, 0 @ load control register | |
463 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
464 | mov r0, #0 | |
465 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
466 | mov pc, r12 | |
467 | ||
c76b6b41 | 468 | __arm6_mmu_cache_on: |
1da177e4 LT |
469 | mov r12, lr |
470 | bl __setup_mmu | |
471 | mov r0, #0 | |
472 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
473 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
474 | mov r0, #0x30 | |
c76b6b41 | 475 | bl __common_mmu_cache_on |
1da177e4 LT |
476 | mov r0, #0 |
477 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
478 | mov pc, r12 | |
479 | ||
c76b6b41 | 480 | __common_mmu_cache_on: |
1da177e4 LT |
481 | #ifndef DEBUG |
482 | orr r0, r0, #0x000d @ Write buffer, mmu | |
483 | #endif | |
484 | mov r1, #-1 | |
485 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
486 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
487 | b 1f |
488 | .align 5 @ cache line aligned | |
489 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
490 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
491 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
1da177e4 LT |
492 | |
493 | /* | |
494 | * All code following this line is relocatable. It is relocated by | |
495 | * the above code to the end of the decompressed kernel image and | |
496 | * executed there. During this time, we have no stacks. | |
497 | * | |
498 | * r0 = decompressed kernel length | |
499 | * r1-r3 = unused | |
500 | * r4 = kernel execution address | |
501 | * r5 = decompressed kernel start | |
502 | * r6 = processor ID | |
503 | * r7 = architecture ID | |
f4619025 RK |
504 | * r8 = atags pointer |
505 | * r9-r14 = corrupted | |
1da177e4 LT |
506 | */ |
507 | .align 5 | |
f4619025 | 508 | reloc_start: add r9, r5, r0 |
c7341d43 | 509 | sub r9, r9, #128 @ do not copy the stack |
1da177e4 LT |
510 | debug_reloc_start |
511 | mov r1, r4 | |
512 | 1: | |
513 | .rept 4 | |
f4619025 RK |
514 | ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel |
515 | stmia r1!, {r0, r2, r3, r10 - r14} | |
1da177e4 LT |
516 | .endr |
517 | ||
f4619025 | 518 | cmp r5, r9 |
1da177e4 | 519 | blo 1b |
c7341d43 | 520 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
521 | debug_reloc_end |
522 | ||
523 | call_kernel: bl cache_clean_flush | |
524 | bl cache_off | |
f4619025 | 525 | mov r0, #0 @ must be zero |
1da177e4 | 526 | mov r1, r7 @ restore architecture number |
f4619025 | 527 | mov r2, r8 @ restore atags pointer |
1da177e4 LT |
528 | mov pc, r4 @ call kernel |
529 | ||
530 | /* | |
531 | * Here follow the relocatable cache support functions for the | |
532 | * various processors. This is a generic hook for locating an | |
533 | * entry and jumping to an instruction at the specified offset | |
534 | * from the start of the block. Please note this is all position | |
535 | * independent code. | |
536 | * | |
537 | * r1 = corrupted | |
538 | * r2 = corrupted | |
539 | * r3 = block offset | |
540 | * r6 = corrupted | |
541 | * r12 = corrupted | |
542 | */ | |
543 | ||
544 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 545 | #ifdef CONFIG_CPU_CP15 |
1da177e4 | 546 | mrc p15, 0, r6, c0, c0 @ get processor ID |
f12d0d7c HC |
547 | #else |
548 | ldr r6, =CONFIG_PROCESSOR_ID | |
549 | #endif | |
1da177e4 LT |
550 | 1: ldr r1, [r12, #0] @ get value |
551 | ldr r2, [r12, #4] @ get mask | |
552 | eor r1, r1, r6 @ (real ^ match) | |
553 | tst r1, r2 @ & mask | |
554 | addeq pc, r12, r3 @ call cache function | |
555 | add r12, r12, #4*5 | |
556 | b 1b | |
557 | ||
558 | /* | |
559 | * Table for cache operations. This is basically: | |
560 | * - CPU ID match | |
561 | * - CPU ID mask | |
562 | * - 'cache on' method instruction | |
563 | * - 'cache off' method instruction | |
564 | * - 'cache flush' method instruction | |
565 | * | |
566 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
567 | * | |
568 | * Writethrough caches generally only need 'on' and 'off' | |
569 | * methods. Writeback caches _must_ have the flush method | |
570 | * defined. | |
571 | */ | |
572 | .type proc_types,#object | |
573 | proc_types: | |
574 | .word 0x41560600 @ ARM6/610 | |
575 | .word 0xffffffe0 | |
c76b6b41 HC |
576 | b __arm6_mmu_cache_off @ works, but slow |
577 | b __arm6_mmu_cache_off | |
1da177e4 | 578 | mov pc, lr |
c76b6b41 HC |
579 | @ b __arm6_mmu_cache_on @ untested |
580 | @ b __arm6_mmu_cache_off | |
581 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
582 | |
583 | .word 0x00000000 @ old ARM ID | |
584 | .word 0x0000f000 | |
585 | mov pc, lr | |
586 | mov pc, lr | |
587 | mov pc, lr | |
588 | ||
589 | .word 0x41007000 @ ARM7/710 | |
590 | .word 0xfff8fe00 | |
c76b6b41 HC |
591 | b __arm7_mmu_cache_off |
592 | b __arm7_mmu_cache_off | |
1da177e4 LT |
593 | mov pc, lr |
594 | ||
595 | .word 0x41807200 @ ARM720T (writethrough) | |
596 | .word 0xffffff00 | |
c76b6b41 HC |
597 | b __armv4_mmu_cache_on |
598 | b __armv4_mmu_cache_off | |
1da177e4 LT |
599 | mov pc, lr |
600 | ||
10c2df65 HC |
601 | .word 0x41007400 @ ARM74x |
602 | .word 0xff00ff00 | |
603 | b __armv3_mpu_cache_on | |
604 | b __armv3_mpu_cache_off | |
605 | b __armv3_mpu_cache_flush | |
606 | ||
607 | .word 0x41009400 @ ARM94x | |
608 | .word 0xff00ff00 | |
609 | b __armv4_mpu_cache_on | |
610 | b __armv4_mpu_cache_off | |
611 | b __armv4_mpu_cache_flush | |
612 | ||
1da177e4 LT |
613 | .word 0x00007000 @ ARM7 IDs |
614 | .word 0x0000f000 | |
615 | mov pc, lr | |
616 | mov pc, lr | |
617 | mov pc, lr | |
618 | ||
619 | @ Everything from here on will be the new ID system. | |
620 | ||
621 | .word 0x4401a100 @ sa110 / sa1100 | |
622 | .word 0xffffffe0 | |
c76b6b41 HC |
623 | b __armv4_mmu_cache_on |
624 | b __armv4_mmu_cache_off | |
625 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
626 | |
627 | .word 0x6901b110 @ sa1110 | |
628 | .word 0xfffffff0 | |
c76b6b41 HC |
629 | b __armv4_mmu_cache_on |
630 | b __armv4_mmu_cache_off | |
631 | b __armv4_mmu_cache_flush | |
1da177e4 | 632 | |
59c7bcd4 EM |
633 | .word 0x56056930 |
634 | .word 0xff0ffff0 @ PXA935 | |
635 | b __armv4_mmu_cache_on | |
c76b6b41 HC |
636 | b __armv4_mmu_cache_off |
637 | b __armv4_mmu_cache_flush | |
1da177e4 | 638 | |
2e2023fe NP |
639 | .word 0x56050000 @ Feroceon |
640 | .word 0xff0f0000 | |
3ebb5a2b NP |
641 | b __armv4_mmu_cache_on |
642 | b __armv4_mmu_cache_off | |
643 | b __armv5tej_mmu_cache_flush | |
644 | ||
1da177e4 LT |
645 | @ These match on the architecture ID |
646 | ||
647 | .word 0x00020000 @ ARMv4T | |
648 | .word 0x000f0000 | |
c76b6b41 HC |
649 | b __armv4_mmu_cache_on |
650 | b __armv4_mmu_cache_off | |
651 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
652 | |
653 | .word 0x00050000 @ ARMv5TE | |
654 | .word 0x000f0000 | |
c76b6b41 HC |
655 | b __armv4_mmu_cache_on |
656 | b __armv4_mmu_cache_off | |
657 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
658 | |
659 | .word 0x00060000 @ ARMv5TEJ | |
660 | .word 0x000f0000 | |
c76b6b41 HC |
661 | b __armv4_mmu_cache_on |
662 | b __armv4_mmu_cache_off | |
15754bf9 | 663 | b __armv5tej_mmu_cache_flush |
1da177e4 | 664 | |
45a7b9cf | 665 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 666 | .word 0x000ff000 |
c76b6b41 HC |
667 | b __armv4_mmu_cache_on |
668 | b __armv4_mmu_cache_off | |
669 | b __armv6_mmu_cache_flush | |
1da177e4 | 670 | |
7d09e854 CM |
671 | .word 0x000f0000 @ new CPU Id |
672 | .word 0x000f0000 | |
673 | b __armv7_mmu_cache_on | |
674 | b __armv7_mmu_cache_off | |
675 | b __armv7_mmu_cache_flush | |
676 | ||
1da177e4 LT |
677 | .word 0 @ unrecognised type |
678 | .word 0 | |
679 | mov pc, lr | |
680 | mov pc, lr | |
681 | mov pc, lr | |
682 | ||
683 | .size proc_types, . - proc_types | |
684 | ||
685 | /* | |
686 | * Turn off the Cache and MMU. ARMv3 does not support | |
687 | * reading the control register, but ARMv4 does. | |
688 | * | |
689 | * On entry, r6 = processor ID | |
690 | * On exit, r0, r1, r2, r3, r12 corrupted | |
691 | * This routine must preserve: r4, r6, r7 | |
692 | */ | |
693 | .align 5 | |
694 | cache_off: mov r3, #12 @ cache_off function | |
695 | b call_cache_fn | |
696 | ||
10c2df65 HC |
697 | __armv4_mpu_cache_off: |
698 | mrc p15, 0, r0, c1, c0 | |
699 | bic r0, r0, #0x000d | |
700 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
701 | mov r0, #0 | |
702 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
703 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
704 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
705 | mov pc, lr | |
706 | ||
707 | __armv3_mpu_cache_off: | |
708 | mrc p15, 0, r0, c1, c0 | |
709 | bic r0, r0, #0x000d | |
710 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
711 | mov r0, #0 | |
712 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
713 | mov pc, lr | |
714 | ||
c76b6b41 | 715 | __armv4_mmu_cache_off: |
1da177e4 LT |
716 | mrc p15, 0, r0, c1, c0 |
717 | bic r0, r0, #0x000d | |
718 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
719 | mov r0, #0 | |
720 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
721 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
722 | mov pc, lr | |
723 | ||
7d09e854 CM |
724 | __armv7_mmu_cache_off: |
725 | mrc p15, 0, r0, c1, c0 | |
726 | bic r0, r0, #0x000d | |
727 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
728 | mov r12, lr | |
729 | bl __armv7_mmu_cache_flush | |
730 | mov r0, #0 | |
731 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB | |
c30c2f99 CM |
732 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
733 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
734 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
7d09e854 CM |
735 | mov pc, r12 |
736 | ||
c76b6b41 | 737 | __arm6_mmu_cache_off: |
1da177e4 | 738 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 739 | b __armv3_mmu_cache_off |
1da177e4 | 740 | |
c76b6b41 | 741 | __arm7_mmu_cache_off: |
1da177e4 | 742 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 743 | b __armv3_mmu_cache_off |
1da177e4 | 744 | |
c76b6b41 | 745 | __armv3_mmu_cache_off: |
1da177e4 LT |
746 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
747 | mov r0, #0 | |
748 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
749 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
750 | mov pc, lr | |
751 | ||
752 | /* | |
753 | * Clean and flush the cache to maintain consistency. | |
754 | * | |
755 | * On entry, | |
756 | * r6 = processor ID | |
757 | * On exit, | |
758 | * r1, r2, r3, r11, r12 corrupted | |
759 | * This routine must preserve: | |
760 | * r0, r4, r5, r6, r7 | |
761 | */ | |
762 | .align 5 | |
763 | cache_clean_flush: | |
764 | mov r3, #16 | |
765 | b call_cache_fn | |
766 | ||
10c2df65 HC |
767 | __armv4_mpu_cache_flush: |
768 | mov r2, #1 | |
769 | mov r3, #0 | |
770 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
771 | mov r1, #7 << 5 @ 8 segments | |
772 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
773 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
774 | subs r3, r3, #1 << 26 | |
775 | bcs 2b @ entries 63 to 0 | |
776 | subs r1, r1, #1 << 5 | |
777 | bcs 1b @ segments 7 to 0 | |
778 | ||
779 | teq r2, #0 | |
780 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
781 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
782 | mov pc, lr | |
783 | ||
784 | ||
c76b6b41 | 785 | __armv6_mmu_cache_flush: |
1da177e4 LT |
786 | mov r1, #0 |
787 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
788 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
789 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
790 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
791 | mov pc, lr | |
792 | ||
7d09e854 CM |
793 | __armv7_mmu_cache_flush: |
794 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
795 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
7d09e854 | 796 | mov r10, #0 |
c30c2f99 | 797 | beq hierarchical |
7d09e854 CM |
798 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
799 | b iflush | |
800 | hierarchical: | |
c30c2f99 CM |
801 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
802 | stmfd sp!, {r0-r5, r7, r9, r11} | |
7d09e854 CM |
803 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
804 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
805 | mov r3, r3, lsr #23 @ left align loc bit field | |
806 | beq finished @ if loc is 0, then no need to clean | |
807 | mov r10, #0 @ start clean at cache level 0 | |
808 | loop1: | |
809 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
810 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
811 | and r1, r1, #7 @ mask of the bits for current cache only | |
812 | cmp r1, #2 @ see what cache we have at this level | |
813 | blt skip @ skip if no cache, or just i-cache | |
814 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
815 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
816 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
817 | and r2, r1, #7 @ extract the length of the cache lines | |
818 | add r2, r2, #4 @ add 4 (line length offset) | |
819 | ldr r4, =0x3ff | |
820 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
000b5025 | 821 | clz r5, r4 @ find bit position of way size increment |
7d09e854 CM |
822 | ldr r7, =0x7fff |
823 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
824 | loop2: | |
825 | mov r9, r4 @ create working copy of max way size | |
826 | loop3: | |
827 | orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 | |
828 | orr r11, r11, r7, lsl r2 @ factor index number into r11 | |
829 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way | |
830 | subs r9, r9, #1 @ decrement the way | |
831 | bge loop3 | |
832 | subs r7, r7, #1 @ decrement the index | |
833 | bge loop2 | |
834 | skip: | |
835 | add r10, r10, #2 @ increment cache number | |
836 | cmp r3, r10 | |
837 | bgt loop1 | |
838 | finished: | |
c30c2f99 | 839 | ldmfd sp!, {r0-r5, r7, r9, r11} |
7d09e854 CM |
840 | mov r10, #0 @ swith back to cache level 0 |
841 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
7d09e854 | 842 | iflush: |
c30c2f99 | 843 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
7d09e854 | 844 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
c30c2f99 CM |
845 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
846 | mcr p15, 0, r10, c7, c5, 4 @ ISB | |
7d09e854 CM |
847 | mov pc, lr |
848 | ||
15754bf9 NP |
849 | __armv5tej_mmu_cache_flush: |
850 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache | |
851 | bne 1b | |
852 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache | |
853 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
854 | mov pc, lr | |
855 | ||
c76b6b41 | 856 | __armv4_mmu_cache_flush: |
1da177e4 LT |
857 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
858 | mov r11, #32 @ default: 32 byte line size | |
859 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
860 | teq r3, r6 @ cache ID register present? | |
861 | beq no_cache_id | |
862 | mov r1, r3, lsr #18 | |
863 | and r1, r1, #7 | |
864 | mov r2, #1024 | |
865 | mov r2, r2, lsl r1 @ base dcache size *2 | |
866 | tst r3, #1 << 14 @ test M bit | |
867 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
868 | mov r3, r3, lsr #12 | |
869 | and r3, r3, #3 | |
870 | mov r11, #8 | |
871 | mov r11, r11, lsl r3 @ cache line size in bytes | |
872 | no_cache_id: | |
873 | bic r1, pc, #63 @ align to longest cache line | |
874 | add r2, r1, r2 | |
875 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
876 | teq r1, r2 | |
877 | bne 1b | |
878 | ||
879 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
880 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
881 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
882 | mov pc, lr | |
883 | ||
c76b6b41 | 884 | __armv3_mmu_cache_flush: |
10c2df65 | 885 | __armv3_mpu_cache_flush: |
1da177e4 LT |
886 | mov r1, #0 |
887 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
888 | mov pc, lr | |
889 | ||
890 | /* | |
891 | * Various debugging routines for printing hex characters and | |
892 | * memory, which again must be relocatable. | |
893 | */ | |
894 | #ifdef DEBUG | |
895 | .type phexbuf,#object | |
896 | phexbuf: .space 12 | |
897 | .size phexbuf, . - phexbuf | |
898 | ||
899 | phex: adr r3, phexbuf | |
900 | mov r2, #0 | |
901 | strb r2, [r3, r1] | |
902 | 1: subs r1, r1, #1 | |
903 | movmi r0, r3 | |
904 | bmi puts | |
905 | and r2, r0, #15 | |
906 | mov r0, r0, lsr #4 | |
907 | cmp r2, #10 | |
908 | addge r2, r2, #7 | |
909 | add r2, r2, #'0' | |
910 | strb r2, [r3, r1] | |
911 | b 1b | |
912 | ||
913 | puts: loadsp r3 | |
914 | 1: ldrb r2, [r0], #1 | |
915 | teq r2, #0 | |
916 | moveq pc, lr | |
5cd0c344 | 917 | 2: writeb r2, r3 |
1da177e4 LT |
918 | mov r1, #0x00020000 |
919 | 3: subs r1, r1, #1 | |
920 | bne 3b | |
921 | teq r2, #'\n' | |
922 | moveq r2, #'\r' | |
923 | beq 2b | |
924 | teq r0, #0 | |
925 | bne 1b | |
926 | mov pc, lr | |
927 | putc: | |
928 | mov r2, r0 | |
929 | mov r0, #0 | |
930 | loadsp r3 | |
931 | b 2b | |
932 | ||
933 | memdump: mov r12, r0 | |
934 | mov r10, lr | |
935 | mov r11, #0 | |
936 | 2: mov r0, r11, lsl #2 | |
937 | add r0, r0, r12 | |
938 | mov r1, #8 | |
939 | bl phex | |
940 | mov r0, #':' | |
941 | bl putc | |
942 | 1: mov r0, #' ' | |
943 | bl putc | |
944 | ldr r0, [r12, r11, lsl #2] | |
945 | mov r1, #8 | |
946 | bl phex | |
947 | and r0, r11, #7 | |
948 | teq r0, #3 | |
949 | moveq r0, #' ' | |
950 | bleq putc | |
951 | and r0, r11, #7 | |
952 | add r11, r11, #1 | |
953 | teq r0, #7 | |
954 | bne 1b | |
955 | mov r0, #'\n' | |
956 | bl putc | |
957 | cmp r11, #64 | |
958 | blt 2b | |
959 | mov pc, r10 | |
960 | #endif | |
961 | ||
92c83ff1 | 962 | .ltorg |
1da177e4 LT |
963 | reloc_end: |
964 | ||
965 | .align | |
966 | .section ".stack", "w" | |
967 | user_stack: .space 4096 |