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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 TL |
23 | |
24 | #ifdef CONFIG_CPU_V6 | |
25 | .macro loadsp, rb | |
26 | .endm | |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
30 | #else | |
1da177e4 LT |
31 | .macro loadsp, rb |
32 | .endm | |
224b5be6 | 33 | .macro writeb, ch, rb |
41a9e680 | 34 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 35 | .endm |
7d95ded9 TL |
36 | #endif |
37 | ||
5cd0c344 | 38 | #else |
224b5be6 RK |
39 | |
40 | #include <asm/arch/debug-macro.S> | |
41 | ||
5cd0c344 RK |
42 | .macro writeb, ch, rb |
43 | senduart \ch, \rb | |
1da177e4 | 44 | .endm |
5cd0c344 | 45 | |
224b5be6 | 46 | #if defined(CONFIG_ARCH_SA1100) |
1da177e4 LT |
47 | .macro loadsp, rb |
48 | mov \rb, #0x80000000 @ physical base address | |
224b5be6 | 49 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 50 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 51 | #else |
1da177e4 | 52 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 53 | #endif |
1da177e4 | 54 | .endm |
1da177e4 | 55 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 56 | .macro loadsp, rb |
1da177e4 | 57 | mov \rb, #0x50000000 |
c7657846 | 58 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
1da177e4 | 59 | .endm |
1da177e4 | 60 | #else |
224b5be6 RK |
61 | .macro loadsp, rb |
62 | addruart \rb | |
63 | .endm | |
1da177e4 | 64 | #endif |
5cd0c344 | 65 | #endif |
1da177e4 LT |
66 | #endif |
67 | ||
68 | .macro kputc,val | |
69 | mov r0, \val | |
70 | bl putc | |
71 | .endm | |
72 | ||
73 | .macro kphex,val,len | |
74 | mov r0, \val | |
75 | mov r1, #\len | |
76 | bl phex | |
77 | .endm | |
78 | ||
79 | .macro debug_reloc_start | |
80 | #ifdef DEBUG | |
81 | kputc #'\n' | |
82 | kphex r6, 8 /* processor id */ | |
83 | kputc #':' | |
84 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 85 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
86 | kputc #':' |
87 | mrc p15, 0, r0, c1, c0 | |
88 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 89 | #endif |
1da177e4 LT |
90 | kputc #'\n' |
91 | kphex r5, 8 /* decompressed kernel start */ | |
92 | kputc #'-' | |
f4619025 | 93 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
94 | kputc #'>' |
95 | kphex r4, 8 /* kernel execution address */ | |
96 | kputc #'\n' | |
97 | #endif | |
98 | .endm | |
99 | ||
100 | .macro debug_reloc_end | |
101 | #ifdef DEBUG | |
102 | kphex r5, 8 /* end of kernel */ | |
103 | kputc #'\n' | |
104 | mov r0, r4 | |
105 | bl memdump /* dump 256 bytes at start of kernel */ | |
106 | #endif | |
107 | .endm | |
108 | ||
109 | .section ".start", #alloc, #execinstr | |
110 | /* | |
111 | * sort out different calling conventions | |
112 | */ | |
113 | .align | |
114 | start: | |
115 | .type start,#function | |
116 | .rept 8 | |
117 | mov r0, r0 | |
118 | .endr | |
119 | ||
120 | b 1f | |
121 | .word 0x016f2818 @ Magic numbers to help the loader | |
122 | .word start @ absolute load/run zImage address | |
123 | .word _edata @ zImage end address | |
124 | 1: mov r7, r1 @ save architecture ID | |
f4619025 | 125 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
126 | |
127 | #ifndef __ARM_ARCH_2__ | |
128 | /* | |
129 | * Booting from Angel - need to enter SVC mode and disable | |
130 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
131 | * We only do this if we were in user mode on entry. | |
132 | */ | |
133 | mrs r2, cpsr @ get current mode | |
134 | tst r2, #3 @ not user? | |
135 | bne not_angel | |
136 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
137 | swi 0x123456 @ angel_SWI_ARM | |
138 | not_angel: | |
139 | mrs r2, cpsr @ turn off interrupts to | |
140 | orr r2, r2, #0xc0 @ prevent angel from running | |
141 | msr cpsr_c, r2 | |
142 | #else | |
143 | teqp pc, #0x0c000003 @ turn off interrupts | |
144 | #endif | |
145 | ||
146 | /* | |
147 | * Note that some cache flushing and other stuff may | |
148 | * be needed here - is there an Angel SWI call for this? | |
149 | */ | |
150 | ||
151 | /* | |
152 | * some architecture specific code can be inserted | |
f4619025 | 153 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
154 | */ |
155 | ||
156 | .text | |
157 | adr r0, LC0 | |
158 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
159 | subs r0, r0, r1 @ calculate the delta offset | |
160 | ||
161 | @ if delta is zero, we are | |
162 | beq not_relocated @ running at the address we | |
163 | @ were linked at. | |
164 | ||
165 | /* | |
166 | * We're running at a different address. We need to fix | |
167 | * up various pointers: | |
168 | * r5 - zImage base address | |
169 | * r6 - GOT start | |
170 | * ip - GOT end | |
171 | */ | |
172 | add r5, r5, r0 | |
173 | add r6, r6, r0 | |
174 | add ip, ip, r0 | |
175 | ||
176 | #ifndef CONFIG_ZBOOT_ROM | |
177 | /* | |
178 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
179 | * we need to fix up pointers into the BSS region. | |
180 | * r2 - BSS start | |
181 | * r3 - BSS end | |
182 | * sp - stack pointer | |
183 | */ | |
184 | add r2, r2, r0 | |
185 | add r3, r3, r0 | |
186 | add sp, sp, r0 | |
187 | ||
188 | /* | |
189 | * Relocate all entries in the GOT table. | |
190 | */ | |
191 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
192 | add r1, r1, r0 @ table. This fixes up the | |
193 | str r1, [r6], #4 @ C references. | |
194 | cmp r6, ip | |
195 | blo 1b | |
196 | #else | |
197 | ||
198 | /* | |
199 | * Relocate entries in the GOT table. We only relocate | |
200 | * the entries that are outside the (relocated) BSS region. | |
201 | */ | |
202 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
203 | cmp r1, r2 @ entry < bss_start || | |
204 | cmphs r3, r1 @ _end < entry | |
205 | addlo r1, r1, r0 @ table. This fixes up the | |
206 | str r1, [r6], #4 @ C references. | |
207 | cmp r6, ip | |
208 | blo 1b | |
209 | #endif | |
210 | ||
211 | not_relocated: mov r0, #0 | |
212 | 1: str r0, [r2], #4 @ clear bss | |
213 | str r0, [r2], #4 | |
214 | str r0, [r2], #4 | |
215 | str r0, [r2], #4 | |
216 | cmp r2, r3 | |
217 | blo 1b | |
218 | ||
219 | /* | |
220 | * The C runtime environment should now be setup | |
221 | * sufficiently. Turn the cache on, set up some | |
222 | * pointers, and start decompressing. | |
223 | */ | |
224 | bl cache_on | |
225 | ||
226 | mov r1, sp @ malloc space above stack | |
227 | add r2, sp, #0x10000 @ 64k max | |
228 | ||
229 | /* | |
230 | * Check to see if we will overwrite ourselves. | |
231 | * r4 = final kernel address | |
232 | * r5 = start of this image | |
233 | * r2 = end of malloc space (and therefore this image) | |
234 | * We basically want: | |
235 | * r4 >= r2 -> OK | |
236 | * r4 + image length <= r5 -> OK | |
237 | */ | |
238 | cmp r4, r2 | |
239 | bhs wont_overwrite | |
2552fc27 LB |
240 | sub r3, sp, r5 @ > compressed kernel size |
241 | add r0, r4, r3, lsl #2 @ allow for 4x expansion | |
1da177e4 LT |
242 | cmp r0, r5 |
243 | bls wont_overwrite | |
244 | ||
245 | mov r5, r2 @ decompress after malloc space | |
246 | mov r0, r5 | |
247 | mov r3, r7 | |
248 | bl decompress_kernel | |
249 | ||
c7341d43 | 250 | add r0, r0, #127 + 128 @ alignment + stack |
1da177e4 LT |
251 | bic r0, r0, #127 @ align the kernel length |
252 | /* | |
253 | * r0 = decompressed kernel length | |
254 | * r1-r3 = unused | |
255 | * r4 = kernel execution address | |
256 | * r5 = decompressed kernel start | |
257 | * r6 = processor ID | |
258 | * r7 = architecture ID | |
f4619025 RK |
259 | * r8 = atags pointer |
260 | * r9-r14 = corrupted | |
1da177e4 LT |
261 | */ |
262 | add r1, r5, r0 @ end of decompressed kernel | |
263 | adr r2, reloc_start | |
264 | ldr r3, LC1 | |
265 | add r3, r2, r3 | |
f4619025 RK |
266 | 1: ldmia r2!, {r9 - r14} @ copy relocation code |
267 | stmia r1!, {r9 - r14} | |
268 | ldmia r2!, {r9 - r14} | |
269 | stmia r1!, {r9 - r14} | |
1da177e4 LT |
270 | cmp r2, r3 |
271 | blo 1b | |
c7341d43 | 272 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
273 | |
274 | bl cache_clean_flush | |
275 | add pc, r5, r0 @ call relocation code | |
276 | ||
277 | /* | |
278 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
279 | * | |
280 | * r4 = kernel execution address | |
281 | * r7 = architecture ID | |
282 | */ | |
283 | wont_overwrite: mov r0, r4 | |
284 | mov r3, r7 | |
285 | bl decompress_kernel | |
286 | b call_kernel | |
287 | ||
288 | .type LC0, #object | |
289 | LC0: .word LC0 @ r1 | |
290 | .word __bss_start @ r2 | |
291 | .word _end @ r3 | |
292 | .word zreladdr @ r4 | |
293 | .word _start @ r5 | |
294 | .word _got_start @ r6 | |
295 | .word _got_end @ ip | |
296 | .word user_stack+4096 @ sp | |
297 | LC1: .word reloc_end - reloc_start | |
298 | .size LC0, . - LC0 | |
299 | ||
300 | #ifdef CONFIG_ARCH_RPC | |
301 | .globl params | |
302 | params: ldr r0, =params_phys | |
303 | mov pc, lr | |
304 | .ltorg | |
305 | .align | |
306 | #endif | |
307 | ||
308 | /* | |
309 | * Turn on the cache. We need to setup some page tables so that we | |
310 | * can have both the I and D caches on. | |
311 | * | |
312 | * We place the page tables 16k down from the kernel execution address, | |
313 | * and we hope that nothing else is using it. If we're using it, we | |
314 | * will go pop! | |
315 | * | |
316 | * On entry, | |
317 | * r4 = kernel execution address | |
318 | * r6 = processor ID | |
319 | * r7 = architecture number | |
f4619025 RK |
320 | * r8 = atags pointer |
321 | * r9 = run-time address of "start" (???) | |
1da177e4 | 322 | * On exit, |
f4619025 | 323 | * r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 324 | * This routine must preserve: |
f4619025 | 325 | * r4, r5, r6, r7, r8 |
1da177e4 LT |
326 | */ |
327 | .align 5 | |
328 | cache_on: mov r3, #8 @ cache_on function | |
329 | b call_cache_fn | |
330 | ||
10c2df65 HC |
331 | /* |
332 | * Initialize the highest priority protection region, PR7 | |
333 | * to cover all 32bit address and cacheable and bufferable. | |
334 | */ | |
335 | __armv4_mpu_cache_on: | |
336 | mov r0, #0x3f @ 4G, the whole | |
337 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
338 | mcr p15, 0, r0, c6, c7, 1 | |
339 | ||
340 | mov r0, #0x80 @ PR7 | |
341 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
342 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
343 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
344 | ||
345 | mov r0, #0xc000 | |
346 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
347 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
348 | ||
349 | mov r0, #0 | |
350 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
351 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
352 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
353 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
354 | @ ...I .... ..D. WC.M | |
355 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
356 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
357 | ||
358 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
359 | ||
360 | mov r0, #0 | |
361 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
362 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
363 | mov pc, lr | |
364 | ||
365 | __armv3_mpu_cache_on: | |
366 | mov r0, #0x3f @ 4G, the whole | |
367 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
368 | ||
369 | mov r0, #0x80 @ PR7 | |
370 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
371 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
372 | ||
373 | mov r0, #0xc000 | |
374 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
375 | ||
376 | mov r0, #0 | |
377 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
378 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
379 | @ .... .... .... WC.M | |
380 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
381 | mov r0, #0 | |
382 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
383 | ||
384 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
385 | mov pc, lr | |
386 | ||
1da177e4 LT |
387 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
388 | bic r3, r3, #0xff @ Align the pointer | |
389 | bic r3, r3, #0x3f00 | |
390 | /* | |
391 | * Initialise the page tables, turning on the cacheable and bufferable | |
392 | * bits for the RAM area only. | |
393 | */ | |
394 | mov r0, r3 | |
f4619025 RK |
395 | mov r9, r0, lsr #18 |
396 | mov r9, r9, lsl #18 @ start of RAM | |
397 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
398 | mov r1, #0x12 |
399 | orr r1, r1, #3 << 10 | |
400 | add r2, r3, #16384 | |
265d5e48 | 401 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 402 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 403 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
404 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
405 | str r1, [r0], #4 @ 1:1 mapping | |
406 | add r1, r1, #1048576 | |
407 | teq r0, r2 | |
408 | bne 1b | |
409 | /* | |
410 | * If ever we are running from Flash, then we surely want the cache | |
411 | * to be enabled also for our execution instance... We map 2MB of it | |
412 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
413 | * If the execution is in RAM then we would only be duplicating the above. | |
414 | */ | |
415 | mov r1, #0x1e | |
416 | orr r1, r1, #3 << 10 | |
417 | mov r2, pc, lsr #20 | |
418 | orr r1, r1, r2, lsl #20 | |
419 | add r0, r3, r2, lsl #2 | |
420 | str r1, [r0], #4 | |
421 | add r1, r1, #1048576 | |
422 | str r1, [r0] | |
423 | mov pc, lr | |
424 | ||
c76b6b41 | 425 | __armv4_mmu_cache_on: |
1da177e4 LT |
426 | mov r12, lr |
427 | bl __setup_mmu | |
428 | mov r0, #0 | |
429 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
430 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
431 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
432 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
433 | orr r0, r0, #0x0030 | |
c76b6b41 | 434 | bl __common_mmu_cache_on |
1da177e4 LT |
435 | mov r0, #0 |
436 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
437 | mov pc, r12 | |
438 | ||
7d09e854 CM |
439 | __armv7_mmu_cache_on: |
440 | mov r12, lr | |
441 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 | |
442 | tst r11, #0xf @ VMSA | |
443 | blne __setup_mmu | |
444 | mov r0, #0 | |
445 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
446 | tst r11, #0xf @ VMSA | |
447 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
448 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
449 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
450 | orr r0, r0, #0x003c @ write buffer | |
451 | orrne r0, r0, #1 @ MMU enabled | |
452 | movne r1, #-1 | |
453 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | |
454 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
455 | mcr p15, 0, r0, c1, c0, 0 @ load control register | |
456 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
457 | mov r0, #0 | |
458 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
459 | mov pc, r12 | |
460 | ||
c76b6b41 | 461 | __arm6_mmu_cache_on: |
1da177e4 LT |
462 | mov r12, lr |
463 | bl __setup_mmu | |
464 | mov r0, #0 | |
465 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
466 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
467 | mov r0, #0x30 | |
c76b6b41 | 468 | bl __common_mmu_cache_on |
1da177e4 LT |
469 | mov r0, #0 |
470 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
471 | mov pc, r12 | |
472 | ||
c76b6b41 | 473 | __common_mmu_cache_on: |
1da177e4 LT |
474 | #ifndef DEBUG |
475 | orr r0, r0, #0x000d @ Write buffer, mmu | |
476 | #endif | |
477 | mov r1, #-1 | |
478 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
479 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
480 | b 1f |
481 | .align 5 @ cache line aligned | |
482 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
483 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
484 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
1da177e4 LT |
485 | |
486 | /* | |
487 | * All code following this line is relocatable. It is relocated by | |
488 | * the above code to the end of the decompressed kernel image and | |
489 | * executed there. During this time, we have no stacks. | |
490 | * | |
491 | * r0 = decompressed kernel length | |
492 | * r1-r3 = unused | |
493 | * r4 = kernel execution address | |
494 | * r5 = decompressed kernel start | |
495 | * r6 = processor ID | |
496 | * r7 = architecture ID | |
f4619025 RK |
497 | * r8 = atags pointer |
498 | * r9-r14 = corrupted | |
1da177e4 LT |
499 | */ |
500 | .align 5 | |
f4619025 | 501 | reloc_start: add r9, r5, r0 |
c7341d43 | 502 | sub r9, r9, #128 @ do not copy the stack |
1da177e4 LT |
503 | debug_reloc_start |
504 | mov r1, r4 | |
505 | 1: | |
506 | .rept 4 | |
f4619025 RK |
507 | ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel |
508 | stmia r1!, {r0, r2, r3, r10 - r14} | |
1da177e4 LT |
509 | .endr |
510 | ||
f4619025 | 511 | cmp r5, r9 |
1da177e4 | 512 | blo 1b |
c7341d43 | 513 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
514 | debug_reloc_end |
515 | ||
516 | call_kernel: bl cache_clean_flush | |
517 | bl cache_off | |
f4619025 | 518 | mov r0, #0 @ must be zero |
1da177e4 | 519 | mov r1, r7 @ restore architecture number |
f4619025 | 520 | mov r2, r8 @ restore atags pointer |
1da177e4 LT |
521 | mov pc, r4 @ call kernel |
522 | ||
523 | /* | |
524 | * Here follow the relocatable cache support functions for the | |
525 | * various processors. This is a generic hook for locating an | |
526 | * entry and jumping to an instruction at the specified offset | |
527 | * from the start of the block. Please note this is all position | |
528 | * independent code. | |
529 | * | |
530 | * r1 = corrupted | |
531 | * r2 = corrupted | |
532 | * r3 = block offset | |
533 | * r6 = corrupted | |
534 | * r12 = corrupted | |
535 | */ | |
536 | ||
537 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 538 | #ifdef CONFIG_CPU_CP15 |
1da177e4 | 539 | mrc p15, 0, r6, c0, c0 @ get processor ID |
f12d0d7c HC |
540 | #else |
541 | ldr r6, =CONFIG_PROCESSOR_ID | |
542 | #endif | |
1da177e4 LT |
543 | 1: ldr r1, [r12, #0] @ get value |
544 | ldr r2, [r12, #4] @ get mask | |
545 | eor r1, r1, r6 @ (real ^ match) | |
546 | tst r1, r2 @ & mask | |
547 | addeq pc, r12, r3 @ call cache function | |
548 | add r12, r12, #4*5 | |
549 | b 1b | |
550 | ||
551 | /* | |
552 | * Table for cache operations. This is basically: | |
553 | * - CPU ID match | |
554 | * - CPU ID mask | |
555 | * - 'cache on' method instruction | |
556 | * - 'cache off' method instruction | |
557 | * - 'cache flush' method instruction | |
558 | * | |
559 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
560 | * | |
561 | * Writethrough caches generally only need 'on' and 'off' | |
562 | * methods. Writeback caches _must_ have the flush method | |
563 | * defined. | |
564 | */ | |
565 | .type proc_types,#object | |
566 | proc_types: | |
567 | .word 0x41560600 @ ARM6/610 | |
568 | .word 0xffffffe0 | |
c76b6b41 HC |
569 | b __arm6_mmu_cache_off @ works, but slow |
570 | b __arm6_mmu_cache_off | |
1da177e4 | 571 | mov pc, lr |
c76b6b41 HC |
572 | @ b __arm6_mmu_cache_on @ untested |
573 | @ b __arm6_mmu_cache_off | |
574 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
575 | |
576 | .word 0x00000000 @ old ARM ID | |
577 | .word 0x0000f000 | |
578 | mov pc, lr | |
579 | mov pc, lr | |
580 | mov pc, lr | |
581 | ||
582 | .word 0x41007000 @ ARM7/710 | |
583 | .word 0xfff8fe00 | |
c76b6b41 HC |
584 | b __arm7_mmu_cache_off |
585 | b __arm7_mmu_cache_off | |
1da177e4 LT |
586 | mov pc, lr |
587 | ||
588 | .word 0x41807200 @ ARM720T (writethrough) | |
589 | .word 0xffffff00 | |
c76b6b41 HC |
590 | b __armv4_mmu_cache_on |
591 | b __armv4_mmu_cache_off | |
1da177e4 LT |
592 | mov pc, lr |
593 | ||
10c2df65 HC |
594 | .word 0x41007400 @ ARM74x |
595 | .word 0xff00ff00 | |
596 | b __armv3_mpu_cache_on | |
597 | b __armv3_mpu_cache_off | |
598 | b __armv3_mpu_cache_flush | |
599 | ||
600 | .word 0x41009400 @ ARM94x | |
601 | .word 0xff00ff00 | |
602 | b __armv4_mpu_cache_on | |
603 | b __armv4_mpu_cache_off | |
604 | b __armv4_mpu_cache_flush | |
605 | ||
1da177e4 LT |
606 | .word 0x00007000 @ ARM7 IDs |
607 | .word 0x0000f000 | |
608 | mov pc, lr | |
609 | mov pc, lr | |
610 | mov pc, lr | |
611 | ||
612 | @ Everything from here on will be the new ID system. | |
613 | ||
614 | .word 0x4401a100 @ sa110 / sa1100 | |
615 | .word 0xffffffe0 | |
c76b6b41 HC |
616 | b __armv4_mmu_cache_on |
617 | b __armv4_mmu_cache_off | |
618 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
619 | |
620 | .word 0x6901b110 @ sa1110 | |
621 | .word 0xfffffff0 | |
c76b6b41 HC |
622 | b __armv4_mmu_cache_on |
623 | b __armv4_mmu_cache_off | |
624 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
625 | |
626 | @ These match on the architecture ID | |
627 | ||
628 | .word 0x00020000 @ ARMv4T | |
629 | .word 0x000f0000 | |
c76b6b41 HC |
630 | b __armv4_mmu_cache_on |
631 | b __armv4_mmu_cache_off | |
632 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
633 | |
634 | .word 0x00050000 @ ARMv5TE | |
635 | .word 0x000f0000 | |
c76b6b41 HC |
636 | b __armv4_mmu_cache_on |
637 | b __armv4_mmu_cache_off | |
638 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
639 | |
640 | .word 0x00060000 @ ARMv5TEJ | |
641 | .word 0x000f0000 | |
c76b6b41 HC |
642 | b __armv4_mmu_cache_on |
643 | b __armv4_mmu_cache_off | |
644 | b __armv4_mmu_cache_flush | |
1da177e4 | 645 | |
45a7b9cf | 646 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 647 | .word 0x000ff000 |
c76b6b41 HC |
648 | b __armv4_mmu_cache_on |
649 | b __armv4_mmu_cache_off | |
650 | b __armv6_mmu_cache_flush | |
1da177e4 | 651 | |
7d09e854 CM |
652 | .word 0x000f0000 @ new CPU Id |
653 | .word 0x000f0000 | |
654 | b __armv7_mmu_cache_on | |
655 | b __armv7_mmu_cache_off | |
656 | b __armv7_mmu_cache_flush | |
657 | ||
1da177e4 LT |
658 | .word 0 @ unrecognised type |
659 | .word 0 | |
660 | mov pc, lr | |
661 | mov pc, lr | |
662 | mov pc, lr | |
663 | ||
664 | .size proc_types, . - proc_types | |
665 | ||
666 | /* | |
667 | * Turn off the Cache and MMU. ARMv3 does not support | |
668 | * reading the control register, but ARMv4 does. | |
669 | * | |
670 | * On entry, r6 = processor ID | |
671 | * On exit, r0, r1, r2, r3, r12 corrupted | |
672 | * This routine must preserve: r4, r6, r7 | |
673 | */ | |
674 | .align 5 | |
675 | cache_off: mov r3, #12 @ cache_off function | |
676 | b call_cache_fn | |
677 | ||
10c2df65 HC |
678 | __armv4_mpu_cache_off: |
679 | mrc p15, 0, r0, c1, c0 | |
680 | bic r0, r0, #0x000d | |
681 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
682 | mov r0, #0 | |
683 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
684 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
685 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
686 | mov pc, lr | |
687 | ||
688 | __armv3_mpu_cache_off: | |
689 | mrc p15, 0, r0, c1, c0 | |
690 | bic r0, r0, #0x000d | |
691 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
692 | mov r0, #0 | |
693 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
694 | mov pc, lr | |
695 | ||
c76b6b41 | 696 | __armv4_mmu_cache_off: |
1da177e4 LT |
697 | mrc p15, 0, r0, c1, c0 |
698 | bic r0, r0, #0x000d | |
699 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
700 | mov r0, #0 | |
701 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
702 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
703 | mov pc, lr | |
704 | ||
7d09e854 CM |
705 | __armv7_mmu_cache_off: |
706 | mrc p15, 0, r0, c1, c0 | |
707 | bic r0, r0, #0x000d | |
708 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
709 | mov r12, lr | |
710 | bl __armv7_mmu_cache_flush | |
711 | mov r0, #0 | |
712 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB | |
713 | mov pc, r12 | |
714 | ||
c76b6b41 | 715 | __arm6_mmu_cache_off: |
1da177e4 | 716 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 717 | b __armv3_mmu_cache_off |
1da177e4 | 718 | |
c76b6b41 | 719 | __arm7_mmu_cache_off: |
1da177e4 | 720 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 721 | b __armv3_mmu_cache_off |
1da177e4 | 722 | |
c76b6b41 | 723 | __armv3_mmu_cache_off: |
1da177e4 LT |
724 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
725 | mov r0, #0 | |
726 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
727 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
728 | mov pc, lr | |
729 | ||
730 | /* | |
731 | * Clean and flush the cache to maintain consistency. | |
732 | * | |
733 | * On entry, | |
734 | * r6 = processor ID | |
735 | * On exit, | |
736 | * r1, r2, r3, r11, r12 corrupted | |
737 | * This routine must preserve: | |
738 | * r0, r4, r5, r6, r7 | |
739 | */ | |
740 | .align 5 | |
741 | cache_clean_flush: | |
742 | mov r3, #16 | |
743 | b call_cache_fn | |
744 | ||
10c2df65 HC |
745 | __armv4_mpu_cache_flush: |
746 | mov r2, #1 | |
747 | mov r3, #0 | |
748 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
749 | mov r1, #7 << 5 @ 8 segments | |
750 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
751 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
752 | subs r3, r3, #1 << 26 | |
753 | bcs 2b @ entries 63 to 0 | |
754 | subs r1, r1, #1 << 5 | |
755 | bcs 1b @ segments 7 to 0 | |
756 | ||
757 | teq r2, #0 | |
758 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
759 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
760 | mov pc, lr | |
761 | ||
762 | ||
c76b6b41 | 763 | __armv6_mmu_cache_flush: |
1da177e4 LT |
764 | mov r1, #0 |
765 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
766 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
767 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
768 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
769 | mov pc, lr | |
770 | ||
7d09e854 CM |
771 | __armv7_mmu_cache_flush: |
772 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
773 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
774 | beq hierarchical | |
775 | mov r10, #0 | |
776 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D | |
777 | b iflush | |
778 | hierarchical: | |
779 | stmfd sp!, {r0-r5, r7, r9-r11} | |
780 | mrc p15, 1, r0, c0, c0, 1 @ read clidr | |
781 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
782 | mov r3, r3, lsr #23 @ left align loc bit field | |
783 | beq finished @ if loc is 0, then no need to clean | |
784 | mov r10, #0 @ start clean at cache level 0 | |
785 | loop1: | |
786 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
787 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
788 | and r1, r1, #7 @ mask of the bits for current cache only | |
789 | cmp r1, #2 @ see what cache we have at this level | |
790 | blt skip @ skip if no cache, or just i-cache | |
791 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
792 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
793 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
794 | and r2, r1, #7 @ extract the length of the cache lines | |
795 | add r2, r2, #4 @ add 4 (line length offset) | |
796 | ldr r4, =0x3ff | |
797 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
798 | .word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment | |
799 | ldr r7, =0x7fff | |
800 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
801 | loop2: | |
802 | mov r9, r4 @ create working copy of max way size | |
803 | loop3: | |
804 | orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 | |
805 | orr r11, r11, r7, lsl r2 @ factor index number into r11 | |
806 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way | |
807 | subs r9, r9, #1 @ decrement the way | |
808 | bge loop3 | |
809 | subs r7, r7, #1 @ decrement the index | |
810 | bge loop2 | |
811 | skip: | |
812 | add r10, r10, #2 @ increment cache number | |
813 | cmp r3, r10 | |
814 | bgt loop1 | |
815 | finished: | |
816 | mov r10, #0 @ swith back to cache level 0 | |
817 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
818 | ldmfd sp!, {r0-r5, r7, r9-r11} | |
819 | iflush: | |
820 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB | |
821 | mcr p15, 0, r10, c7, c10, 4 @ drain WB | |
822 | mov pc, lr | |
823 | ||
c76b6b41 | 824 | __armv4_mmu_cache_flush: |
1da177e4 LT |
825 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
826 | mov r11, #32 @ default: 32 byte line size | |
827 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
828 | teq r3, r6 @ cache ID register present? | |
829 | beq no_cache_id | |
830 | mov r1, r3, lsr #18 | |
831 | and r1, r1, #7 | |
832 | mov r2, #1024 | |
833 | mov r2, r2, lsl r1 @ base dcache size *2 | |
834 | tst r3, #1 << 14 @ test M bit | |
835 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
836 | mov r3, r3, lsr #12 | |
837 | and r3, r3, #3 | |
838 | mov r11, #8 | |
839 | mov r11, r11, lsl r3 @ cache line size in bytes | |
840 | no_cache_id: | |
841 | bic r1, pc, #63 @ align to longest cache line | |
842 | add r2, r1, r2 | |
843 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
844 | teq r1, r2 | |
845 | bne 1b | |
846 | ||
847 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
848 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
849 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
850 | mov pc, lr | |
851 | ||
c76b6b41 | 852 | __armv3_mmu_cache_flush: |
10c2df65 | 853 | __armv3_mpu_cache_flush: |
1da177e4 LT |
854 | mov r1, #0 |
855 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
856 | mov pc, lr | |
857 | ||
858 | /* | |
859 | * Various debugging routines for printing hex characters and | |
860 | * memory, which again must be relocatable. | |
861 | */ | |
862 | #ifdef DEBUG | |
863 | .type phexbuf,#object | |
864 | phexbuf: .space 12 | |
865 | .size phexbuf, . - phexbuf | |
866 | ||
867 | phex: adr r3, phexbuf | |
868 | mov r2, #0 | |
869 | strb r2, [r3, r1] | |
870 | 1: subs r1, r1, #1 | |
871 | movmi r0, r3 | |
872 | bmi puts | |
873 | and r2, r0, #15 | |
874 | mov r0, r0, lsr #4 | |
875 | cmp r2, #10 | |
876 | addge r2, r2, #7 | |
877 | add r2, r2, #'0' | |
878 | strb r2, [r3, r1] | |
879 | b 1b | |
880 | ||
881 | puts: loadsp r3 | |
882 | 1: ldrb r2, [r0], #1 | |
883 | teq r2, #0 | |
884 | moveq pc, lr | |
5cd0c344 | 885 | 2: writeb r2, r3 |
1da177e4 LT |
886 | mov r1, #0x00020000 |
887 | 3: subs r1, r1, #1 | |
888 | bne 3b | |
889 | teq r2, #'\n' | |
890 | moveq r2, #'\r' | |
891 | beq 2b | |
892 | teq r0, #0 | |
893 | bne 1b | |
894 | mov pc, lr | |
895 | putc: | |
896 | mov r2, r0 | |
897 | mov r0, #0 | |
898 | loadsp r3 | |
899 | b 2b | |
900 | ||
901 | memdump: mov r12, r0 | |
902 | mov r10, lr | |
903 | mov r11, #0 | |
904 | 2: mov r0, r11, lsl #2 | |
905 | add r0, r0, r12 | |
906 | mov r1, #8 | |
907 | bl phex | |
908 | mov r0, #':' | |
909 | bl putc | |
910 | 1: mov r0, #' ' | |
911 | bl putc | |
912 | ldr r0, [r12, r11, lsl #2] | |
913 | mov r1, #8 | |
914 | bl phex | |
915 | and r0, r11, #7 | |
916 | teq r0, #3 | |
917 | moveq r0, #' ' | |
918 | bleq putc | |
919 | and r0, r11, #7 | |
920 | add r11, r11, #1 | |
921 | teq r0, #7 | |
922 | bne 1b | |
923 | mov r0, #'\n' | |
924 | bl putc | |
925 | cmp r11, #64 | |
926 | blt 2b | |
927 | mov pc, r10 | |
928 | #endif | |
929 | ||
92c83ff1 | 930 | .ltorg |
1da177e4 LT |
931 | reloc_end: |
932 | ||
933 | .align | |
934 | .section ".stack", "w" | |
935 | user_stack: .space 4096 |