Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
1d8f51d4 | 5 | select ARCH_CLOCKSOURCE_DATA |
ec80eb46 | 6 | select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC |
c7780ab5 | 7 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
21266be9 | 8 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
2b68f6ca | 9 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 10 | select ARCH_HAS_FORTIFY_SOURCE |
75851720 | 11 | select ARCH_HAS_KCOV |
e69244d2 | 12 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
3010a5ea | 13 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
ea8c64ac | 14 | select ARCH_HAS_PHYS_TO_DMA |
75851720 | 15 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
16 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
17 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
3d06770e | 18 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 19 | select ARCH_HAVE_CUSTOM_GPIO_H |
957e3fac | 20 | select ARCH_HAS_GCOV_PROFILE_ALL |
d7018848 | 21 | select ARCH_MIGHT_HAVE_PC_PARPORT |
ad21fc4f LA |
22 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
23 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 24 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 25 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 26 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 27 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 28 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 29 | select CLONE_BACKWARDS |
b1b3f49c | 30 | select CPU_PM if (SUSPEND || CPU_IDLE) |
dce5c9e3 | 31 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
002e6745 | 32 | select DMA_DIRECT_OPS if !MMU |
b01aec9b BP |
33 | select EDAC_SUPPORT |
34 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 35 | select GENERIC_ALLOCATOR |
2ef7a295 | 36 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
4477ca45 | 37 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 38 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
ea2d9a96 | 39 | select GENERIC_CPU_AUTOPROBE |
2937367b | 40 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 41 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
42 | select GENERIC_IRQ_PROBE |
43 | select GENERIC_IRQ_SHOW | |
7c07005e | 44 | select GENERIC_IRQ_SHOW_LEVEL |
b1b3f49c | 45 | select GENERIC_PCI_IOMAP |
38ff87f7 | 46 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
47 | select GENERIC_SMP_IDLE_THREAD |
48 | select GENERIC_STRNCPY_FROM_USER | |
49 | select GENERIC_STRNLEN_USER | |
a71b092a | 50 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 51 | select HARDIRQS_SW_RESEND |
7a017721 | 52 | select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) |
0b7857db | 53 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee AB |
54 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
55 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU | |
e0c25d95 | 56 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
91702175 | 57 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
08626a60 | 58 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 59 | select HAVE_ARCH_TRACEHOOK |
b329f95d | 60 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 61 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 62 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
63 | select HAVE_C_RECORDMCOUNT |
64 | select HAVE_DEBUG_KMEMLEAK | |
b1b3f49c | 65 | select HAVE_DMA_CONTIGUOUS if MMU |
437682ee | 66 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 67 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 68 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 69 | select HAVE_EXIT_THREAD |
b1b3f49c | 70 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 71 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 72 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
6b90bd4b | 73 | select HAVE_GCC_PLUGINS |
1fe53268 | 74 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
75 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
76 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 77 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 78 | select HAVE_KERNEL_GZIP |
f9b493ac | 79 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 80 | select HAVE_KERNEL_LZMA |
b1b3f49c | 81 | select HAVE_KERNEL_LZO |
a7f464f3 | 82 | select HAVE_KERNEL_XZ |
cb1293e2 | 83 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
b1b3f49c RK |
84 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
85 | select HAVE_MEMBLOCK | |
7d485f64 | 86 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 87 | select HAVE_NMI |
b1b3f49c | 88 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
0dc016db | 89 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 90 | select HAVE_PERF_EVENTS |
49863894 WD |
91 | select HAVE_PERF_REGS |
92 | select HAVE_PERF_USER_STACK_DUMP | |
a0ad5496 | 93 | select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) |
e513f8bf | 94 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 95 | select HAVE_RSEQ |
d148eac0 | 96 | select HAVE_STACKPROTECTOR |
b1b3f49c | 97 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 98 | select HAVE_UID16 |
31c1fc81 | 99 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 100 | select IRQ_FORCED_THREADING |
171b3f0d | 101 | select MODULES_USE_ELF_REL |
f616ab59 | 102 | select NEED_DMA_MAP_STATE |
aa7d5f18 AB |
103 | select OF_EARLY_FLATTREE if OF |
104 | select OF_RESERVED_MEM if OF | |
171b3f0d RK |
105 | select OLD_SIGACTION |
106 | select OLD_SIGSUSPEND3 | |
b1b3f49c | 107 | select PERF_USE_VMALLOC |
b26d07a0 | 108 | select REFCOUNT_FULL |
b1b3f49c RK |
109 | select RTC_LIB |
110 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
111 | # Above selects are sorted alphabetically; please add new ones |
112 | # according to that. Thanks. | |
1da177e4 LT |
113 | help |
114 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 115 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 116 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 117 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
118 | Europe. There is an ARM Linux project with a web page at |
119 | <http://www.arm.linux.org.uk/>. | |
120 | ||
74facffe | 121 | config ARM_HAS_SG_CHAIN |
308c09f1 | 122 | select ARCH_HAS_SG_CHAIN |
74facffe RK |
123 | bool |
124 | ||
4ce63fcd | 125 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 126 | bool |
b1b3f49c RK |
127 | select ARM_HAS_SG_CHAIN |
128 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 129 | |
60460abf SWK |
130 | if ARM_DMA_USE_IOMMU |
131 | ||
132 | config ARM_DMA_IOMMU_ALIGNMENT | |
133 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
134 | range 4 9 | |
135 | default 8 | |
136 | help | |
137 | DMA mapping framework by default aligns all buffers to the smallest | |
138 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
139 | size. This works well for buffers up to a few hundreds kilobytes, but | |
140 | for larger buffers it just a waste of address space. Drivers which has | |
141 | relatively small addressing window (like 64Mib) might run out of | |
142 | virtual space with just a few allocations. | |
143 | ||
144 | With this parameter you can specify the maximum PAGE_SIZE order for | |
145 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
146 | specified order. The order is expressed as a power of two multiplied | |
147 | by the PAGE_SIZE. | |
148 | ||
149 | endif | |
150 | ||
0b05da72 HUK |
151 | config MIGHT_HAVE_PCI |
152 | bool | |
153 | ||
75e7153a RB |
154 | config SYS_SUPPORTS_APM_EMULATION |
155 | bool | |
156 | ||
bc581770 LW |
157 | config HAVE_TCM |
158 | bool | |
159 | select GENERIC_ALLOCATOR | |
160 | ||
e119bfff RK |
161 | config HAVE_PROC_CPU |
162 | bool | |
163 | ||
ce816fa8 | 164 | config NO_IOPORT_MAP |
5ea81769 | 165 | bool |
5ea81769 | 166 | |
1da177e4 LT |
167 | config EISA |
168 | bool | |
169 | ---help--- | |
170 | The Extended Industry Standard Architecture (EISA) bus was | |
171 | developed as an open alternative to the IBM MicroChannel bus. | |
172 | ||
173 | The EISA bus provided some of the features of the IBM MicroChannel | |
174 | bus while maintaining backward compatibility with cards made for | |
175 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
176 | 1995 when it was made obsolete by the PCI bus. | |
177 | ||
178 | Say Y here if you are building a kernel for an EISA-based machine. | |
179 | ||
180 | Otherwise, say N. | |
181 | ||
182 | config SBUS | |
183 | bool | |
184 | ||
f16fb1ec RK |
185 | config STACKTRACE_SUPPORT |
186 | bool | |
187 | default y | |
188 | ||
189 | config LOCKDEP_SUPPORT | |
190 | bool | |
191 | default y | |
192 | ||
7ad1bcb2 RK |
193 | config TRACE_IRQFLAGS_SUPPORT |
194 | bool | |
cb1293e2 | 195 | default !CPU_V7M |
7ad1bcb2 | 196 | |
1da177e4 LT |
197 | config RWSEM_XCHGADD_ALGORITHM |
198 | bool | |
8a87411b | 199 | default y |
1da177e4 | 200 | |
f0d1b0b3 DH |
201 | config ARCH_HAS_ILOG2_U32 |
202 | bool | |
f0d1b0b3 DH |
203 | |
204 | config ARCH_HAS_ILOG2_U64 | |
205 | bool | |
f0d1b0b3 | 206 | |
4a1b5733 EV |
207 | config ARCH_HAS_BANDGAP |
208 | bool | |
209 | ||
a5f4c561 SA |
210 | config FIX_EARLYCON_MEM |
211 | def_bool y if MMU | |
212 | ||
b89c3b16 AM |
213 | config GENERIC_HWEIGHT |
214 | bool | |
215 | default y | |
216 | ||
1da177e4 LT |
217 | config GENERIC_CALIBRATE_DELAY |
218 | bool | |
219 | default y | |
220 | ||
a08b6b79 Z |
221 | config ARCH_MAY_HAVE_PC_FDC |
222 | bool | |
223 | ||
5ac6da66 CL |
224 | config ZONE_DMA |
225 | bool | |
5ac6da66 | 226 | |
c7edc9e3 DL |
227 | config ARCH_SUPPORTS_UPROBES |
228 | def_bool y | |
229 | ||
58af4a24 RH |
230 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
231 | bool | |
232 | ||
1da177e4 LT |
233 | config GENERIC_ISA_DMA |
234 | bool | |
235 | ||
1da177e4 LT |
236 | config FIQ |
237 | bool | |
238 | ||
13a5045d RH |
239 | config NEED_RET_TO_USER |
240 | bool | |
241 | ||
034d2f5a AV |
242 | config ARCH_MTD_XIP |
243 | bool | |
244 | ||
dc21af99 | 245 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
246 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
247 | default y | |
b511d75d | 248 | depends on !XIP_KERNEL && MMU |
dc21af99 | 249 | help |
111e9a5c RK |
250 | Patch phys-to-virt and virt-to-phys translation functions at |
251 | boot and module load time according to the position of the | |
252 | kernel in system memory. | |
dc21af99 | 253 | |
111e9a5c | 254 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 255 | of physical memory is at a 16MB boundary. |
dc21af99 | 256 | |
c1becedc RK |
257 | Only disable this option if you know that you do not require |
258 | this feature (eg, building a kernel for a single machine) and | |
259 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 260 | |
c334bc15 RH |
261 | config NEED_MACH_IO_H |
262 | bool | |
263 | help | |
264 | Select this when mach/io.h is required to provide special | |
265 | definitions for this platform. The need for mach/io.h should | |
266 | be avoided when possible. | |
267 | ||
0cdc8b92 | 268 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
269 | bool |
270 | help | |
0cdc8b92 NP |
271 | Select this when mach/memory.h is required to provide special |
272 | definitions for this platform. The need for mach/memory.h should | |
273 | be avoided when possible. | |
dc21af99 | 274 | |
1b9f95f8 | 275 | config PHYS_OFFSET |
974c0724 | 276 | hex "Physical address of main memory" if MMU |
c6f54a9b | 277 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 278 | default DRAM_BASE if !MMU |
c6f54a9b | 279 | default 0x00000000 if ARCH_EBSA110 || \ |
c6f54a9b UKK |
280 | ARCH_FOOTBRIDGE || \ |
281 | ARCH_INTEGRATOR || \ | |
282 | ARCH_IOP13XX || \ | |
283 | ARCH_KS8695 || \ | |
8f2c0062 | 284 | ARCH_REALVIEW |
c6f54a9b UKK |
285 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
286 | default 0x20000000 if ARCH_S5PV210 | |
b8824c9a | 287 | default 0xc0000000 if ARCH_SA1100 |
111e9a5c | 288 | help |
1b9f95f8 NP |
289 | Please provide the physical address corresponding to the |
290 | location of main memory in your system. | |
cada3c08 | 291 | |
87e040b6 SG |
292 | config GENERIC_BUG |
293 | def_bool y | |
294 | depends on BUG | |
295 | ||
1bcad26e KS |
296 | config PGTABLE_LEVELS |
297 | int | |
298 | default 3 if ARM_LPAE | |
299 | default 2 | |
300 | ||
1da177e4 LT |
301 | menu "System Type" |
302 | ||
3c427975 HC |
303 | config MMU |
304 | bool "MMU-based Paged Memory Management Support" | |
305 | default y | |
306 | help | |
307 | Select if you want MMU-based virtualised addressing space | |
308 | support by paged memory management. If unsure, say 'Y'. | |
309 | ||
e0c25d95 DC |
310 | config ARCH_MMAP_RND_BITS_MIN |
311 | default 8 | |
312 | ||
313 | config ARCH_MMAP_RND_BITS_MAX | |
314 | default 14 if PAGE_OFFSET=0x40000000 | |
315 | default 15 if PAGE_OFFSET=0x80000000 | |
316 | default 16 | |
317 | ||
ccf50e23 RK |
318 | # |
319 | # The "ARM system type" choice list is ordered alphabetically by option | |
320 | # text. Please add new entries in the option alphabetic order. | |
321 | # | |
1da177e4 LT |
322 | choice |
323 | prompt "ARM system type" | |
70722803 | 324 | default ARM_SINGLE_ARMV7M if !MMU |
1420b22b | 325 | default ARCH_MULTIPLATFORM if MMU |
1da177e4 | 326 | |
387798b3 RH |
327 | config ARCH_MULTIPLATFORM |
328 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 329 | depends on MMU |
42dc836d | 330 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
331 | select ARM_PATCH_PHYS_VIRT |
332 | select AUTO_ZRELADDR | |
bb0eb050 | 333 | select TIMER_OF |
66314223 | 334 | select COMMON_CLK |
ddb902cc | 335 | select GENERIC_CLOCKEVENTS |
4c301f9b | 336 | select GENERIC_IRQ_MULTI_HANDLER |
08d38beb | 337 | select MIGHT_HAVE_PCI |
e13688fe | 338 | select PCI_DOMAINS if PCI |
66314223 DN |
339 | select SPARSE_IRQ |
340 | select USE_OF | |
66314223 | 341 | |
9c77bc43 SA |
342 | config ARM_SINGLE_ARMV7M |
343 | bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" | |
344 | depends on !MMU | |
9c77bc43 | 345 | select ARM_NVIC |
499f1640 | 346 | select AUTO_ZRELADDR |
bb0eb050 | 347 | select TIMER_OF |
9c77bc43 SA |
348 | select COMMON_CLK |
349 | select CPU_V7M | |
350 | select GENERIC_CLOCKEVENTS | |
351 | select NO_IOPORT_MAP | |
352 | select SPARSE_IRQ | |
353 | select USE_OF | |
354 | ||
1da177e4 LT |
355 | config ARCH_EBSA110 |
356 | bool "EBSA-110" | |
b1b3f49c | 357 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 358 | select CPU_SA110 |
f7e68bbf | 359 | select ISA |
c334bc15 | 360 | select NEED_MACH_IO_H |
0cdc8b92 | 361 | select NEED_MACH_MEMORY_H |
ce816fa8 | 362 | select NO_IOPORT_MAP |
1da177e4 LT |
363 | help |
364 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 365 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
366 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
367 | parallel port. | |
368 | ||
e7736d47 LB |
369 | config ARCH_EP93XX |
370 | bool "EP93xx-based" | |
80320927 | 371 | select ARCH_SPARSEMEM_ENABLE |
e7736d47 | 372 | select ARM_AMBA |
cd5bad41 | 373 | imply ARM_PATCH_PHYS_VIRT |
e7736d47 | 374 | select ARM_VIC |
b8824c9a | 375 | select AUTO_ZRELADDR |
6d803ba7 | 376 | select CLKDEV_LOOKUP |
000bc178 | 377 | select CLKSRC_MMIO |
b1b3f49c | 378 | select CPU_ARM920T |
000bc178 | 379 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 380 | select GPIOLIB |
e7736d47 LB |
381 | help |
382 | This enables support for the Cirrus EP93xx series of CPUs. | |
383 | ||
1da177e4 LT |
384 | config ARCH_FOOTBRIDGE |
385 | bool "FootBridge" | |
c750815e | 386 | select CPU_SA110 |
1da177e4 | 387 | select FOOTBRIDGE |
4e8d7637 | 388 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 389 | select HAVE_IDE |
8ef6e620 | 390 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 391 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
392 | help |
393 | Support for systems based on the DC21285 companion chip | |
394 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 395 | |
4af6fee1 DS |
396 | config ARCH_NETX |
397 | bool "Hilscher NetX based" | |
b1b3f49c | 398 | select ARM_VIC |
234b6ced | 399 | select CLKSRC_MMIO |
c750815e | 400 | select CPU_ARM926T |
2fcfe6b8 | 401 | select GENERIC_CLOCKEVENTS |
f999b8bd | 402 | help |
4af6fee1 DS |
403 | This enables support for systems based on the Hilscher NetX Soc |
404 | ||
3b938be6 RK |
405 | config ARCH_IOP13XX |
406 | bool "IOP13xx-based" | |
407 | depends on MMU | |
b1b3f49c | 408 | select CPU_XSC3 |
0cdc8b92 | 409 | select NEED_MACH_MEMORY_H |
13a5045d | 410 | select NEED_RET_TO_USER |
b1b3f49c RK |
411 | select PCI |
412 | select PLAT_IOP | |
413 | select VMSPLIT_1G | |
37ebbcff | 414 | select SPARSE_IRQ |
3b938be6 RK |
415 | help |
416 | Support for Intel's IOP13XX (XScale) family of processors. | |
417 | ||
3f7e5815 LB |
418 | config ARCH_IOP32X |
419 | bool "IOP32x-based" | |
a4f7e763 | 420 | depends on MMU |
c750815e | 421 | select CPU_XSCALE |
e9004f50 | 422 | select GPIO_IOP |
5c34a4e8 | 423 | select GPIOLIB |
13a5045d | 424 | select NEED_RET_TO_USER |
f7e68bbf | 425 | select PCI |
b1b3f49c | 426 | select PLAT_IOP |
f999b8bd | 427 | help |
3f7e5815 LB |
428 | Support for Intel's 80219 and IOP32X (XScale) family of |
429 | processors. | |
430 | ||
431 | config ARCH_IOP33X | |
432 | bool "IOP33x-based" | |
433 | depends on MMU | |
c750815e | 434 | select CPU_XSCALE |
e9004f50 | 435 | select GPIO_IOP |
5c34a4e8 | 436 | select GPIOLIB |
13a5045d | 437 | select NEED_RET_TO_USER |
3f7e5815 | 438 | select PCI |
b1b3f49c | 439 | select PLAT_IOP |
3f7e5815 LB |
440 | help |
441 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 442 | |
3b938be6 RK |
443 | config ARCH_IXP4XX |
444 | bool "IXP4xx-based" | |
a4f7e763 | 445 | depends on MMU |
58af4a24 | 446 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
51aaf81f | 447 | select ARCH_SUPPORTS_BIG_ENDIAN |
234b6ced | 448 | select CLKSRC_MMIO |
c750815e | 449 | select CPU_XSCALE |
b1b3f49c | 450 | select DMABOUNCE if PCI |
3b938be6 | 451 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 452 | select GPIOLIB |
0b05da72 | 453 | select MIGHT_HAVE_PCI |
c334bc15 | 454 | select NEED_MACH_IO_H |
9296d94d | 455 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 456 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 457 | help |
3b938be6 | 458 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 459 | |
edabd38e SB |
460 | config ARCH_DOVE |
461 | bool "Marvell Dove" | |
756b2531 | 462 | select CPU_PJ4 |
edabd38e | 463 | select GENERIC_CLOCKEVENTS |
4c301f9b | 464 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 465 | select GPIOLIB |
0f81bd43 | 466 | select MIGHT_HAVE_PCI |
171b3f0d | 467 | select MVEBU_MBUS |
9139acd1 SH |
468 | select PINCTRL |
469 | select PINCTRL_DOVE | |
abcda1dc | 470 | select PLAT_ORION_LEGACY |
0bd86961 | 471 | select SPARSE_IRQ |
c5d431e8 | 472 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 473 | help |
edabd38e | 474 | Support for the Marvell Dove SoC 88AP510 |
788c9700 RK |
475 | |
476 | config ARCH_KS8695 | |
477 | bool "Micrel/Kendin KS8695" | |
c7e783d6 | 478 | select CLKSRC_MMIO |
b1b3f49c | 479 | select CPU_ARM922T |
c7e783d6 | 480 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 481 | select GPIOLIB |
b1b3f49c | 482 | select NEED_MACH_MEMORY_H |
788c9700 RK |
483 | help |
484 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
485 | System-on-Chip devices. | |
486 | ||
788c9700 RK |
487 | config ARCH_W90X900 |
488 | bool "Nuvoton W90X900 CPU" | |
6d803ba7 | 489 | select CLKDEV_LOOKUP |
6fa5d5f7 | 490 | select CLKSRC_MMIO |
b1b3f49c | 491 | select CPU_ARM926T |
58b5369e | 492 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 493 | select GPIOLIB |
788c9700 | 494 | help |
a8bc4ead | 495 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
496 | At present, the w90x900 has been renamed nuc900, regarding | |
497 | the ARM series product line, you can login the following | |
498 | link address to know more. | |
499 | ||
500 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
501 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 502 | |
93e22567 RK |
503 | config ARCH_LPC32XX |
504 | bool "NXP LPC32XX" | |
93e22567 RK |
505 | select ARM_AMBA |
506 | select CLKDEV_LOOKUP | |
c227f127 VZ |
507 | select CLKSRC_LPC32XX |
508 | select COMMON_CLK | |
93e22567 RK |
509 | select CPU_ARM926T |
510 | select GENERIC_CLOCKEVENTS | |
4c301f9b | 511 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 512 | select GPIOLIB |
8cb17b5e | 513 | select SPARSE_IRQ |
93e22567 RK |
514 | select USE_OF |
515 | help | |
516 | Support for the NXP LPC32XX family of processors | |
517 | ||
1da177e4 | 518 | config ARCH_PXA |
2c8086a5 | 519 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 520 | depends on MMU |
b1b3f49c | 521 | select ARCH_MTD_XIP |
b1b3f49c RK |
522 | select ARM_CPU_SUSPEND if PM |
523 | select AUTO_ZRELADDR | |
a1c0a6ad | 524 | select COMMON_CLK |
6d803ba7 | 525 | select CLKDEV_LOOKUP |
389d9b58 | 526 | select CLKSRC_PXA |
234b6ced | 527 | select CLKSRC_MMIO |
bb0eb050 | 528 | select TIMER_OF |
2f202861 | 529 | select CPU_XSCALE if !CPU_XSC3 |
981d0f39 | 530 | select GENERIC_CLOCKEVENTS |
4c301f9b | 531 | select GENERIC_IRQ_MULTI_HANDLER |
157d2644 | 532 | select GPIO_PXA |
5c34a4e8 | 533 | select GPIOLIB |
d0ee9f40 | 534 | select HAVE_IDE |
d6cf30ca | 535 | select IRQ_DOMAIN |
b1b3f49c RK |
536 | select PLAT_PXA |
537 | select SPARSE_IRQ | |
f999b8bd | 538 | help |
2c8086a5 | 539 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
540 | |
541 | config ARCH_RPC | |
542 | bool "RiscPC" | |
868e87cc | 543 | depends on MMU |
1da177e4 | 544 | select ARCH_ACORN |
a08b6b79 | 545 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 546 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 547 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 548 | select CPU_SA110 |
b1b3f49c | 549 | select FIQ |
d0ee9f40 | 550 | select HAVE_IDE |
b1b3f49c RK |
551 | select HAVE_PATA_PLATFORM |
552 | select ISA_DMA_API | |
c334bc15 | 553 | select NEED_MACH_IO_H |
0cdc8b92 | 554 | select NEED_MACH_MEMORY_H |
ce816fa8 | 555 | select NO_IOPORT_MAP |
1da177e4 LT |
556 | help |
557 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
558 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
559 | ||
560 | config ARCH_SA1100 | |
561 | bool "SA1100-based" | |
b1b3f49c | 562 | select ARCH_MTD_XIP |
b1b3f49c RK |
563 | select ARCH_SPARSEMEM_ENABLE |
564 | select CLKDEV_LOOKUP | |
565 | select CLKSRC_MMIO | |
389d9b58 | 566 | select CLKSRC_PXA |
bb0eb050 | 567 | select TIMER_OF if OF |
1937f5b9 | 568 | select CPU_FREQ |
b1b3f49c | 569 | select CPU_SA1100 |
3e238be2 | 570 | select GENERIC_CLOCKEVENTS |
4c301f9b | 571 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 572 | select GPIOLIB |
d0ee9f40 | 573 | select HAVE_IDE |
1eca42b4 | 574 | select IRQ_DOMAIN |
b1b3f49c | 575 | select ISA |
0cdc8b92 | 576 | select NEED_MACH_MEMORY_H |
375dec92 | 577 | select SPARSE_IRQ |
f999b8bd MM |
578 | help |
579 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 580 | |
b130d5c2 KK |
581 | config ARCH_S3C24XX |
582 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 583 | select ATAGS |
b1b3f49c | 584 | select CLKDEV_LOOKUP |
4280506a | 585 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 586 | select GENERIC_CLOCKEVENTS |
880cf071 | 587 | select GPIO_SAMSUNG |
5c34a4e8 | 588 | select GPIOLIB |
4c301f9b | 589 | select GENERIC_IRQ_MULTI_HANDLER |
20676c15 | 590 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 591 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 592 | select HAVE_S3C_RTC if RTC_CLASS |
c334bc15 | 593 | select NEED_MACH_IO_H |
cd8dc7ae | 594 | select SAMSUNG_ATAGS |
ea04d6b4 | 595 | select USE_OF |
1da177e4 | 596 | help |
b130d5c2 KK |
597 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
598 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
599 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
600 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 601 | |
7c6337e2 KH |
602 | config ARCH_DAVINCI |
603 | bool "TI DaVinci" | |
b1b3f49c | 604 | select ARCH_HAS_HOLES_MEMORYMODEL |
27823278 | 605 | select COMMON_CLK |
ce32c5c5 | 606 | select CPU_ARM926T |
20e9969b | 607 | select GENERIC_ALLOCATOR |
b1b3f49c | 608 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 609 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 610 | select GPIOLIB |
b1b3f49c | 611 | select HAVE_IDE |
27823278 DL |
612 | select PM_GENERIC_DOMAINS if PM |
613 | select PM_GENERIC_DOMAINS_OF if PM && OF | |
614 | select RESET_CONTROLLER | |
689e331f | 615 | select USE_OF |
b1b3f49c | 616 | select ZONE_DMA |
7c6337e2 KH |
617 | help |
618 | Support for TI's DaVinci platform. | |
619 | ||
a0694861 TL |
620 | config ARCH_OMAP1 |
621 | bool "TI OMAP1" | |
00a36698 | 622 | depends on MMU |
9af915da | 623 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 624 | select ARCH_OMAP |
b1b3f49c | 625 | select CLKDEV_LOOKUP |
d6e15d78 | 626 | select CLKSRC_MMIO |
b1b3f49c | 627 | select GENERIC_CLOCKEVENTS |
a0694861 | 628 | select GENERIC_IRQ_CHIP |
4c301f9b | 629 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 630 | select GPIOLIB |
a0694861 TL |
631 | select HAVE_IDE |
632 | select IRQ_DOMAIN | |
633 | select NEED_MACH_IO_H if PCCARD | |
634 | select NEED_MACH_MEMORY_H | |
685e2d08 | 635 | select SPARSE_IRQ |
21f47fbc | 636 | help |
a0694861 | 637 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 638 | |
1da177e4 LT |
639 | endchoice |
640 | ||
387798b3 RH |
641 | menu "Multiple platform selection" |
642 | depends on ARCH_MULTIPLATFORM | |
643 | ||
644 | comment "CPU Core family selection" | |
645 | ||
f8afae40 AB |
646 | config ARCH_MULTI_V4 |
647 | bool "ARMv4 based platforms (FA526)" | |
648 | depends on !ARCH_MULTI_V6_V7 | |
649 | select ARCH_MULTI_V4_V5 | |
650 | select CPU_FA526 | |
651 | ||
387798b3 RH |
652 | config ARCH_MULTI_V4T |
653 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 654 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 655 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
656 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
657 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
658 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
659 | |
660 | config ARCH_MULTI_V5 | |
661 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 662 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 663 | select ARCH_MULTI_V4_V5 |
12567bbd | 664 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
665 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
666 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
667 | |
668 | config ARCH_MULTI_V4_V5 | |
669 | bool | |
670 | ||
671 | config ARCH_MULTI_V6 | |
8dda05cc | 672 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 673 | select ARCH_MULTI_V6_V7 |
42f4754a | 674 | select CPU_V6K |
387798b3 RH |
675 | |
676 | config ARCH_MULTI_V7 | |
8dda05cc | 677 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
678 | default y |
679 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 680 | select CPU_V7 |
90bc8ac7 | 681 | select HAVE_SMP |
387798b3 RH |
682 | |
683 | config ARCH_MULTI_V6_V7 | |
684 | bool | |
9352b05b | 685 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
686 | |
687 | config ARCH_MULTI_CPU_AUTO | |
688 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
689 | select ARCH_MULTI_V5 | |
690 | ||
691 | endmenu | |
692 | ||
05e2a3de | 693 | config ARCH_VIRT |
e3246542 MY |
694 | bool "Dummy Virtual Machine" |
695 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 696 | select ARM_AMBA |
05e2a3de | 697 | select ARM_GIC |
3ee80364 | 698 | select ARM_GIC_V2M if PCI |
0b28f1db | 699 | select ARM_GIC_V3 |
bb29cecb | 700 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 701 | select ARM_PSCI |
4b8b5f25 | 702 | select HAVE_ARM_ARCH_TIMER |
8e2649d0 | 703 | select ARCH_SUPPORTS_BIG_ENDIAN |
05e2a3de | 704 | |
ccf50e23 RK |
705 | # |
706 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
707 | # Kconfigs may be included either alphabetically (according to the | |
708 | # plat- suffix) or along side the corresponding mach-* source. | |
709 | # | |
6bb8536c AF |
710 | source "arch/arm/mach-actions/Kconfig" |
711 | ||
445d9b30 TZ |
712 | source "arch/arm/mach-alpine/Kconfig" |
713 | ||
590b460c LP |
714 | source "arch/arm/mach-artpec/Kconfig" |
715 | ||
d9bfc86d OR |
716 | source "arch/arm/mach-asm9260/Kconfig" |
717 | ||
a66c51f9 AB |
718 | source "arch/arm/mach-aspeed/Kconfig" |
719 | ||
95b8f20f RK |
720 | source "arch/arm/mach-at91/Kconfig" |
721 | ||
1d22924e AB |
722 | source "arch/arm/mach-axxia/Kconfig" |
723 | ||
8ac49e04 CD |
724 | source "arch/arm/mach-bcm/Kconfig" |
725 | ||
1c37fa10 SH |
726 | source "arch/arm/mach-berlin/Kconfig" |
727 | ||
1da177e4 LT |
728 | source "arch/arm/mach-clps711x/Kconfig" |
729 | ||
d94f944e AV |
730 | source "arch/arm/mach-cns3xxx/Kconfig" |
731 | ||
95b8f20f RK |
732 | source "arch/arm/mach-davinci/Kconfig" |
733 | ||
df8d742e BS |
734 | source "arch/arm/mach-digicolor/Kconfig" |
735 | ||
95b8f20f RK |
736 | source "arch/arm/mach-dove/Kconfig" |
737 | ||
e7736d47 LB |
738 | source "arch/arm/mach-ep93xx/Kconfig" |
739 | ||
a66c51f9 AB |
740 | source "arch/arm/mach-exynos/Kconfig" |
741 | source "arch/arm/plat-samsung/Kconfig" | |
742 | ||
1da177e4 LT |
743 | source "arch/arm/mach-footbridge/Kconfig" |
744 | ||
59d3a193 PZ |
745 | source "arch/arm/mach-gemini/Kconfig" |
746 | ||
387798b3 RH |
747 | source "arch/arm/mach-highbank/Kconfig" |
748 | ||
389ee0c2 HZ |
749 | source "arch/arm/mach-hisi/Kconfig" |
750 | ||
a66c51f9 AB |
751 | source "arch/arm/mach-imx/Kconfig" |
752 | ||
1da177e4 LT |
753 | source "arch/arm/mach-integrator/Kconfig" |
754 | ||
a66c51f9 AB |
755 | source "arch/arm/mach-iop13xx/Kconfig" |
756 | ||
3f7e5815 LB |
757 | source "arch/arm/mach-iop32x/Kconfig" |
758 | ||
759 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 LT |
760 | |
761 | source "arch/arm/mach-ixp4xx/Kconfig" | |
762 | ||
828989ad SS |
763 | source "arch/arm/mach-keystone/Kconfig" |
764 | ||
95b8f20f RK |
765 | source "arch/arm/mach-ks8695/Kconfig" |
766 | ||
a66c51f9 AB |
767 | source "arch/arm/mach-mediatek/Kconfig" |
768 | ||
3b8f5030 CC |
769 | source "arch/arm/mach-meson/Kconfig" |
770 | ||
a66c51f9 | 771 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 772 | |
a66c51f9 | 773 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 774 | |
794d15b2 SS |
775 | source "arch/arm/mach-mv78xx0/Kconfig" |
776 | ||
a66c51f9 | 777 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 778 | |
1d3f33d5 SG |
779 | source "arch/arm/mach-mxs/Kconfig" |
780 | ||
95b8f20f | 781 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 782 | |
95b8f20f | 783 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 784 | |
7bffa14c BH |
785 | source "arch/arm/mach-npcm/Kconfig" |
786 | ||
9851ca57 DT |
787 | source "arch/arm/mach-nspire/Kconfig" |
788 | ||
d48af15e TL |
789 | source "arch/arm/plat-omap/Kconfig" |
790 | ||
791 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 792 | |
1dbae815 TL |
793 | source "arch/arm/mach-omap2/Kconfig" |
794 | ||
9dd0b194 | 795 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 796 | |
a66c51f9 AB |
797 | source "arch/arm/mach-oxnas/Kconfig" |
798 | ||
387798b3 RH |
799 | source "arch/arm/mach-picoxcell/Kconfig" |
800 | ||
a66c51f9 AB |
801 | source "arch/arm/mach-prima2/Kconfig" |
802 | ||
95b8f20f RK |
803 | source "arch/arm/mach-pxa/Kconfig" |
804 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 805 | |
8fc1b0f8 KG |
806 | source "arch/arm/mach-qcom/Kconfig" |
807 | ||
95b8f20f RK |
808 | source "arch/arm/mach-realview/Kconfig" |
809 | ||
d63dc051 HS |
810 | source "arch/arm/mach-rockchip/Kconfig" |
811 | ||
a66c51f9 AB |
812 | source "arch/arm/mach-s3c24xx/Kconfig" |
813 | ||
814 | source "arch/arm/mach-s3c64xx/Kconfig" | |
815 | ||
816 | source "arch/arm/mach-s5pv210/Kconfig" | |
817 | ||
95b8f20f | 818 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 819 | |
a66c51f9 AB |
820 | source "arch/arm/mach-shmobile/Kconfig" |
821 | ||
387798b3 RH |
822 | source "arch/arm/mach-socfpga/Kconfig" |
823 | ||
a7ed099f | 824 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 825 | |
65ebcc11 SK |
826 | source "arch/arm/mach-sti/Kconfig" |
827 | ||
bcb84fb4 AT |
828 | source "arch/arm/mach-stm32/Kconfig" |
829 | ||
3b52634f MR |
830 | source "arch/arm/mach-sunxi/Kconfig" |
831 | ||
d6de5b02 MG |
832 | source "arch/arm/mach-tango/Kconfig" |
833 | ||
c5f80065 EG |
834 | source "arch/arm/mach-tegra/Kconfig" |
835 | ||
95b8f20f | 836 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 837 | |
ba56a987 MY |
838 | source "arch/arm/mach-uniphier/Kconfig" |
839 | ||
95b8f20f | 840 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
841 | |
842 | source "arch/arm/mach-versatile/Kconfig" | |
843 | ||
ceade897 | 844 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 845 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 846 | |
6f35f9a9 TP |
847 | source "arch/arm/mach-vt8500/Kconfig" |
848 | ||
7ec80ddf | 849 | source "arch/arm/mach-w90x900/Kconfig" |
850 | ||
acede515 JN |
851 | source "arch/arm/mach-zx/Kconfig" |
852 | ||
9a45eb69 JC |
853 | source "arch/arm/mach-zynq/Kconfig" |
854 | ||
499f1640 SA |
855 | # ARMv7-M architecture |
856 | config ARCH_EFM32 | |
857 | bool "Energy Micro efm32" | |
858 | depends on ARM_SINGLE_ARMV7M | |
5c34a4e8 | 859 | select GPIOLIB |
499f1640 SA |
860 | help |
861 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
862 | processors. | |
863 | ||
864 | config ARCH_LPC18XX | |
865 | bool "NXP LPC18xx/LPC43xx" | |
866 | depends on ARM_SINGLE_ARMV7M | |
867 | select ARCH_HAS_RESET_CONTROLLER | |
868 | select ARM_AMBA | |
869 | select CLKSRC_LPC32XX | |
870 | select PINCTRL | |
871 | help | |
872 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
873 | high performance microcontrollers. | |
874 | ||
1847119d | 875 | config ARCH_MPS2 |
17bd274e | 876 | bool "ARM MPS2 platform" |
1847119d VM |
877 | depends on ARM_SINGLE_ARMV7M |
878 | select ARM_AMBA | |
879 | select CLKSRC_MPS2 | |
880 | help | |
881 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
882 | with a range of available cores like Cortex-M3/M4/M7. | |
883 | ||
884 | Please, note that depends which Application Note is used memory map | |
885 | for the platform may vary, so adjustment of RAM base might be needed. | |
886 | ||
1da177e4 LT |
887 | # Definitions to make life easier |
888 | config ARCH_ACORN | |
889 | bool | |
890 | ||
7ae1f7ec LB |
891 | config PLAT_IOP |
892 | bool | |
469d3044 | 893 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 894 | |
69b02f6a LB |
895 | config PLAT_ORION |
896 | bool | |
bfe45e0b | 897 | select CLKSRC_MMIO |
b1b3f49c | 898 | select COMMON_CLK |
dc7ad3b3 | 899 | select GENERIC_IRQ_CHIP |
278b45b0 | 900 | select IRQ_DOMAIN |
69b02f6a | 901 | |
abcda1dc TP |
902 | config PLAT_ORION_LEGACY |
903 | bool | |
904 | select PLAT_ORION | |
905 | ||
bd5ce433 EM |
906 | config PLAT_PXA |
907 | bool | |
908 | ||
f4b8b319 RK |
909 | config PLAT_VERSATILE |
910 | bool | |
911 | ||
d9a1beaa AC |
912 | source "arch/arm/firmware/Kconfig" |
913 | ||
1da177e4 LT |
914 | source arch/arm/mm/Kconfig |
915 | ||
afe4b25e | 916 | config IWMMXT |
d93003e8 SH |
917 | bool "Enable iWMMXt support" |
918 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
919 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
920 | help |
921 | Enable support for iWMMXt context switching at run time if | |
922 | running on a CPU that supports it. | |
923 | ||
3b93e7b0 HC |
924 | if !MMU |
925 | source "arch/arm/Kconfig-nommu" | |
926 | endif | |
927 | ||
3e0a07f8 GC |
928 | config PJ4B_ERRATA_4742 |
929 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
930 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
931 | default y | |
932 | help | |
933 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
934 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
935 | the retiring WFI/WFE instructions and the newly issued subsequent | |
936 | instructions. This sensitivity can result in a CPU hang scenario. | |
937 | Workaround: | |
938 | The software must insert either a Data Synchronization Barrier (DSB) | |
939 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
940 | instruction | |
941 | ||
f0c4b8d6 WD |
942 | config ARM_ERRATA_326103 |
943 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
944 | depends on CPU_V6 | |
945 | help | |
946 | Executing a SWP instruction to read-only memory does not set bit 11 | |
947 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
948 | treat the access as a read, preventing a COW from occurring and | |
949 | causing the faulting task to livelock. | |
950 | ||
9cba3ccc CM |
951 | config ARM_ERRATA_411920 |
952 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 953 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
954 | help |
955 | Invalidation of the Instruction Cache operation can | |
956 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
957 | It does not affect the MPCore. This option enables the ARM Ltd. | |
958 | recommended workaround. | |
959 | ||
7ce236fc CM |
960 | config ARM_ERRATA_430973 |
961 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
962 | depends on CPU_V7 | |
963 | help | |
964 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 965 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
966 | interworking branch is replaced with another code sequence at the |
967 | same virtual address, whether due to self-modifying code or virtual | |
968 | to physical address re-mapping, Cortex-A8 does not recover from the | |
969 | stale interworking branch prediction. This results in Cortex-A8 | |
970 | executing the new code sequence in the incorrect ARM or Thumb state. | |
971 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
972 | and also flushes the branch target cache at every context switch. | |
973 | Note that setting specific bits in the ACTLR register may not be | |
974 | available in non-secure mode. | |
975 | ||
855c551f CM |
976 | config ARM_ERRATA_458693 |
977 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
978 | depends on CPU_V7 | |
62e4d357 | 979 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
980 | help |
981 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
982 | erratum. For very specific sequences of memory operations, it is | |
983 | possible for a hazard condition intended for a cache line to instead | |
984 | be incorrectly associated with a different cache line. This false | |
985 | hazard might then cause a processor deadlock. The workaround enables | |
986 | the L1 caching of the NEON accesses and disables the PLD instruction | |
987 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
988 | register may not be available in non-secure mode. | |
989 | ||
0516e464 CM |
990 | config ARM_ERRATA_460075 |
991 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
992 | depends on CPU_V7 | |
62e4d357 | 993 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
994 | help |
995 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
996 | erratum. Any asynchronous access to the L2 cache may encounter a | |
997 | situation in which recent store transactions to the L2 cache are lost | |
998 | and overwritten with stale memory contents from external memory. The | |
999 | workaround disables the write-allocate mode for the L2 cache via the | |
1000 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1001 | may not be available in non-secure mode. | |
1002 | ||
9f05027c WD |
1003 | config ARM_ERRATA_742230 |
1004 | bool "ARM errata: DMB operation may be faulty" | |
1005 | depends on CPU_V7 && SMP | |
62e4d357 | 1006 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1007 | help |
1008 | This option enables the workaround for the 742230 Cortex-A9 | |
1009 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1010 | between two write operations may not ensure the correct visibility | |
1011 | ordering of the two writes. This workaround sets a specific bit in | |
1012 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1013 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1014 | the two writes. | |
1015 | ||
a672e99b WD |
1016 | config ARM_ERRATA_742231 |
1017 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1018 | depends on CPU_V7 && SMP | |
62e4d357 | 1019 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1020 | help |
1021 | This option enables the workaround for the 742231 Cortex-A9 | |
1022 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1023 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1024 | accessing some data located in the same cache line, may get corrupted | |
1025 | data due to bad handling of the address hazard when the line gets | |
1026 | replaced from one of the CPUs at the same time as another CPU is | |
1027 | accessing it. This workaround sets specific bits in the diagnostic | |
1028 | register of the Cortex-A9 which reduces the linefill issuing | |
1029 | capabilities of the processor. | |
1030 | ||
69155794 JM |
1031 | config ARM_ERRATA_643719 |
1032 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1033 | depends on CPU_V7 && SMP | |
e5a5de44 | 1034 | default y |
69155794 JM |
1035 | help |
1036 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1037 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1038 | register returns zero when it should return one. The workaround | |
1039 | corrects this value, ensuring cache maintenance operations which use | |
1040 | it behave as intended and avoiding data corruption. | |
1041 | ||
cdf357f1 WD |
1042 | config ARM_ERRATA_720789 |
1043 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1044 | depends on CPU_V7 |
cdf357f1 WD |
1045 | help |
1046 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1047 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1048 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1049 | As a consequence of this erratum, some TLB entries which should be | |
1050 | invalidated are not, resulting in an incoherency in the system page | |
1051 | tables. The workaround changes the TLB flushing routines to invalidate | |
1052 | entries regardless of the ASID. | |
475d92fc WD |
1053 | |
1054 | config ARM_ERRATA_743622 | |
1055 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1056 | depends on CPU_V7 | |
62e4d357 | 1057 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1058 | help |
1059 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1060 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1061 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1062 | corruption. This workaround sets a specific bit in the diagnostic | |
1063 | register of the Cortex-A9 which disables the Store Buffer | |
1064 | optimisation, preventing the defect from occurring. This has no | |
1065 | visible impact on the overall performance or power consumption of the | |
1066 | processor. | |
1067 | ||
9a27c27c WD |
1068 | config ARM_ERRATA_751472 |
1069 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1070 | depends on CPU_V7 |
62e4d357 | 1071 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1072 | help |
1073 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1074 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1075 | completion of a following broadcasted operation if the second | |
1076 | operation is received by a CPU before the ICIALLUIS has completed, | |
1077 | potentially leading to corrupted entries in the cache or TLB. | |
1078 | ||
fcbdc5fe WD |
1079 | config ARM_ERRATA_754322 |
1080 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1081 | depends on CPU_V7 | |
1082 | help | |
1083 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1084 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1085 | which starts prior to an ASID switch but completes afterwards. This | |
1086 | can populate the micro-TLB with a stale entry which may be hit with | |
1087 | the new ASID. This workaround places two dsb instructions in the mm | |
1088 | switching code so that no page table walks can cross the ASID switch. | |
1089 | ||
5dab26af WD |
1090 | config ARM_ERRATA_754327 |
1091 | bool "ARM errata: no automatic Store Buffer drain" | |
1092 | depends on CPU_V7 && SMP | |
1093 | help | |
1094 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1095 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1096 | mechanism and therefore a livelock may occur if an external agent | |
1097 | continuously polls a memory location waiting to observe an update. | |
1098 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1099 | written polling loops from denying visibility of updates to memory. | |
1100 | ||
145e10e1 CM |
1101 | config ARM_ERRATA_364296 |
1102 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1103 | depends on CPU_V6 |
145e10e1 CM |
1104 | help |
1105 | This options enables the workaround for the 364296 ARM1136 | |
1106 | r0p2 erratum (possible cache data corruption with | |
1107 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1108 | the auxiliary control register and the FI bit in the control | |
1109 | register, thus disabling hit-under-miss without putting the | |
1110 | processor into full low interrupt latency mode. ARM11MPCore | |
1111 | is not affected. | |
1112 | ||
f630c1bd WD |
1113 | config ARM_ERRATA_764369 |
1114 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1115 | depends on CPU_V7 && SMP | |
1116 | help | |
1117 | This option enables the workaround for erratum 764369 | |
1118 | affecting Cortex-A9 MPCore with two or more processors (all | |
1119 | current revisions). Under certain timing circumstances, a data | |
1120 | cache line maintenance operation by MVA targeting an Inner | |
1121 | Shareable memory region may fail to proceed up to either the | |
1122 | Point of Coherency or to the Point of Unification of the | |
1123 | system. This workaround adds a DSB instruction before the | |
1124 | relevant cache maintenance functions and sets a specific bit | |
1125 | in the diagnostic control register of the SCU. | |
1126 | ||
7253b85c SH |
1127 | config ARM_ERRATA_775420 |
1128 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1129 | depends on CPU_V7 | |
1130 | help | |
1131 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1132 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1133 | operation aborts with MMU exception, it might cause the processor | |
1134 | to deadlock. This workaround puts DSB before executing ISB if | |
1135 | an abort may occur on cache maintenance. | |
1136 | ||
93dc6887 CM |
1137 | config ARM_ERRATA_798181 |
1138 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1139 | depends on CPU_V7 && SMP | |
1140 | help | |
1141 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1142 | adequately shooting down all use of the old entries. This | |
1143 | option enables the Linux kernel workaround for this erratum | |
1144 | which sends an IPI to the CPUs that are running the same ASID | |
1145 | as the one being invalidated. | |
1146 | ||
84b6504f WD |
1147 | config ARM_ERRATA_773022 |
1148 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1149 | depends on CPU_V7 | |
1150 | help | |
1151 | This option enables the workaround for the 773022 Cortex-A15 | |
1152 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1153 | loop buffer may deliver incorrect instructions. This | |
1154 | workaround disables the loop buffer to avoid the erratum. | |
1155 | ||
62c0f4a5 DA |
1156 | config ARM_ERRATA_818325_852422 |
1157 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1158 | depends on CPU_V7 | |
1159 | help | |
1160 | This option enables the workaround for: | |
1161 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1162 | instruction might deadlock. Fixed in r0p1. | |
1163 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1164 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1165 | any Cortex-A12 cores yet. | |
1166 | This workaround for all both errata involves setting bit[12] of the | |
1167 | Feature Register. This bit disables an optimisation applied to a | |
1168 | sequence of 2 instructions that use opposing condition codes. | |
1169 | ||
416bcf21 DA |
1170 | config ARM_ERRATA_821420 |
1171 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1172 | depends on CPU_V7 | |
1173 | help | |
1174 | This option enables the workaround for the 821420 Cortex-A12 | |
1175 | (all revs) erratum. In very rare timing conditions, a sequence | |
1176 | of VMOV to Core registers instructions, for which the second | |
1177 | one is in the shadow of a branch or abort, can lead to a | |
1178 | deadlock when the VMOV instructions are issued out-of-order. | |
1179 | ||
9f6f9354 DA |
1180 | config ARM_ERRATA_825619 |
1181 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1182 | depends on CPU_V7 | |
1183 | help | |
1184 | This option enables the workaround for the 825619 Cortex-A12 | |
1185 | (all revs) erratum. Within rare timing constraints, executing a | |
1186 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1187 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1188 | ||
1189 | config ARM_ERRATA_852421 | |
1190 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1191 | depends on CPU_V7 | |
1192 | help | |
1193 | This option enables the workaround for the 852421 Cortex-A17 | |
1194 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1195 | execution of a DMB ST instruction might fail to properly order | |
1196 | stores from GroupA and stores from GroupB. | |
1197 | ||
62c0f4a5 DA |
1198 | config ARM_ERRATA_852423 |
1199 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1200 | depends on CPU_V7 | |
1201 | help | |
1202 | This option enables the workaround for: | |
1203 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1204 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1205 | any Cortex-A17 cores yet. | |
1206 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1207 | config option from the A12 erratum due to the way errata are checked | |
1208 | for and handled. | |
1209 | ||
1da177e4 LT |
1210 | endmenu |
1211 | ||
1212 | source "arch/arm/common/Kconfig" | |
1213 | ||
1da177e4 LT |
1214 | menu "Bus support" |
1215 | ||
1da177e4 LT |
1216 | config ISA |
1217 | bool | |
1da177e4 LT |
1218 | help |
1219 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1220 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1221 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1222 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1223 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1224 | ||
065909b9 | 1225 | # Select ISA DMA controller support |
1da177e4 LT |
1226 | config ISA_DMA |
1227 | bool | |
065909b9 | 1228 | select ISA_DMA_API |
1da177e4 | 1229 | |
065909b9 | 1230 | # Select ISA DMA interface |
5cae841b AV |
1231 | config ISA_DMA_API |
1232 | bool | |
5cae841b | 1233 | |
1da177e4 | 1234 | config PCI |
0b05da72 | 1235 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1236 | help |
1237 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1238 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1239 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1240 | VESA. If you have PCI, say Y, otherwise N. | |
1241 | ||
52882173 | 1242 | config PCI_DOMAINS |
925d3166 | 1243 | bool "Support for multiple PCI domains" |
52882173 | 1244 | depends on PCI |
925d3166 LP |
1245 | help |
1246 | Enable PCI domains kernel management. Say Y if your machine | |
1247 | has a PCI bus hierarchy that requires more than one PCI | |
1248 | domain (aka segment) to be correctly managed. Say N otherwise. | |
1249 | ||
1250 | If you don't know what to do here, say N. | |
52882173 | 1251 | |
8c7d1474 LP |
1252 | config PCI_DOMAINS_GENERIC |
1253 | def_bool PCI_DOMAINS | |
1254 | ||
b080ac8a MRJ |
1255 | config PCI_NANOENGINE |
1256 | bool "BSE nanoEngine PCI support" | |
1257 | depends on SA1100_NANOENGINE | |
1258 | help | |
1259 | Enable PCI on the BSE nanoEngine board. | |
1260 | ||
36e23590 MW |
1261 | config PCI_SYSCALL |
1262 | def_bool PCI | |
1263 | ||
a0113a99 MR |
1264 | config PCI_HOST_ITE8152 |
1265 | bool | |
1266 | depends on PCI && MACH_ARMCORE | |
1267 | default y | |
1268 | select DMABOUNCE | |
1269 | ||
1da177e4 LT |
1270 | source "drivers/pci/Kconfig" |
1271 | ||
1272 | source "drivers/pcmcia/Kconfig" | |
1273 | ||
1274 | endmenu | |
1275 | ||
1276 | menu "Kernel Features" | |
1277 | ||
3b55658a DM |
1278 | config HAVE_SMP |
1279 | bool | |
1280 | help | |
1281 | This option should be selected by machines which have an SMP- | |
1282 | capable CPU. | |
1283 | ||
1284 | The only effect of this option is to make the SMP-related | |
1285 | options available to the user for configuration. | |
1286 | ||
1da177e4 | 1287 | config SMP |
bb2d8130 | 1288 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1289 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1290 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1291 | depends on HAVE_SMP |
801bb21c | 1292 | depends on MMU || ARM_MPU |
0361748f | 1293 | select IRQ_WORK |
1da177e4 LT |
1294 | help |
1295 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1296 | a system with only one CPU, say N. If you have a system with more |
1297 | than one CPU, say Y. | |
1da177e4 | 1298 | |
4a474157 | 1299 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1300 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1301 | you say Y here, the kernel will run on many, but not all, |
1302 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1303 | will run faster if you say N here. | |
1da177e4 | 1304 | |
395cf969 | 1305 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
ecf38679 | 1306 | <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at |
50a23e6e | 1307 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1308 | |
1309 | If you don't know what to do here, say N. | |
1310 | ||
f00ec48f | 1311 | config SMP_ON_UP |
5744ff43 | 1312 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1313 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1314 | default y |
1315 | help | |
1316 | SMP kernels contain instructions which fail on non-SMP processors. | |
1317 | Enabling this option allows the kernel to modify itself to make | |
1318 | these instructions safe. Disabling it allows about 1K of space | |
1319 | savings. | |
1320 | ||
1321 | If you don't know what to do here, say Y. | |
1322 | ||
c9018aab VG |
1323 | config ARM_CPU_TOPOLOGY |
1324 | bool "Support cpu topology definition" | |
1325 | depends on SMP && CPU_V7 | |
1326 | default y | |
1327 | help | |
1328 | Support ARM cpu topology definition. The MPIDR register defines | |
1329 | affinity between processors which is then used to describe the cpu | |
1330 | topology of an ARM System. | |
1331 | ||
1332 | config SCHED_MC | |
1333 | bool "Multi-core scheduler support" | |
1334 | depends on ARM_CPU_TOPOLOGY | |
1335 | help | |
1336 | Multi-core scheduler support improves the CPU scheduler's decision | |
1337 | making when dealing with multi-core CPU chips at a cost of slightly | |
1338 | increased overhead in some places. If unsure say N here. | |
1339 | ||
1340 | config SCHED_SMT | |
1341 | bool "SMT scheduler support" | |
1342 | depends on ARM_CPU_TOPOLOGY | |
1343 | help | |
1344 | Improves the CPU scheduler's decision making when dealing with | |
1345 | MultiThreading at a cost of slightly increased overhead in some | |
1346 | places. If unsure say N here. | |
1347 | ||
a8cbcd92 RK |
1348 | config HAVE_ARM_SCU |
1349 | bool | |
a8cbcd92 RK |
1350 | help |
1351 | This option enables support for the ARM system coherency unit | |
1352 | ||
8a4da6e3 | 1353 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1354 | bool "Architected timer support" |
1355 | depends on CPU_V7 | |
8a4da6e3 | 1356 | select ARM_ARCH_TIMER |
0c403462 | 1357 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1358 | help |
1359 | This option enables support for the ARM architected timer | |
1360 | ||
f32f4ce2 RK |
1361 | config HAVE_ARM_TWD |
1362 | bool | |
bb0eb050 | 1363 | select TIMER_OF if OF |
f32f4ce2 RK |
1364 | help |
1365 | This options enables support for the ARM timer and watchdog unit | |
1366 | ||
e8db288e NP |
1367 | config MCPM |
1368 | bool "Multi-Cluster Power Management" | |
1369 | depends on CPU_V7 && SMP | |
1370 | help | |
1371 | This option provides the common power management infrastructure | |
1372 | for (multi-)cluster based systems, such as big.LITTLE based | |
1373 | systems. | |
1374 | ||
ebf4a5c5 HZ |
1375 | config MCPM_QUAD_CLUSTER |
1376 | bool | |
1377 | depends on MCPM | |
1378 | help | |
1379 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1380 | to 2 clusters by default. | |
1381 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1382 | option to allow the additional clusters to be managed. | |
1383 | ||
1c33be57 NP |
1384 | config BIG_LITTLE |
1385 | bool "big.LITTLE support (Experimental)" | |
1386 | depends on CPU_V7 && SMP | |
1387 | select MCPM | |
1388 | help | |
1389 | This option enables support selections for the big.LITTLE | |
1390 | system architecture. | |
1391 | ||
1392 | config BL_SWITCHER | |
1393 | bool "big.LITTLE switcher support" | |
6c044fec | 1394 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1395 | select CPU_PM |
1c33be57 NP |
1396 | help |
1397 | The big.LITTLE "switcher" provides the core functionality to | |
1398 | transparently handle transition between a cluster of A15's | |
1399 | and a cluster of A7's in a big.LITTLE system. | |
1400 | ||
b22537c6 NP |
1401 | config BL_SWITCHER_DUMMY_IF |
1402 | tristate "Simple big.LITTLE switcher user interface" | |
1403 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1404 | help | |
1405 | This is a simple and dummy char dev interface to control | |
1406 | the big.LITTLE switcher core code. It is meant for | |
1407 | debugging purposes only. | |
1408 | ||
8d5796d2 LB |
1409 | choice |
1410 | prompt "Memory split" | |
006fa259 | 1411 | depends on MMU |
8d5796d2 LB |
1412 | default VMSPLIT_3G |
1413 | help | |
1414 | Select the desired split between kernel and user memory. | |
1415 | ||
1416 | If you are not absolutely sure what you are doing, leave this | |
1417 | option alone! | |
1418 | ||
1419 | config VMSPLIT_3G | |
1420 | bool "3G/1G user/kernel split" | |
63ce446c | 1421 | config VMSPLIT_3G_OPT |
bbeedfda | 1422 | depends on !ARM_LPAE |
63ce446c | 1423 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1424 | config VMSPLIT_2G |
1425 | bool "2G/2G user/kernel split" | |
1426 | config VMSPLIT_1G | |
1427 | bool "1G/3G user/kernel split" | |
1428 | endchoice | |
1429 | ||
1430 | config PAGE_OFFSET | |
1431 | hex | |
006fa259 | 1432 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1433 | default 0x40000000 if VMSPLIT_1G |
1434 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1435 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1436 | default 0xC0000000 |
1437 | ||
1da177e4 LT |
1438 | config NR_CPUS |
1439 | int "Maximum number of CPUs (2-32)" | |
1440 | range 2 32 | |
1441 | depends on SMP | |
1442 | default "4" | |
1443 | ||
a054a811 | 1444 | config HOTPLUG_CPU |
00b7dede | 1445 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1446 | depends on SMP |
a054a811 RK |
1447 | help |
1448 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1449 | can be controlled through /sys/devices/system/cpu. | |
1450 | ||
2bdd424f WD |
1451 | config ARM_PSCI |
1452 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1453 | depends on HAVE_ARM_SMCCC |
be120397 | 1454 | select ARM_PSCI_FW |
2bdd424f WD |
1455 | help |
1456 | Say Y here if you want Linux to communicate with system firmware | |
1457 | implementing the PSCI specification for CPU-centric power | |
1458 | management operations described in ARM document number ARM DEN | |
1459 | 0022A ("Power State Coordination Interface System Software on | |
1460 | ARM processors"). | |
1461 | ||
2a6ad871 MR |
1462 | # The GPIO number here must be sorted by descending number. In case of |
1463 | # a multiplatform kernel, we just want the highest value required by the | |
1464 | # selected platforms. | |
44986ab0 PDSN |
1465 | config ARCH_NR_GPIO |
1466 | int | |
139358be | 1467 | default 2048 if ARCH_SOCFPGA |
d9be9ceb | 1468 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
b35d2e56 | 1469 | ARCH_ZYNQ |
aa42587a TF |
1470 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1471 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1472 | default 416 if ARCH_SUNXI |
06b851e5 | 1473 | default 392 if ARCH_U8500 |
01bb914c | 1474 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1475 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1476 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1477 | default 0 |
1478 | help | |
1479 | Maximum number of GPIOs in the system. | |
1480 | ||
1481 | If unsure, leave the default value. | |
1482 | ||
c9218b16 | 1483 | config HZ_FIXED |
f8065813 | 1484 | int |
da6b21e9 | 1485 | default 200 if ARCH_EBSA110 |
1164f672 | 1486 | default 128 if SOC_AT91RM9200 |
47d84682 | 1487 | default 0 |
c9218b16 RK |
1488 | |
1489 | choice | |
47d84682 | 1490 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1491 | prompt "Timer frequency" |
1492 | ||
1493 | config HZ_100 | |
1494 | bool "100 Hz" | |
1495 | ||
1496 | config HZ_200 | |
1497 | bool "200 Hz" | |
1498 | ||
1499 | config HZ_250 | |
1500 | bool "250 Hz" | |
1501 | ||
1502 | config HZ_300 | |
1503 | bool "300 Hz" | |
1504 | ||
1505 | config HZ_500 | |
1506 | bool "500 Hz" | |
1507 | ||
1508 | config HZ_1000 | |
1509 | bool "1000 Hz" | |
1510 | ||
1511 | endchoice | |
1512 | ||
1513 | config HZ | |
1514 | int | |
47d84682 | 1515 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1516 | default 100 if HZ_100 |
1517 | default 200 if HZ_200 | |
1518 | default 250 if HZ_250 | |
1519 | default 300 if HZ_300 | |
1520 | default 500 if HZ_500 | |
1521 | default 1000 | |
1522 | ||
1523 | config SCHED_HRTICK | |
1524 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1525 | |
16c79651 | 1526 | config THUMB2_KERNEL |
bc7dea00 | 1527 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1528 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1529 | default y if CPU_THUMBONLY |
89bace65 | 1530 | select ARM_UNWIND |
16c79651 CM |
1531 | help |
1532 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1533 | Thumb-2 mode. |
16c79651 CM |
1534 | |
1535 | If unsure, say N. | |
1536 | ||
6f685c5c DM |
1537 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1538 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1539 | depends on THUMB2_KERNEL && MODULES | |
1540 | default y | |
1541 | help | |
1542 | Various binutils versions can resolve Thumb-2 branches to | |
1543 | locally-defined, preemptible global symbols as short-range "b.n" | |
1544 | branch instructions. | |
1545 | ||
1546 | This is a problem, because there's no guarantee the final | |
1547 | destination of the symbol, or any candidate locations for a | |
1548 | trampoline, are within range of the branch. For this reason, the | |
1549 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1550 | relocation in modules at all, and it makes little sense to add | |
1551 | support. | |
1552 | ||
1553 | The symptom is that the kernel fails with an "unsupported | |
1554 | relocation" error when loading some modules. | |
1555 | ||
1556 | Until fixed tools are available, passing | |
1557 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1558 | code which hits this problem, at the cost of a bit of extra runtime | |
1559 | stack usage in some cases. | |
1560 | ||
1561 | The problem is described in more detail at: | |
1562 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1563 | ||
1564 | Only Thumb-2 kernels are affected. | |
1565 | ||
1566 | Unless you are sure your tools don't have this problem, say Y. | |
1567 | ||
42f25bdd NP |
1568 | config ARM_PATCH_IDIV |
1569 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1570 | depends on CPU_32v7 && !XIP_KERNEL | |
1571 | default y | |
1572 | help | |
1573 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1574 | __aeabi_uidiv() when it needs to perform division on signed | |
1575 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1576 | and udiv instructions that can be used to implement those | |
1577 | functions. | |
1578 | ||
1579 | Enabling this option allows the kernel to modify itself to | |
1580 | replace the first two instructions of these library functions | |
1581 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1582 | it is running on supports them. Typically this will be faster | |
1583 | and less power intensive than running the original library | |
1584 | code to do integer division. | |
1585 | ||
704bdda0 | 1586 | config AEABI |
49460970 RK |
1587 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K |
1588 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K | |
704bdda0 NP |
1589 | help |
1590 | This option allows for the kernel to be compiled using the latest | |
1591 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1592 | space environment that is also compiled with EABI. | |
1593 | ||
1594 | Since there are major incompatibilities between the legacy ABI and | |
1595 | EABI, especially with regard to structure member alignment, this | |
1596 | option also changes the kernel syscall calling convention to | |
1597 | disambiguate both ABIs and allow for backward compatibility support | |
1598 | (selected with CONFIG_OABI_COMPAT). | |
1599 | ||
1600 | To use this you need GCC version 4.0.0 or later. | |
1601 | ||
6c90c872 | 1602 | config OABI_COMPAT |
a73a3ff1 | 1603 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1604 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1605 | help |
1606 | This option preserves the old syscall interface along with the | |
1607 | new (ARM EABI) one. It also provides a compatibility layer to | |
1608 | intercept syscalls that have structure arguments which layout | |
1609 | in memory differs between the legacy ABI and the new ARM EABI | |
1610 | (only for non "thumb" binaries). This option adds a tiny | |
1611 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1612 | |
1613 | The seccomp filter system will not be available when this is | |
1614 | selected, since there is no way yet to sensibly distinguish | |
1615 | between calling conventions during filtering. | |
1616 | ||
6c90c872 NP |
1617 | If you know you'll be using only pure EABI user space then you |
1618 | can say N here. If this option is not selected and you attempt | |
1619 | to execute a legacy ABI binary then the result will be | |
1620 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1621 | at all). If in doubt say N. |
6c90c872 | 1622 | |
eb33575c | 1623 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1624 | bool |
e80d6a24 | 1625 | |
05944d74 RK |
1626 | config ARCH_SPARSEMEM_ENABLE |
1627 | bool | |
1628 | ||
07a2f737 RK |
1629 | config ARCH_SPARSEMEM_DEFAULT |
1630 | def_bool ARCH_SPARSEMEM_ENABLE | |
1631 | ||
05944d74 | 1632 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1633 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1634 | |
7b7bf499 WD |
1635 | config HAVE_ARCH_PFN_VALID |
1636 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1637 | ||
e585513b | 1638 | config HAVE_GENERIC_GUP |
b8cd51af SC |
1639 | def_bool y |
1640 | depends on ARM_LPAE | |
1641 | ||
053a96ca | 1642 | config HIGHMEM |
e8db89a2 RK |
1643 | bool "High Memory Support" |
1644 | depends on MMU | |
053a96ca NP |
1645 | help |
1646 | The address space of ARM processors is only 4 Gigabytes large | |
1647 | and it has to accommodate user address space, kernel address | |
1648 | space as well as some memory mapped IO. That means that, if you | |
1649 | have a large amount of physical memory and/or IO, not all of the | |
1650 | memory can be "permanently mapped" by the kernel. The physical | |
1651 | memory that is not permanently mapped is called "high memory". | |
1652 | ||
1653 | Depending on the selected kernel/user memory split, minimum | |
1654 | vmalloc space and actual amount of RAM, you may not need this | |
1655 | option which should result in a slightly faster kernel. | |
1656 | ||
1657 | If unsure, say n. | |
1658 | ||
65cec8e3 | 1659 | config HIGHPTE |
9a431bd5 | 1660 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1661 | depends on HIGHMEM |
9a431bd5 | 1662 | default y |
b4d103d1 RK |
1663 | help |
1664 | The VM uses one page of physical memory for each page table. | |
1665 | For systems with a lot of processes, this can use a lot of | |
1666 | precious low memory, eventually leading to low memory being | |
1667 | consumed by page tables. Setting this option will allow | |
1668 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1669 | |
a5e090ac RK |
1670 | config CPU_SW_DOMAIN_PAN |
1671 | bool "Enable use of CPU domains to implement privileged no-access" | |
1672 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1673 | default y |
1674 | help | |
a5e090ac RK |
1675 | Increase kernel security by ensuring that normal kernel accesses |
1676 | are unable to access userspace addresses. This can help prevent | |
1677 | use-after-free bugs becoming an exploitable privilege escalation | |
1678 | by ensuring that magic values (such as LIST_POISON) will always | |
1679 | fault when dereferenced. | |
1680 | ||
1681 | CPUs with low-vector mappings use a best-efforts implementation. | |
1682 | Their lower 1MB needs to remain accessible for the vectors, but | |
1683 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1684 | |
1b8873a0 | 1685 | config HW_PERF_EVENTS |
fa8ad788 MR |
1686 | def_bool y |
1687 | depends on ARM_PMU | |
1b8873a0 | 1688 | |
1355e2a6 CM |
1689 | config SYS_SUPPORTS_HUGETLBFS |
1690 | def_bool y | |
1691 | depends on ARM_LPAE | |
1692 | ||
8d962507 CM |
1693 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1694 | def_bool y | |
1695 | depends on ARM_LPAE | |
1696 | ||
4bfab203 SC |
1697 | config ARCH_WANT_GENERAL_HUGETLB |
1698 | def_bool y | |
1699 | ||
7d485f64 AB |
1700 | config ARM_MODULE_PLTS |
1701 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1702 | depends on MODULES | |
e7229f7d | 1703 | default y |
7d485f64 AB |
1704 | help |
1705 | Allocate PLTs when loading modules so that jumps and calls whose | |
1706 | targets are too far away for their relative offsets to be encoded | |
1707 | in the instructions themselves can be bounced via veneers in the | |
1708 | module's PLT. This allows modules to be allocated in the generic | |
1709 | vmalloc area after the dedicated module memory area has been | |
1710 | exhausted. The modules will use slightly more memory, but after | |
1711 | rounding up to page size, the actual memory footprint is usually | |
1712 | the same. | |
1713 | ||
e7229f7d AR |
1714 | Disabling this is usually safe for small single-platform |
1715 | configurations. If unsure, say y. | |
7d485f64 | 1716 | |
c1b2d970 | 1717 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1718 | int "Maximum zone order" |
898f08e1 | 1719 | default "12" if SOC_AM33XX |
6d85e2b0 | 1720 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1721 | default "11" |
1722 | help | |
1723 | The kernel memory allocator divides physically contiguous memory | |
1724 | blocks into "zones", where each zone is a power of two number of | |
1725 | pages. This option selects the largest power of two that the kernel | |
1726 | keeps in the memory allocator. If you need to allocate very large | |
1727 | blocks of physically contiguous memory, then you may need to | |
1728 | increase this value. | |
1729 | ||
1730 | This config option is actually maximum order plus one. For example, | |
1731 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1732 | ||
1da177e4 LT |
1733 | config ALIGNMENT_TRAP |
1734 | bool | |
f12d0d7c | 1735 | depends on CPU_CP15_MMU |
1da177e4 | 1736 | default y if !ARCH_EBSA110 |
e119bfff | 1737 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1738 | help |
84eb8d06 | 1739 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1740 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1741 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1742 | fetch/store instructions will be emulated in software if you say | |
1743 | here, which has a severe performance impact. This is necessary for | |
1744 | correct operation of some network protocols. With an IP-only | |
1745 | configuration it is safe to say N, otherwise say Y. | |
1746 | ||
39ec58f3 | 1747 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1748 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1749 | depends on MMU | |
39ec58f3 LB |
1750 | default y if CPU_FEROCEON |
1751 | help | |
1752 | Implement faster copy_to_user and clear_user methods for CPU | |
1753 | cores where a 8-word STM instruction give significantly higher | |
1754 | memory write throughput than a sequence of individual 32bit stores. | |
1755 | ||
1756 | A possible side effect is a slight increase in scheduling latency | |
1757 | between threads sharing the same address space if they invoke | |
1758 | such copy operations with large buffers. | |
1759 | ||
1760 | However, if the CPU data cache is using a write-allocate mode, | |
1761 | this option is unlikely to provide any performance gain. | |
1762 | ||
70c70d97 NP |
1763 | config SECCOMP |
1764 | bool | |
1765 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1766 | ---help--- | |
1767 | This kernel feature is useful for number crunching applications | |
1768 | that may need to compute untrusted bytecode during their | |
1769 | execution. By using pipes or other transports made available to | |
1770 | the process as file descriptors supporting the read/write | |
1771 | syscalls, it's possible to isolate those applications in | |
1772 | their own address space using seccomp. Once seccomp is | |
1773 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1774 | and the task is only allowed to execute a few safe syscalls | |
1775 | defined by each seccomp mode. | |
1776 | ||
02c2433b SS |
1777 | config PARAVIRT |
1778 | bool "Enable paravirtualization code" | |
1779 | help | |
1780 | This changes the kernel so it can modify itself when it is run | |
1781 | under a hypervisor, potentially improving performance significantly | |
1782 | over full virtualization. | |
1783 | ||
1784 | config PARAVIRT_TIME_ACCOUNTING | |
1785 | bool "Paravirtual steal time accounting" | |
1786 | select PARAVIRT | |
1787 | default n | |
1788 | help | |
1789 | Select this option to enable fine granularity task steal time | |
1790 | accounting. Time spent executing other tasks in parallel with | |
1791 | the current vCPU is discounted from the vCPU power. To account for | |
1792 | that, there can be a small performance impact. | |
1793 | ||
1794 | If in doubt, say N here. | |
1795 | ||
eff8d644 SS |
1796 | config XEN_DOM0 |
1797 | def_bool y | |
1798 | depends on XEN | |
1799 | ||
1800 | config XEN | |
c2ba1f7d | 1801 | bool "Xen guest support on ARM" |
85323a99 | 1802 | depends on ARM && AEABI && OF |
f880b67d | 1803 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1804 | depends on !GENERIC_ATOMIC64 |
7693decc | 1805 | depends on MMU |
51aaf81f | 1806 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1807 | select ARM_PSCI |
f21254cd | 1808 | select SWIOTLB |
83862ccf | 1809 | select SWIOTLB_XEN |
02c2433b | 1810 | select PARAVIRT |
eff8d644 SS |
1811 | help |
1812 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1813 | ||
1da177e4 LT |
1814 | endmenu |
1815 | ||
1816 | menu "Boot options" | |
1817 | ||
9eb8f674 GL |
1818 | config USE_OF |
1819 | bool "Flattened Device Tree support" | |
b1b3f49c | 1820 | select IRQ_DOMAIN |
9eb8f674 | 1821 | select OF |
9eb8f674 GL |
1822 | help |
1823 | Include support for flattened device tree machine descriptions. | |
1824 | ||
bd51e2f5 NP |
1825 | config ATAGS |
1826 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1827 | default y | |
1828 | help | |
1829 | This is the traditional way of passing data to the kernel at boot | |
1830 | time. If you are solely relying on the flattened device tree (or | |
1831 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1832 | to remove ATAGS support from your kernel binary. If unsure, | |
1833 | leave this to y. | |
1834 | ||
1835 | config DEPRECATED_PARAM_STRUCT | |
1836 | bool "Provide old way to pass kernel parameters" | |
1837 | depends on ATAGS | |
1838 | help | |
1839 | This was deprecated in 2001 and announced to live on for 5 years. | |
1840 | Some old boot loaders still use this way. | |
1841 | ||
1da177e4 LT |
1842 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1843 | # TEXT and BSS so we preserve their values in the config files. | |
1844 | config ZBOOT_ROM_TEXT | |
1845 | hex "Compressed ROM boot loader base address" | |
1846 | default "0" | |
1847 | help | |
1848 | The physical address at which the ROM-able zImage is to be | |
1849 | placed in the target. Platforms which normally make use of | |
1850 | ROM-able zImage formats normally set this to a suitable | |
1851 | value in their defconfig file. | |
1852 | ||
1853 | If ZBOOT_ROM is not enabled, this has no effect. | |
1854 | ||
1855 | config ZBOOT_ROM_BSS | |
1856 | hex "Compressed ROM boot loader BSS address" | |
1857 | default "0" | |
1858 | help | |
f8c440b2 DF |
1859 | The base address of an area of read/write memory in the target |
1860 | for the ROM-able zImage which must be available while the | |
1861 | decompressor is running. It must be large enough to hold the | |
1862 | entire decompressed kernel plus an additional 128 KiB. | |
1863 | Platforms which normally make use of ROM-able zImage formats | |
1864 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1865 | |
1866 | If ZBOOT_ROM is not enabled, this has no effect. | |
1867 | ||
1868 | config ZBOOT_ROM | |
1869 | bool "Compressed boot loader in ROM/flash" | |
1870 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1871 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1872 | help |
1873 | Say Y here if you intend to execute your compressed kernel image | |
1874 | (zImage) directly from ROM or flash. If unsure, say N. | |
1875 | ||
e2a6a3aa JB |
1876 | config ARM_APPENDED_DTB |
1877 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1878 | depends on OF |
e2a6a3aa JB |
1879 | help |
1880 | With this option, the boot code will look for a device tree binary | |
1881 | (DTB) appended to zImage | |
1882 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1883 | ||
1884 | This is meant as a backward compatibility convenience for those | |
1885 | systems with a bootloader that can't be upgraded to accommodate | |
1886 | the documented boot protocol using a device tree. | |
1887 | ||
1888 | Beware that there is very little in terms of protection against | |
1889 | this option being confused by leftover garbage in memory that might | |
1890 | look like a DTB header after a reboot if no actual DTB is appended | |
1891 | to zImage. Do not leave this option active in a production kernel | |
1892 | if you don't intend to always append a DTB. Proper passing of the | |
1893 | location into r2 of a bootloader provided DTB is always preferable | |
1894 | to this option. | |
1895 | ||
b90b9a38 NP |
1896 | config ARM_ATAG_DTB_COMPAT |
1897 | bool "Supplement the appended DTB with traditional ATAG information" | |
1898 | depends on ARM_APPENDED_DTB | |
1899 | help | |
1900 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1901 | they provide ATAGs with memory configuration, the ramdisk address, | |
1902 | the kernel cmdline string, etc. Such information is dynamically | |
1903 | provided by the bootloader and can't always be stored in a static | |
1904 | DTB. To allow a device tree enabled kernel to be used with such | |
1905 | bootloaders, this option allows zImage to extract the information | |
1906 | from the ATAG list and store it at run time into the appended DTB. | |
1907 | ||
d0f34a11 GR |
1908 | choice |
1909 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1910 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1911 | ||
1912 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1913 | bool "Use bootloader kernel arguments if available" | |
1914 | help | |
1915 | Uses the command-line options passed by the boot loader instead of | |
1916 | the device tree bootargs property. If the boot loader doesn't provide | |
1917 | any, the device tree bootargs property will be used. | |
1918 | ||
1919 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1920 | bool "Extend with bootloader kernel arguments" | |
1921 | help | |
1922 | The command-line arguments provided by the boot loader will be | |
1923 | appended to the the device tree bootargs property. | |
1924 | ||
1925 | endchoice | |
1926 | ||
1da177e4 LT |
1927 | config CMDLINE |
1928 | string "Default kernel command string" | |
1929 | default "" | |
1930 | help | |
1931 | On some architectures (EBSA110 and CATS), there is currently no way | |
1932 | for the boot loader to pass arguments to the kernel. For these | |
1933 | architectures, you should supply some command-line options at build | |
1934 | time by entering them here. As a minimum, you should specify the | |
1935 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1936 | ||
4394c124 VB |
1937 | choice |
1938 | prompt "Kernel command line type" if CMDLINE != "" | |
1939 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1940 | depends on ATAGS |
4394c124 VB |
1941 | |
1942 | config CMDLINE_FROM_BOOTLOADER | |
1943 | bool "Use bootloader kernel arguments if available" | |
1944 | help | |
1945 | Uses the command-line options passed by the boot loader. If | |
1946 | the boot loader doesn't provide any, the default kernel command | |
1947 | string provided in CMDLINE will be used. | |
1948 | ||
1949 | config CMDLINE_EXTEND | |
1950 | bool "Extend bootloader kernel arguments" | |
1951 | help | |
1952 | The command-line arguments provided by the boot loader will be | |
1953 | appended to the default kernel command string. | |
1954 | ||
92d2040d AH |
1955 | config CMDLINE_FORCE |
1956 | bool "Always use the default kernel command string" | |
92d2040d AH |
1957 | help |
1958 | Always use the default kernel command string, even if the boot | |
1959 | loader passes other arguments to the kernel. | |
1960 | This is useful if you cannot or don't want to change the | |
1961 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1962 | endchoice |
92d2040d | 1963 | |
1da177e4 LT |
1964 | config XIP_KERNEL |
1965 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1966 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1967 | help |
1968 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1969 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1970 | space since the text section of the kernel is not loaded from flash | |
1971 | to RAM. Read-write sections, such as the data section and stack, | |
1972 | are still copied to RAM. The XIP kernel is not compressed since | |
1973 | it has to run directly from flash, so it will take more space to | |
1974 | store it. The flash address used to link the kernel object files, | |
1975 | and for storing it, is configuration dependent. Therefore, if you | |
1976 | say Y here, you must know the proper physical address where to | |
1977 | store the kernel image depending on your own flash memory usage. | |
1978 | ||
1979 | Also note that the make target becomes "make xipImage" rather than | |
1980 | "make zImage" or "make Image". The final kernel binary to put in | |
1981 | ROM memory will be arch/arm/boot/xipImage. | |
1982 | ||
1983 | If unsure, say N. | |
1984 | ||
1985 | config XIP_PHYS_ADDR | |
1986 | hex "XIP Kernel Physical Location" | |
1987 | depends on XIP_KERNEL | |
1988 | default "0x00080000" | |
1989 | help | |
1990 | This is the physical address in your flash memory the kernel will | |
1991 | be linked for and stored to. This address is dependent on your | |
1992 | own flash usage. | |
1993 | ||
ca8b5d97 NP |
1994 | config XIP_DEFLATED_DATA |
1995 | bool "Store kernel .data section compressed in ROM" | |
1996 | depends on XIP_KERNEL | |
1997 | select ZLIB_INFLATE | |
1998 | help | |
1999 | Before the kernel is actually executed, its .data section has to be | |
2000 | copied to RAM from ROM. This option allows for storing that data | |
2001 | in compressed form and decompressed to RAM rather than merely being | |
2002 | copied, saving some precious ROM space. A possible drawback is a | |
2003 | slightly longer boot delay. | |
2004 | ||
c587e4a6 RP |
2005 | config KEXEC |
2006 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2007 | depends on (!SMP || PM_SLEEP_SMP) |
cb1293e2 | 2008 | depends on !CPU_V7M |
2965faa5 | 2009 | select KEXEC_CORE |
c587e4a6 RP |
2010 | help |
2011 | kexec is a system call that implements the ability to shutdown your | |
2012 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2013 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2014 | you can start any kernel with it, not just Linux. |
2015 | ||
2016 | It is an ongoing process to be certain the hardware in a machine | |
2017 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 2018 | initially work for you. |
c587e4a6 | 2019 | |
4cd9d6f7 RP |
2020 | config ATAGS_PROC |
2021 | bool "Export atags in procfs" | |
bd51e2f5 | 2022 | depends on ATAGS && KEXEC |
b98d7291 | 2023 | default y |
4cd9d6f7 RP |
2024 | help |
2025 | Should the atags used to boot the kernel be exported in an "atags" | |
2026 | file in procfs. Useful with kexec. | |
2027 | ||
cb5d39b3 MW |
2028 | config CRASH_DUMP |
2029 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2030 | help |
2031 | Generate crash dump after being started by kexec. This should | |
2032 | be normally only set in special crash dump kernels which are | |
2033 | loaded in the main kernel with kexec-tools into a specially | |
2034 | reserved region and then later executed after a crash by | |
2035 | kdump/kexec. The crash dump kernel must be compiled to a | |
2036 | memory address not used by the main kernel | |
2037 | ||
2038 | For more details see Documentation/kdump/kdump.txt | |
2039 | ||
e69edc79 EM |
2040 | config AUTO_ZRELADDR |
2041 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2042 | help |
2043 | ZRELADDR is the physical address where the decompressed kernel | |
2044 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2045 | will be determined at run-time by masking the current IP with | |
2046 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2047 | from start of memory. | |
2048 | ||
81a0bc39 RF |
2049 | config EFI_STUB |
2050 | bool | |
2051 | ||
2052 | config EFI | |
2053 | bool "UEFI runtime support" | |
2054 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
2055 | select UCS2_STRING | |
2056 | select EFI_PARAMS_FROM_FDT | |
2057 | select EFI_STUB | |
2058 | select EFI_ARMSTUB | |
2059 | select EFI_RUNTIME_WRAPPERS | |
2060 | ---help--- | |
2061 | This option provides support for runtime services provided | |
2062 | by UEFI firmware (such as non-volatile variables, realtime | |
2063 | clock, and platform reset). A UEFI stub is also provided to | |
2064 | allow the kernel to be booted as an EFI application. This | |
2065 | is only useful for kernels that may run on systems that have | |
2066 | UEFI firmware. | |
2067 | ||
bb817bef AB |
2068 | config DMI |
2069 | bool "Enable support for SMBIOS (DMI) tables" | |
2070 | depends on EFI | |
2071 | default y | |
2072 | help | |
2073 | This enables SMBIOS/DMI feature for systems. | |
2074 | ||
2075 | This option is only useful on systems that have UEFI firmware. | |
2076 | However, even with this option, the resultant kernel should | |
2077 | continue to boot on existing non-UEFI platforms. | |
2078 | ||
2079 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
2080 | i.e., the the practice of identifying the platform via DMI to | |
2081 | decide whether certain workarounds for buggy hardware and/or | |
2082 | firmware need to be enabled. This would require the DMI subsystem | |
2083 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
2084 | ||
1da177e4 LT |
2085 | endmenu |
2086 | ||
ac9d7efc | 2087 | menu "CPU Power Management" |
1da177e4 | 2088 | |
1da177e4 | 2089 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2090 | |
ac9d7efc RK |
2091 | source "drivers/cpuidle/Kconfig" |
2092 | ||
2093 | endmenu | |
2094 | ||
1da177e4 LT |
2095 | menu "Floating point emulation" |
2096 | ||
2097 | comment "At least one emulation must be selected" | |
2098 | ||
2099 | config FPE_NWFPE | |
2100 | bool "NWFPE math emulation" | |
593c252a | 2101 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2102 | ---help--- |
2103 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2104 | This is necessary to run most binaries. Linux does not currently | |
2105 | support floating point hardware so you need to say Y here even if | |
2106 | your machine has an FPA or floating point co-processor podule. | |
2107 | ||
2108 | You may say N here if you are going to load the Acorn FPEmulator | |
2109 | early in the bootup. | |
2110 | ||
2111 | config FPE_NWFPE_XP | |
2112 | bool "Support extended precision" | |
bedf142b | 2113 | depends on FPE_NWFPE |
1da177e4 LT |
2114 | help |
2115 | Say Y to include 80-bit support in the kernel floating-point | |
2116 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2117 | Note that gcc does not generate 80-bit operations by default, | |
2118 | so in most cases this option only enlarges the size of the | |
2119 | floating point emulator without any good reason. | |
2120 | ||
2121 | You almost surely want to say N here. | |
2122 | ||
2123 | config FPE_FASTFPE | |
2124 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2125 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2126 | ---help--- |
2127 | Say Y here to include the FAST floating point emulator in the kernel. | |
2128 | This is an experimental much faster emulator which now also has full | |
2129 | precision for the mantissa. It does not support any exceptions. | |
2130 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2131 | ||
2132 | It should be sufficient for most programs. It may be not suitable | |
2133 | for scientific calculations, but you have to check this for yourself. | |
2134 | If you do not feel you need a faster FP emulation you should better | |
2135 | choose NWFPE. | |
2136 | ||
2137 | config VFP | |
2138 | bool "VFP-format floating point maths" | |
e399b1a4 | 2139 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2140 | help |
2141 | Say Y to include VFP support code in the kernel. This is needed | |
2142 | if your hardware includes a VFP unit. | |
2143 | ||
2144 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2145 | release notes and additional status information. | |
2146 | ||
2147 | Say N if your target does not have VFP hardware. | |
2148 | ||
25ebee02 CM |
2149 | config VFPv3 |
2150 | bool | |
2151 | depends on VFP | |
2152 | default y if CPU_V7 | |
2153 | ||
b5872db4 CM |
2154 | config NEON |
2155 | bool "Advanced SIMD (NEON) Extension support" | |
2156 | depends on VFPv3 && CPU_V7 | |
2157 | help | |
2158 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2159 | Extension. | |
2160 | ||
73c132c1 AB |
2161 | config KERNEL_MODE_NEON |
2162 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2163 | depends on NEON && AEABI |
73c132c1 AB |
2164 | help |
2165 | Say Y to include support for NEON in kernel mode. | |
2166 | ||
1da177e4 LT |
2167 | endmenu |
2168 | ||
1da177e4 LT |
2169 | menu "Power management options" |
2170 | ||
eceab4ac | 2171 | source "kernel/power/Kconfig" |
1da177e4 | 2172 | |
f4cb5700 | 2173 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2174 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2175 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2176 | def_bool y |
2177 | ||
15e0d9e3 | 2178 | config ARM_CPU_SUSPEND |
8b6f2499 | 2179 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 2180 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 2181 | |
603fb42a SC |
2182 | config ARCH_HIBERNATION_POSSIBLE |
2183 | bool | |
2184 | depends on MMU | |
2185 | default y if ARCH_SUSPEND_POSSIBLE | |
2186 | ||
1da177e4 LT |
2187 | endmenu |
2188 | ||
916f743d KG |
2189 | source "drivers/firmware/Kconfig" |
2190 | ||
652ccae5 AB |
2191 | if CRYPTO |
2192 | source "arch/arm/crypto/Kconfig" | |
2193 | endif | |
1da177e4 | 2194 | |
749cf76c | 2195 | source "arch/arm/kvm/Kconfig" |