Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
fed240d9 | 6 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND |
aef0f78e | 7 | select ARCH_HAS_BINFMT_FLAT |
2792d84e | 8 | select ARCH_HAS_CURRENT_STACK_POINTER |
c7780ab5 | 9 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
419e2f18 | 10 | select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE |
2b68f6ca | 11 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 12 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 13 | select ARCH_HAS_KEEPINITRD |
75851720 | 14 | select ARCH_HAS_KCOV |
e69244d2 | 15 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 16 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
3010a5ea | 17 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
347cb6af | 18 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 19 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
20 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
21 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
31b089bb CH |
22 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU |
23 | select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU | |
dc2acded | 24 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 25 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 26 | select ARCH_HAVE_CUSTOM_GPIO_H |
9aaf9bb7 | 27 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K |
957e3fac | 28 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e545df3 | 29 | select ARCH_KEEP_MEMBLOCK |
d7018848 | 30 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7c703e54 | 31 | select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN |
ad21fc4f LA |
32 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
33 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 34 | select ARCH_SUPPORTS_ATOMIC_RMW |
855f9a8e | 35 | select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE |
017f161a | 36 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 37 | select ARCH_USE_CMPXCHG_LOCKREF |
dce44566 | 38 | select ARCH_USE_MEMTEST |
dba79c3d | 39 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
07431506 | 40 | select ARCH_WANT_GENERAL_HUGETLB |
b1b3f49c | 41 | select ARCH_WANT_IPC_PARSE_VERSION |
59612b24 | 42 | select ARCH_WANT_LD_ORPHAN_WARN |
bdd15a28 | 43 | select BINFMT_FLAT_ARGVP_ENVP_ON_STACK |
10916706 | 44 | select BUILDTIME_TABLE_SORT if MMU |
171b3f0d | 45 | select CLONE_BACKWARDS |
f00790aa | 46 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 47 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 48 | select DMA_DECLARE_COHERENT |
31b089bb | 49 | select DMA_GLOBAL_POOL if !MMU |
2f9237d4 | 50 | select DMA_OPS |
f5ff79fd | 51 | select DMA_NONCOHERENT_MMAP if MMU |
b01aec9b BP |
52 | select EDAC_SUPPORT |
53 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 54 | select GENERIC_ALLOCATOR |
2ef7a295 | 55 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 56 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 57 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
56afcd3d | 58 | select GENERIC_IRQ_IPI if SMP |
ea2d9a96 | 59 | select GENERIC_CPU_AUTOPROBE |
2937367b | 60 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 61 | select GENERIC_IDLE_POLL_SETUP |
234a0f20 | 62 | select GENERIC_IRQ_MULTI_HANDLER |
b1b3f49c RK |
63 | select GENERIC_IRQ_PROBE |
64 | select GENERIC_IRQ_SHOW | |
7c07005e | 65 | select GENERIC_IRQ_SHOW_LEVEL |
914ee966 | 66 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
b1b3f49c | 67 | select GENERIC_PCI_IOMAP |
38ff87f7 | 68 | select GENERIC_SCHED_CLOCK |
b1b3f49c | 69 | select GENERIC_SMP_IDLE_THREAD |
b1b3f49c | 70 | select HARDIRQS_SW_RESEND |
f00790aa | 71 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 72 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee | 73 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
75969686 | 74 | select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL |
437682ee | 75 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU |
42101571 | 76 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL |
e0c25d95 | 77 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
4f5b0c17 | 78 | select HAVE_ARCH_PFN_VALID |
282a181b | 79 | select HAVE_ARCH_SECCOMP |
f00790aa | 80 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 81 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 82 | select HAVE_ARCH_TRACEHOOK |
e8003bf6 | 83 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE |
b329f95d | 84 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 85 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 86 | select HAVE_CONTEXT_TRACKING |
b1b3f49c | 87 | select HAVE_C_RECORDMCOUNT |
4ed308c4 | 88 | select HAVE_BUILDTIME_MCOUNT_SORT |
bc420c6c | 89 | select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL |
b1b3f49c | 90 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 91 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 92 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 93 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 94 | select HAVE_EXIT_THREAD |
67a929e0 | 95 | select HAVE_FAST_GUP if ARM_LPAE |
f00790aa | 96 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
41918ec8 | 97 | select HAVE_FUNCTION_GRAPH_TRACER |
d6800ca7 | 98 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 99 | select HAVE_GCC_PLUGINS |
f00790aa | 100 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
87c46b6c | 101 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 102 | select HAVE_KERNEL_GZIP |
f9b493ac | 103 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 104 | select HAVE_KERNEL_LZMA |
b1b3f49c | 105 | select HAVE_KERNEL_LZO |
a7f464f3 | 106 | select HAVE_KERNEL_XZ |
cb1293e2 | 107 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 108 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 109 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 110 | select HAVE_NMI |
0dc016db | 111 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 112 | select HAVE_PERF_EVENTS |
49863894 WD |
113 | select HAVE_PERF_REGS |
114 | select HAVE_PERF_USER_STACK_DUMP | |
ff2e6d72 | 115 | select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 116 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 117 | select HAVE_RSEQ |
d148eac0 | 118 | select HAVE_STACKPROTECTOR |
b1b3f49c | 119 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 120 | select HAVE_UID16 |
31c1fc81 | 121 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 122 | select IRQ_FORCED_THREADING |
171b3f0d | 123 | select MODULES_USE_ELF_REL |
f616ab59 | 124 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 125 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
126 | select OLD_SIGACTION |
127 | select OLD_SIGSUSPEND3 | |
20f1b79d | 128 | select PCI_SYSCALL if PCI |
b1b3f49c RK |
129 | select PERF_USE_VMALLOC |
130 | select RTC_LIB | |
131 | select SYS_SUPPORTS_APM_EMULATION | |
9c46929e | 132 | select THREAD_INFO_IN_TASK |
d6905849 | 133 | select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS |
4aae683f | 134 | select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M |
171b3f0d RK |
135 | # Above selects are sorted alphabetically; please add new ones |
136 | # according to that. Thanks. | |
1da177e4 LT |
137 | help |
138 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 139 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 140 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 141 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
142 | Europe. There is an ARM Linux project with a web page at |
143 | <http://www.arm.linux.org.uk/>. | |
144 | ||
d6905849 AB |
145 | config ARM_HAS_GROUP_RELOCS |
146 | def_bool y | |
147 | depends on !LD_IS_LLD || LLD_VERSION >= 140000 | |
148 | depends on !COMPILE_TEST | |
149 | help | |
150 | Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group | |
151 | relocations, which have been around for a long time, but were not | |
152 | supported in LLD until version 14. The combined range is -/+ 256 MiB, | |
153 | which is usually sufficient, but not for allyesconfig, so we disable | |
154 | this feature when doing compile testing. | |
155 | ||
74facffe RK |
156 | config ARM_HAS_SG_CHAIN |
157 | bool | |
158 | ||
4ce63fcd | 159 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 160 | bool |
b1b3f49c RK |
161 | select ARM_HAS_SG_CHAIN |
162 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 163 | |
60460abf SWK |
164 | if ARM_DMA_USE_IOMMU |
165 | ||
166 | config ARM_DMA_IOMMU_ALIGNMENT | |
167 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
168 | range 4 9 | |
169 | default 8 | |
170 | help | |
171 | DMA mapping framework by default aligns all buffers to the smallest | |
172 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
173 | size. This works well for buffers up to a few hundreds kilobytes, but | |
174 | for larger buffers it just a waste of address space. Drivers which has | |
175 | relatively small addressing window (like 64Mib) might run out of | |
176 | virtual space with just a few allocations. | |
177 | ||
178 | With this parameter you can specify the maximum PAGE_SIZE order for | |
179 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
180 | specified order. The order is expressed as a power of two multiplied | |
181 | by the PAGE_SIZE. | |
182 | ||
183 | endif | |
184 | ||
75e7153a RB |
185 | config SYS_SUPPORTS_APM_EMULATION |
186 | bool | |
187 | ||
bc581770 LW |
188 | config HAVE_TCM |
189 | bool | |
190 | select GENERIC_ALLOCATOR | |
191 | ||
e119bfff RK |
192 | config HAVE_PROC_CPU |
193 | bool | |
194 | ||
ce816fa8 | 195 | config NO_IOPORT_MAP |
5ea81769 | 196 | bool |
5ea81769 | 197 | |
1da177e4 LT |
198 | config SBUS |
199 | bool | |
200 | ||
f16fb1ec RK |
201 | config STACKTRACE_SUPPORT |
202 | bool | |
203 | default y | |
204 | ||
205 | config LOCKDEP_SUPPORT | |
206 | bool | |
207 | default y | |
208 | ||
f0d1b0b3 DH |
209 | config ARCH_HAS_ILOG2_U32 |
210 | bool | |
f0d1b0b3 DH |
211 | |
212 | config ARCH_HAS_ILOG2_U64 | |
213 | bool | |
f0d1b0b3 | 214 | |
4a1b5733 EV |
215 | config ARCH_HAS_BANDGAP |
216 | bool | |
217 | ||
a5f4c561 SA |
218 | config FIX_EARLYCON_MEM |
219 | def_bool y if MMU | |
220 | ||
b89c3b16 AM |
221 | config GENERIC_HWEIGHT |
222 | bool | |
223 | default y | |
224 | ||
1da177e4 LT |
225 | config GENERIC_CALIBRATE_DELAY |
226 | bool | |
227 | default y | |
228 | ||
a08b6b79 Z |
229 | config ARCH_MAY_HAVE_PC_FDC |
230 | bool | |
231 | ||
c7edc9e3 DL |
232 | config ARCH_SUPPORTS_UPROBES |
233 | def_bool y | |
234 | ||
1da177e4 LT |
235 | config GENERIC_ISA_DMA |
236 | bool | |
237 | ||
1da177e4 LT |
238 | config FIQ |
239 | bool | |
240 | ||
034d2f5a AV |
241 | config ARCH_MTD_XIP |
242 | bool | |
243 | ||
dc21af99 | 244 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
245 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
246 | default y | |
b511d75d | 247 | depends on !XIP_KERNEL && MMU |
dc21af99 | 248 | help |
111e9a5c RK |
249 | Patch phys-to-virt and virt-to-phys translation functions at |
250 | boot and module load time according to the position of the | |
251 | kernel in system memory. | |
dc21af99 | 252 | |
111e9a5c | 253 | This can only be used with non-XIP MMU kernels where the base |
9443076e | 254 | of physical memory is at a 2 MiB boundary. |
dc21af99 | 255 | |
c1becedc RK |
256 | Only disable this option if you know that you do not require |
257 | this feature (eg, building a kernel for a single machine) and | |
258 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 259 | |
c334bc15 RH |
260 | config NEED_MACH_IO_H |
261 | bool | |
262 | help | |
263 | Select this when mach/io.h is required to provide special | |
264 | definitions for this platform. The need for mach/io.h should | |
265 | be avoided when possible. | |
266 | ||
0cdc8b92 | 267 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
268 | bool |
269 | help | |
0cdc8b92 NP |
270 | Select this when mach/memory.h is required to provide special |
271 | definitions for this platform. The need for mach/memory.h should | |
272 | be avoided when possible. | |
dc21af99 | 273 | |
1b9f95f8 | 274 | config PHYS_OFFSET |
974c0724 | 275 | hex "Physical address of main memory" if MMU |
c6f54a9b | 276 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 277 | default DRAM_BASE if !MMU |
06954b6a | 278 | default 0x00000000 if ARCH_FOOTBRIDGE |
c6f54a9b | 279 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
c6e77bb6 AB |
280 | default 0x30000000 if ARCH_S3C24XX |
281 | default 0xa0000000 if ARCH_IOP32X || ARCH_PXA | |
282 | default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 | |
283 | default 0 | |
111e9a5c | 284 | help |
1b9f95f8 NP |
285 | Please provide the physical address corresponding to the |
286 | location of main memory in your system. | |
cada3c08 | 287 | |
87e040b6 SG |
288 | config GENERIC_BUG |
289 | def_bool y | |
290 | depends on BUG | |
291 | ||
1bcad26e KS |
292 | config PGTABLE_LEVELS |
293 | int | |
294 | default 3 if ARM_LPAE | |
295 | default 2 | |
296 | ||
1da177e4 LT |
297 | menu "System Type" |
298 | ||
3c427975 HC |
299 | config MMU |
300 | bool "MMU-based Paged Memory Management Support" | |
301 | default y | |
302 | help | |
303 | Select if you want MMU-based virtualised addressing space | |
304 | support by paged memory management. If unsure, say 'Y'. | |
305 | ||
2f618d5e AB |
306 | config ARM_SINGLE_ARMV7M |
307 | def_bool !MMU | |
308 | select ARM_NVIC | |
309 | select AUTO_ZRELADDR | |
310 | select TIMER_OF | |
311 | select COMMON_CLK | |
312 | select CPU_V7M | |
313 | select NO_IOPORT_MAP | |
314 | select SPARSE_IRQ | |
315 | select USE_OF | |
316 | ||
e0c25d95 DC |
317 | config ARCH_MMAP_RND_BITS_MIN |
318 | default 8 | |
319 | ||
320 | config ARCH_MMAP_RND_BITS_MAX | |
321 | default 14 if PAGE_OFFSET=0x40000000 | |
322 | default 15 if PAGE_OFFSET=0x80000000 | |
323 | default 16 | |
324 | ||
ccf50e23 RK |
325 | # |
326 | # The "ARM system type" choice list is ordered alphabetically by option | |
327 | # text. Please add new entries in the option alphabetic order. | |
328 | # | |
1da177e4 LT |
329 | choice |
330 | prompt "ARM system type" | |
2f618d5e AB |
331 | depends on MMU |
332 | default ARCH_MULTIPLATFORM | |
1da177e4 | 333 | |
387798b3 RH |
334 | config ARCH_MULTIPLATFORM |
335 | bool "Allow multiple platforms to be selected" | |
fb597f2a GF |
336 | select ARCH_FLATMEM_ENABLE |
337 | select ARCH_SPARSEMEM_ENABLE | |
338 | select ARCH_SELECT_MEMORY_MODEL | |
42dc836d | 339 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
340 | select ARM_PATCH_PHYS_VIRT |
341 | select AUTO_ZRELADDR | |
bb0eb050 | 342 | select TIMER_OF |
66314223 | 343 | select COMMON_CLK |
eb01d42a | 344 | select HAVE_PCI |
2eac9c2d | 345 | select PCI_DOMAINS_GENERIC if PCI |
66314223 DN |
346 | select SPARSE_IRQ |
347 | select USE_OF | |
66314223 | 348 | |
1da177e4 LT |
349 | config ARCH_FOOTBRIDGE |
350 | bool "FootBridge" | |
5d6f5267 | 351 | depends on CPU_LITTLE_ENDIAN |
c750815e | 352 | select CPU_SA110 |
1da177e4 | 353 | select FOOTBRIDGE |
0cdc8b92 | 354 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
355 | help |
356 | Support for systems based on the DC21285 companion chip | |
357 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 358 | |
1da177e4 LT |
359 | config ARCH_RPC |
360 | bool "RiscPC" | |
2abd6e34 | 361 | depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 |
5d6f5267 | 362 | depends on CPU_LITTLE_ENDIAN |
1da177e4 | 363 | select ARCH_ACORN |
a08b6b79 | 364 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 365 | select ARCH_SPARSEMEM_ENABLE |
0b40deee | 366 | select ARM_HAS_SG_CHAIN |
fa04e209 | 367 | select CPU_SA110 |
b1b3f49c | 368 | select FIQ |
b1b3f49c RK |
369 | select HAVE_PATA_PLATFORM |
370 | select ISA_DMA_API | |
6239da29 | 371 | select LEGACY_TIMER_TICK |
c334bc15 | 372 | select NEED_MACH_IO_H |
0cdc8b92 | 373 | select NEED_MACH_MEMORY_H |
ce816fa8 | 374 | select NO_IOPORT_MAP |
1da177e4 LT |
375 | help |
376 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
377 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
378 | ||
379 | config ARCH_SA1100 | |
380 | bool "SA1100-based" | |
5d6f5267 | 381 | depends on CPU_LITTLE_ENDIAN |
b1b3f49c | 382 | select ARCH_MTD_XIP |
b1b3f49c | 383 | select ARCH_SPARSEMEM_ENABLE |
b1b3f49c | 384 | select CLKSRC_MMIO |
389d9b58 | 385 | select CLKSRC_PXA |
bb0eb050 | 386 | select TIMER_OF if OF |
d6c82046 | 387 | select COMMON_CLK |
1937f5b9 | 388 | select CPU_FREQ |
b1b3f49c | 389 | select CPU_SA1100 |
5c34a4e8 | 390 | select GPIOLIB |
1eca42b4 | 391 | select IRQ_DOMAIN |
b1b3f49c | 392 | select ISA |
0cdc8b92 | 393 | select NEED_MACH_MEMORY_H |
375dec92 | 394 | select SPARSE_IRQ |
f999b8bd MM |
395 | help |
396 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 397 | |
1da177e4 LT |
398 | endchoice |
399 | ||
387798b3 RH |
400 | menu "Multiple platform selection" |
401 | depends on ARCH_MULTIPLATFORM | |
402 | ||
403 | comment "CPU Core family selection" | |
404 | ||
f8afae40 AB |
405 | config ARCH_MULTI_V4 |
406 | bool "ARMv4 based platforms (FA526)" | |
407 | depends on !ARCH_MULTI_V6_V7 | |
408 | select ARCH_MULTI_V4_V5 | |
409 | select CPU_FA526 | |
410 | ||
387798b3 RH |
411 | config ARCH_MULTI_V4T |
412 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 413 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 414 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
415 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
416 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
417 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
418 | |
419 | config ARCH_MULTI_V5 | |
420 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 421 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 422 | select ARCH_MULTI_V4_V5 |
12567bbd | 423 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
424 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
425 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
426 | |
427 | config ARCH_MULTI_V4_V5 | |
428 | bool | |
429 | ||
430 | config ARCH_MULTI_V6 | |
8dda05cc | 431 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 432 | select ARCH_MULTI_V6_V7 |
42f4754a | 433 | select CPU_V6K |
387798b3 RH |
434 | |
435 | config ARCH_MULTI_V7 | |
8dda05cc | 436 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
437 | default y |
438 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 439 | select CPU_V7 |
90bc8ac7 | 440 | select HAVE_SMP |
387798b3 RH |
441 | |
442 | config ARCH_MULTI_V6_V7 | |
443 | bool | |
9352b05b | 444 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
445 | |
446 | config ARCH_MULTI_CPU_AUTO | |
447 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
448 | select ARCH_MULTI_V5 | |
449 | ||
450 | endmenu | |
451 | ||
05e2a3de | 452 | config ARCH_VIRT |
e3246542 MY |
453 | bool "Dummy Virtual Machine" |
454 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 455 | select ARM_AMBA |
05e2a3de | 456 | select ARM_GIC |
3ee80364 | 457 | select ARM_GIC_V2M if PCI |
0b28f1db | 458 | select ARM_GIC_V3 |
bb29cecb | 459 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 460 | select ARM_PSCI |
4b8b5f25 | 461 | select HAVE_ARM_ARCH_TIMER |
05e2a3de | 462 | |
2cf1c348 JC |
463 | config ARCH_AIROHA |
464 | bool "Airoha SoC Support" | |
465 | depends on ARCH_MULTI_V7 | |
466 | select ARM_AMBA | |
467 | select ARM_GIC | |
468 | select ARM_GIC_V3 | |
469 | select ARM_PSCI | |
470 | select HAVE_ARM_ARCH_TIMER | |
471 | select COMMON_CLK | |
472 | help | |
473 | Support for Airoha EN7523 SoCs | |
474 | ||
ccf50e23 RK |
475 | # |
476 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
477 | # Kconfigs may be included either alphabetically (according to the | |
478 | # plat- suffix) or along side the corresponding mach-* source. | |
479 | # | |
6bb8536c AF |
480 | source "arch/arm/mach-actions/Kconfig" |
481 | ||
445d9b30 TZ |
482 | source "arch/arm/mach-alpine/Kconfig" |
483 | ||
590b460c LP |
484 | source "arch/arm/mach-artpec/Kconfig" |
485 | ||
d9bfc86d OR |
486 | source "arch/arm/mach-asm9260/Kconfig" |
487 | ||
a66c51f9 AB |
488 | source "arch/arm/mach-aspeed/Kconfig" |
489 | ||
95b8f20f RK |
490 | source "arch/arm/mach-at91/Kconfig" |
491 | ||
1d22924e AB |
492 | source "arch/arm/mach-axxia/Kconfig" |
493 | ||
8ac49e04 CD |
494 | source "arch/arm/mach-bcm/Kconfig" |
495 | ||
1c37fa10 SH |
496 | source "arch/arm/mach-berlin/Kconfig" |
497 | ||
1da177e4 LT |
498 | source "arch/arm/mach-clps711x/Kconfig" |
499 | ||
d94f944e AV |
500 | source "arch/arm/mach-cns3xxx/Kconfig" |
501 | ||
95b8f20f RK |
502 | source "arch/arm/mach-davinci/Kconfig" |
503 | ||
df8d742e BS |
504 | source "arch/arm/mach-digicolor/Kconfig" |
505 | ||
95b8f20f RK |
506 | source "arch/arm/mach-dove/Kconfig" |
507 | ||
e7736d47 LB |
508 | source "arch/arm/mach-ep93xx/Kconfig" |
509 | ||
a66c51f9 | 510 | source "arch/arm/mach-exynos/Kconfig" |
a66c51f9 | 511 | |
1da177e4 LT |
512 | source "arch/arm/mach-footbridge/Kconfig" |
513 | ||
59d3a193 PZ |
514 | source "arch/arm/mach-gemini/Kconfig" |
515 | ||
387798b3 RH |
516 | source "arch/arm/mach-highbank/Kconfig" |
517 | ||
389ee0c2 HZ |
518 | source "arch/arm/mach-hisi/Kconfig" |
519 | ||
11d89440 NH |
520 | source "arch/arm/mach-hpe/Kconfig" |
521 | ||
a66c51f9 AB |
522 | source "arch/arm/mach-imx/Kconfig" |
523 | ||
3f7e5815 LB |
524 | source "arch/arm/mach-iop32x/Kconfig" |
525 | ||
1da177e4 LT |
526 | source "arch/arm/mach-ixp4xx/Kconfig" |
527 | ||
828989ad SS |
528 | source "arch/arm/mach-keystone/Kconfig" |
529 | ||
75bf1bd7 | 530 | source "arch/arm/mach-lpc32xx/Kconfig" |
95b8f20f | 531 | |
a66c51f9 AB |
532 | source "arch/arm/mach-mediatek/Kconfig" |
533 | ||
3b8f5030 CC |
534 | source "arch/arm/mach-meson/Kconfig" |
535 | ||
9fb29c73 ST |
536 | source "arch/arm/mach-milbeaut/Kconfig" |
537 | ||
a66c51f9 | 538 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 539 | |
a66c51f9 | 540 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 541 | |
312b62b6 DP |
542 | source "arch/arm/mach-mstar/Kconfig" |
543 | ||
794d15b2 SS |
544 | source "arch/arm/mach-mv78xx0/Kconfig" |
545 | ||
a66c51f9 | 546 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 547 | |
1d3f33d5 SG |
548 | source "arch/arm/mach-mxs/Kconfig" |
549 | ||
95b8f20f | 550 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 551 | |
7bffa14c BH |
552 | source "arch/arm/mach-npcm/Kconfig" |
553 | ||
9851ca57 DT |
554 | source "arch/arm/mach-nspire/Kconfig" |
555 | ||
d48af15e | 556 | source "arch/arm/mach-omap1/Kconfig" |
1da177e4 | 557 | |
1dbae815 TL |
558 | source "arch/arm/mach-omap2/Kconfig" |
559 | ||
9dd0b194 | 560 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 561 | |
a66c51f9 AB |
562 | source "arch/arm/mach-oxnas/Kconfig" |
563 | ||
95b8f20f | 564 | source "arch/arm/mach-pxa/Kconfig" |
585cf175 | 565 | |
8fc1b0f8 KG |
566 | source "arch/arm/mach-qcom/Kconfig" |
567 | ||
78e3dbc1 AF |
568 | source "arch/arm/mach-rda/Kconfig" |
569 | ||
86aeee4d AF |
570 | source "arch/arm/mach-realtek/Kconfig" |
571 | ||
d63dc051 HS |
572 | source "arch/arm/mach-rockchip/Kconfig" |
573 | ||
71b9114d | 574 | source "arch/arm/mach-s3c/Kconfig" |
a66c51f9 AB |
575 | |
576 | source "arch/arm/mach-s5pv210/Kconfig" | |
577 | ||
95b8f20f | 578 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 579 | |
a66c51f9 AB |
580 | source "arch/arm/mach-shmobile/Kconfig" |
581 | ||
387798b3 RH |
582 | source "arch/arm/mach-socfpga/Kconfig" |
583 | ||
a7ed099f | 584 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 585 | |
65ebcc11 SK |
586 | source "arch/arm/mach-sti/Kconfig" |
587 | ||
bcb84fb4 AT |
588 | source "arch/arm/mach-stm32/Kconfig" |
589 | ||
3b52634f MR |
590 | source "arch/arm/mach-sunxi/Kconfig" |
591 | ||
c5f80065 EG |
592 | source "arch/arm/mach-tegra/Kconfig" |
593 | ||
ba56a987 MY |
594 | source "arch/arm/mach-uniphier/Kconfig" |
595 | ||
95b8f20f | 596 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
597 | |
598 | source "arch/arm/mach-versatile/Kconfig" | |
599 | ||
6f35f9a9 TP |
600 | source "arch/arm/mach-vt8500/Kconfig" |
601 | ||
9a45eb69 JC |
602 | source "arch/arm/mach-zynq/Kconfig" |
603 | ||
499f1640 | 604 | # ARMv7-M architecture |
499f1640 SA |
605 | config ARCH_LPC18XX |
606 | bool "NXP LPC18xx/LPC43xx" | |
607 | depends on ARM_SINGLE_ARMV7M | |
608 | select ARCH_HAS_RESET_CONTROLLER | |
609 | select ARM_AMBA | |
610 | select CLKSRC_LPC32XX | |
611 | select PINCTRL | |
612 | help | |
613 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
614 | high performance microcontrollers. | |
615 | ||
1847119d | 616 | config ARCH_MPS2 |
17bd274e | 617 | bool "ARM MPS2 platform" |
1847119d VM |
618 | depends on ARM_SINGLE_ARMV7M |
619 | select ARM_AMBA | |
620 | select CLKSRC_MPS2 | |
621 | help | |
622 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
623 | with a range of available cores like Cortex-M3/M4/M7. | |
624 | ||
625 | Please, note that depends which Application Note is used memory map | |
626 | for the platform may vary, so adjustment of RAM base might be needed. | |
627 | ||
1da177e4 LT |
628 | # Definitions to make life easier |
629 | config ARCH_ACORN | |
630 | bool | |
631 | ||
69b02f6a LB |
632 | config PLAT_ORION |
633 | bool | |
bfe45e0b | 634 | select CLKSRC_MMIO |
b1b3f49c | 635 | select COMMON_CLK |
dc7ad3b3 | 636 | select GENERIC_IRQ_CHIP |
278b45b0 | 637 | select IRQ_DOMAIN |
69b02f6a | 638 | |
abcda1dc TP |
639 | config PLAT_ORION_LEGACY |
640 | bool | |
641 | select PLAT_ORION | |
642 | ||
f4b8b319 RK |
643 | config PLAT_VERSATILE |
644 | bool | |
645 | ||
8636a1f9 | 646 | source "arch/arm/mm/Kconfig" |
1da177e4 | 647 | |
afe4b25e | 648 | config IWMMXT |
d93003e8 SH |
649 | bool "Enable iWMMXt support" |
650 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
651 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
652 | help |
653 | Enable support for iWMMXt context switching at run time if | |
654 | running on a CPU that supports it. | |
655 | ||
3b93e7b0 HC |
656 | if !MMU |
657 | source "arch/arm/Kconfig-nommu" | |
658 | endif | |
659 | ||
3e0a07f8 GC |
660 | config PJ4B_ERRATA_4742 |
661 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
662 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
663 | default y | |
664 | help | |
665 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
666 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
667 | the retiring WFI/WFE instructions and the newly issued subsequent | |
668 | instructions. This sensitivity can result in a CPU hang scenario. | |
669 | Workaround: | |
670 | The software must insert either a Data Synchronization Barrier (DSB) | |
671 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
672 | instruction | |
673 | ||
f0c4b8d6 WD |
674 | config ARM_ERRATA_326103 |
675 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
676 | depends on CPU_V6 | |
677 | help | |
678 | Executing a SWP instruction to read-only memory does not set bit 11 | |
679 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
680 | treat the access as a read, preventing a COW from occurring and | |
681 | causing the faulting task to livelock. | |
682 | ||
9cba3ccc CM |
683 | config ARM_ERRATA_411920 |
684 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 685 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
686 | help |
687 | Invalidation of the Instruction Cache operation can | |
688 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
689 | It does not affect the MPCore. This option enables the ARM Ltd. | |
690 | recommended workaround. | |
691 | ||
7ce236fc CM |
692 | config ARM_ERRATA_430973 |
693 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
694 | depends on CPU_V7 | |
695 | help | |
696 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 697 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
698 | interworking branch is replaced with another code sequence at the |
699 | same virtual address, whether due to self-modifying code or virtual | |
700 | to physical address re-mapping, Cortex-A8 does not recover from the | |
701 | stale interworking branch prediction. This results in Cortex-A8 | |
702 | executing the new code sequence in the incorrect ARM or Thumb state. | |
703 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
704 | and also flushes the branch target cache at every context switch. | |
705 | Note that setting specific bits in the ACTLR register may not be | |
706 | available in non-secure mode. | |
707 | ||
855c551f CM |
708 | config ARM_ERRATA_458693 |
709 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
710 | depends on CPU_V7 | |
62e4d357 | 711 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
712 | help |
713 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
714 | erratum. For very specific sequences of memory operations, it is | |
715 | possible for a hazard condition intended for a cache line to instead | |
716 | be incorrectly associated with a different cache line. This false | |
717 | hazard might then cause a processor deadlock. The workaround enables | |
718 | the L1 caching of the NEON accesses and disables the PLD instruction | |
719 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
720 | register may not be available in non-secure mode. | |
721 | ||
0516e464 CM |
722 | config ARM_ERRATA_460075 |
723 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
724 | depends on CPU_V7 | |
62e4d357 | 725 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
726 | help |
727 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
728 | erratum. Any asynchronous access to the L2 cache may encounter a | |
729 | situation in which recent store transactions to the L2 cache are lost | |
730 | and overwritten with stale memory contents from external memory. The | |
731 | workaround disables the write-allocate mode for the L2 cache via the | |
732 | ACTLR register. Note that setting specific bits in the ACTLR register | |
733 | may not be available in non-secure mode. | |
734 | ||
9f05027c WD |
735 | config ARM_ERRATA_742230 |
736 | bool "ARM errata: DMB operation may be faulty" | |
737 | depends on CPU_V7 && SMP | |
62e4d357 | 738 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
739 | help |
740 | This option enables the workaround for the 742230 Cortex-A9 | |
741 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
742 | between two write operations may not ensure the correct visibility | |
743 | ordering of the two writes. This workaround sets a specific bit in | |
744 | the diagnostic register of the Cortex-A9 which causes the DMB | |
745 | instruction to behave as a DSB, ensuring the correct behaviour of | |
746 | the two writes. | |
747 | ||
a672e99b WD |
748 | config ARM_ERRATA_742231 |
749 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
750 | depends on CPU_V7 && SMP | |
62e4d357 | 751 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
752 | help |
753 | This option enables the workaround for the 742231 Cortex-A9 | |
754 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
755 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
756 | accessing some data located in the same cache line, may get corrupted | |
757 | data due to bad handling of the address hazard when the line gets | |
758 | replaced from one of the CPUs at the same time as another CPU is | |
759 | accessing it. This workaround sets specific bits in the diagnostic | |
760 | register of the Cortex-A9 which reduces the linefill issuing | |
761 | capabilities of the processor. | |
762 | ||
69155794 JM |
763 | config ARM_ERRATA_643719 |
764 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
765 | depends on CPU_V7 && SMP | |
e5a5de44 | 766 | default y |
69155794 JM |
767 | help |
768 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
769 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
770 | register returns zero when it should return one. The workaround | |
771 | corrects this value, ensuring cache maintenance operations which use | |
772 | it behave as intended and avoiding data corruption. | |
773 | ||
cdf357f1 WD |
774 | config ARM_ERRATA_720789 |
775 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 776 | depends on CPU_V7 |
cdf357f1 WD |
777 | help |
778 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
779 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
780 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
781 | As a consequence of this erratum, some TLB entries which should be | |
782 | invalidated are not, resulting in an incoherency in the system page | |
783 | tables. The workaround changes the TLB flushing routines to invalidate | |
784 | entries regardless of the ASID. | |
475d92fc WD |
785 | |
786 | config ARM_ERRATA_743622 | |
787 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
788 | depends on CPU_V7 | |
62e4d357 | 789 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
790 | help |
791 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 792 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
793 | optimisation in the Cortex-A9 Store Buffer may lead to data |
794 | corruption. This workaround sets a specific bit in the diagnostic | |
795 | register of the Cortex-A9 which disables the Store Buffer | |
796 | optimisation, preventing the defect from occurring. This has no | |
797 | visible impact on the overall performance or power consumption of the | |
798 | processor. | |
799 | ||
9a27c27c WD |
800 | config ARM_ERRATA_751472 |
801 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 802 | depends on CPU_V7 |
62e4d357 | 803 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
804 | help |
805 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
806 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
807 | completion of a following broadcasted operation if the second | |
808 | operation is received by a CPU before the ICIALLUIS has completed, | |
809 | potentially leading to corrupted entries in the cache or TLB. | |
810 | ||
fcbdc5fe WD |
811 | config ARM_ERRATA_754322 |
812 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
813 | depends on CPU_V7 | |
814 | help | |
815 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
816 | r3p*) erratum. A speculative memory access may cause a page table walk | |
817 | which starts prior to an ASID switch but completes afterwards. This | |
818 | can populate the micro-TLB with a stale entry which may be hit with | |
819 | the new ASID. This workaround places two dsb instructions in the mm | |
820 | switching code so that no page table walks can cross the ASID switch. | |
821 | ||
5dab26af WD |
822 | config ARM_ERRATA_754327 |
823 | bool "ARM errata: no automatic Store Buffer drain" | |
824 | depends on CPU_V7 && SMP | |
825 | help | |
826 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
827 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
828 | mechanism and therefore a livelock may occur if an external agent | |
829 | continuously polls a memory location waiting to observe an update. | |
830 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
831 | written polling loops from denying visibility of updates to memory. | |
832 | ||
145e10e1 CM |
833 | config ARM_ERRATA_364296 |
834 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 835 | depends on CPU_V6 |
145e10e1 CM |
836 | help |
837 | This options enables the workaround for the 364296 ARM1136 | |
838 | r0p2 erratum (possible cache data corruption with | |
839 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
840 | the auxiliary control register and the FI bit in the control | |
841 | register, thus disabling hit-under-miss without putting the | |
842 | processor into full low interrupt latency mode. ARM11MPCore | |
843 | is not affected. | |
844 | ||
f630c1bd WD |
845 | config ARM_ERRATA_764369 |
846 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
847 | depends on CPU_V7 && SMP | |
848 | help | |
849 | This option enables the workaround for erratum 764369 | |
850 | affecting Cortex-A9 MPCore with two or more processors (all | |
851 | current revisions). Under certain timing circumstances, a data | |
852 | cache line maintenance operation by MVA targeting an Inner | |
853 | Shareable memory region may fail to proceed up to either the | |
854 | Point of Coherency or to the Point of Unification of the | |
855 | system. This workaround adds a DSB instruction before the | |
856 | relevant cache maintenance functions and sets a specific bit | |
857 | in the diagnostic control register of the SCU. | |
858 | ||
8294fec1 NH |
859 | config ARM_ERRATA_764319 |
860 | bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" | |
861 | depends on CPU_V7 | |
862 | help | |
863 | This option enables the workaround for the 764319 Cortex A-9 erratum. | |
864 | CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an | |
865 | unexpected Undefined Instruction exception when the DBGSWENABLE | |
866 | external pin is set to 0, even when the CP14 accesses are performed | |
867 | from a privileged mode. This work around catches the exception in a | |
868 | way the kernel does not stop execution. | |
869 | ||
7253b85c SH |
870 | config ARM_ERRATA_775420 |
871 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
872 | depends on CPU_V7 | |
873 | help | |
874 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
cb73737e | 875 | r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance |
7253b85c SH |
876 | operation aborts with MMU exception, it might cause the processor |
877 | to deadlock. This workaround puts DSB before executing ISB if | |
878 | an abort may occur on cache maintenance. | |
879 | ||
93dc6887 CM |
880 | config ARM_ERRATA_798181 |
881 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
882 | depends on CPU_V7 && SMP | |
883 | help | |
884 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
885 | adequately shooting down all use of the old entries. This | |
886 | option enables the Linux kernel workaround for this erratum | |
887 | which sends an IPI to the CPUs that are running the same ASID | |
888 | as the one being invalidated. | |
889 | ||
84b6504f WD |
890 | config ARM_ERRATA_773022 |
891 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
892 | depends on CPU_V7 | |
893 | help | |
894 | This option enables the workaround for the 773022 Cortex-A15 | |
895 | (up to r0p4) erratum. In certain rare sequences of code, the | |
896 | loop buffer may deliver incorrect instructions. This | |
897 | workaround disables the loop buffer to avoid the erratum. | |
898 | ||
62c0f4a5 DA |
899 | config ARM_ERRATA_818325_852422 |
900 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
901 | depends on CPU_V7 | |
902 | help | |
903 | This option enables the workaround for: | |
904 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
905 | instruction might deadlock. Fixed in r0p1. | |
906 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
907 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
908 | any Cortex-A12 cores yet. | |
909 | This workaround for all both errata involves setting bit[12] of the | |
910 | Feature Register. This bit disables an optimisation applied to a | |
911 | sequence of 2 instructions that use opposing condition codes. | |
912 | ||
416bcf21 DA |
913 | config ARM_ERRATA_821420 |
914 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
915 | depends on CPU_V7 | |
916 | help | |
917 | This option enables the workaround for the 821420 Cortex-A12 | |
918 | (all revs) erratum. In very rare timing conditions, a sequence | |
919 | of VMOV to Core registers instructions, for which the second | |
920 | one is in the shadow of a branch or abort, can lead to a | |
921 | deadlock when the VMOV instructions are issued out-of-order. | |
922 | ||
9f6f9354 DA |
923 | config ARM_ERRATA_825619 |
924 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
925 | depends on CPU_V7 | |
926 | help | |
927 | This option enables the workaround for the 825619 Cortex-A12 | |
928 | (all revs) erratum. Within rare timing constraints, executing a | |
929 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
930 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
931 | ||
304009a1 DA |
932 | config ARM_ERRATA_857271 |
933 | bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" | |
934 | depends on CPU_V7 | |
935 | help | |
936 | This option enables the workaround for the 857271 Cortex-A12 | |
937 | (all revs) erratum. Under very rare timing conditions, the CPU might | |
938 | hang. The workaround is expected to have a < 1% performance impact. | |
939 | ||
9f6f9354 DA |
940 | config ARM_ERRATA_852421 |
941 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
942 | depends on CPU_V7 | |
943 | help | |
944 | This option enables the workaround for the 852421 Cortex-A17 | |
945 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
946 | execution of a DMB ST instruction might fail to properly order | |
947 | stores from GroupA and stores from GroupB. | |
948 | ||
62c0f4a5 DA |
949 | config ARM_ERRATA_852423 |
950 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
951 | depends on CPU_V7 | |
952 | help | |
953 | This option enables the workaround for: | |
954 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
955 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
956 | any Cortex-A17 cores yet. | |
957 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
958 | config option from the A12 erratum due to the way errata are checked | |
959 | for and handled. | |
960 | ||
304009a1 DA |
961 | config ARM_ERRATA_857272 |
962 | bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" | |
963 | depends on CPU_V7 | |
964 | help | |
965 | This option enables the workaround for the 857272 Cortex-A17 erratum. | |
966 | This erratum is not known to be fixed in any A17 revision. | |
967 | This is identical to Cortex-A12 erratum 857271. It is a separate | |
968 | config option from the A12 erratum due to the way errata are checked | |
969 | for and handled. | |
970 | ||
1da177e4 LT |
971 | endmenu |
972 | ||
973 | source "arch/arm/common/Kconfig" | |
974 | ||
1da177e4 LT |
975 | menu "Bus support" |
976 | ||
1da177e4 LT |
977 | config ISA |
978 | bool | |
1da177e4 LT |
979 | help |
980 | Find out whether you have ISA slots on your motherboard. ISA is the | |
981 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
982 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
983 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
984 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
985 | ||
065909b9 | 986 | # Select ISA DMA controller support |
1da177e4 LT |
987 | config ISA_DMA |
988 | bool | |
065909b9 | 989 | select ISA_DMA_API |
1da177e4 | 990 | |
065909b9 | 991 | # Select ISA DMA interface |
5cae841b AV |
992 | config ISA_DMA_API |
993 | bool | |
5cae841b | 994 | |
b080ac8a MRJ |
995 | config PCI_NANOENGINE |
996 | bool "BSE nanoEngine PCI support" | |
997 | depends on SA1100_NANOENGINE | |
998 | help | |
999 | Enable PCI on the BSE nanoEngine board. | |
1000 | ||
779eb41c BG |
1001 | config ARM_ERRATA_814220 |
1002 | bool "ARM errata: Cache maintenance by set/way operations can execute out of order" | |
1003 | depends on CPU_V7 | |
1004 | help | |
1005 | The v7 ARM states that all cache and branch predictor maintenance | |
1006 | operations that do not specify an address execute, relative to | |
1007 | each other, in program order. | |
1008 | However, because of this erratum, an L2 set/way cache maintenance | |
1009 | operation can overtake an L1 set/way cache maintenance operation. | |
1010 | This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, | |
1011 | r0p4, r0p5. | |
1012 | ||
1da177e4 LT |
1013 | endmenu |
1014 | ||
1015 | menu "Kernel Features" | |
1016 | ||
3b55658a DM |
1017 | config HAVE_SMP |
1018 | bool | |
1019 | help | |
1020 | This option should be selected by machines which have an SMP- | |
1021 | capable CPU. | |
1022 | ||
1023 | The only effect of this option is to make the SMP-related | |
1024 | options available to the user for configuration. | |
1025 | ||
1da177e4 | 1026 | config SMP |
bb2d8130 | 1027 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1028 | depends on CPU_V6K || CPU_V7 |
3b55658a | 1029 | depends on HAVE_SMP |
801bb21c | 1030 | depends on MMU || ARM_MPU |
0361748f | 1031 | select IRQ_WORK |
1da177e4 LT |
1032 | help |
1033 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1034 | a system with only one CPU, say N. If you have a system with more |
1035 | than one CPU, say Y. | |
1da177e4 | 1036 | |
4a474157 | 1037 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1038 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1039 | you say Y here, the kernel will run on many, but not all, |
1040 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1041 | will run faster if you say N here. | |
1da177e4 | 1042 | |
cb1aaebe | 1043 | See also <file:Documentation/x86/i386/IO-APIC.rst>, |
4f4cfa6c | 1044 | <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at |
50a23e6e | 1045 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1046 | |
1047 | If you don't know what to do here, say N. | |
1048 | ||
f00ec48f | 1049 | config SMP_ON_UP |
5744ff43 | 1050 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1051 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1052 | default y |
1053 | help | |
1054 | SMP kernels contain instructions which fail on non-SMP processors. | |
1055 | Enabling this option allows the kernel to modify itself to make | |
1056 | these instructions safe. Disabling it allows about 1K of space | |
1057 | savings. | |
1058 | ||
1059 | If you don't know what to do here, say Y. | |
1060 | ||
50596b75 AB |
1061 | |
1062 | config CURRENT_POINTER_IN_TPIDRURO | |
1063 | def_bool y | |
b87cf911 | 1064 | depends on CPU_32v6K && !CPU_V6 |
50596b75 | 1065 | |
d4664b6c AB |
1066 | config IRQSTACKS |
1067 | def_bool y | |
9974f857 AB |
1068 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
1069 | select HAVE_SOFTIRQ_ON_OWN_STACK | |
50596b75 | 1070 | |
c9018aab VG |
1071 | config ARM_CPU_TOPOLOGY |
1072 | bool "Support cpu topology definition" | |
1073 | depends on SMP && CPU_V7 | |
1074 | default y | |
1075 | help | |
1076 | Support ARM cpu topology definition. The MPIDR register defines | |
1077 | affinity between processors which is then used to describe the cpu | |
1078 | topology of an ARM System. | |
1079 | ||
1080 | config SCHED_MC | |
1081 | bool "Multi-core scheduler support" | |
1082 | depends on ARM_CPU_TOPOLOGY | |
1083 | help | |
1084 | Multi-core scheduler support improves the CPU scheduler's decision | |
1085 | making when dealing with multi-core CPU chips at a cost of slightly | |
1086 | increased overhead in some places. If unsure say N here. | |
1087 | ||
1088 | config SCHED_SMT | |
1089 | bool "SMT scheduler support" | |
1090 | depends on ARM_CPU_TOPOLOGY | |
1091 | help | |
1092 | Improves the CPU scheduler's decision making when dealing with | |
1093 | MultiThreading at a cost of slightly increased overhead in some | |
1094 | places. If unsure say N here. | |
1095 | ||
a8cbcd92 RK |
1096 | config HAVE_ARM_SCU |
1097 | bool | |
a8cbcd92 | 1098 | help |
8f433ec4 | 1099 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 1100 | |
8a4da6e3 | 1101 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1102 | bool "Architected timer support" |
1103 | depends on CPU_V7 | |
8a4da6e3 | 1104 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1105 | help |
1106 | This option enables support for the ARM architected timer | |
1107 | ||
f32f4ce2 RK |
1108 | config HAVE_ARM_TWD |
1109 | bool | |
f32f4ce2 RK |
1110 | help |
1111 | This options enables support for the ARM timer and watchdog unit | |
1112 | ||
e8db288e NP |
1113 | config MCPM |
1114 | bool "Multi-Cluster Power Management" | |
1115 | depends on CPU_V7 && SMP | |
1116 | help | |
1117 | This option provides the common power management infrastructure | |
1118 | for (multi-)cluster based systems, such as big.LITTLE based | |
1119 | systems. | |
1120 | ||
ebf4a5c5 HZ |
1121 | config MCPM_QUAD_CLUSTER |
1122 | bool | |
1123 | depends on MCPM | |
1124 | help | |
1125 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1126 | to 2 clusters by default. | |
1127 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1128 | option to allow the additional clusters to be managed. | |
1129 | ||
1c33be57 NP |
1130 | config BIG_LITTLE |
1131 | bool "big.LITTLE support (Experimental)" | |
1132 | depends on CPU_V7 && SMP | |
1133 | select MCPM | |
1134 | help | |
1135 | This option enables support selections for the big.LITTLE | |
1136 | system architecture. | |
1137 | ||
1138 | config BL_SWITCHER | |
1139 | bool "big.LITTLE switcher support" | |
6c044fec | 1140 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1141 | select CPU_PM |
1c33be57 NP |
1142 | help |
1143 | The big.LITTLE "switcher" provides the core functionality to | |
1144 | transparently handle transition between a cluster of A15's | |
1145 | and a cluster of A7's in a big.LITTLE system. | |
1146 | ||
b22537c6 NP |
1147 | config BL_SWITCHER_DUMMY_IF |
1148 | tristate "Simple big.LITTLE switcher user interface" | |
1149 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1150 | help | |
1151 | This is a simple and dummy char dev interface to control | |
1152 | the big.LITTLE switcher core code. It is meant for | |
1153 | debugging purposes only. | |
1154 | ||
8d5796d2 LB |
1155 | choice |
1156 | prompt "Memory split" | |
006fa259 | 1157 | depends on MMU |
8d5796d2 LB |
1158 | default VMSPLIT_3G |
1159 | help | |
1160 | Select the desired split between kernel and user memory. | |
1161 | ||
1162 | If you are not absolutely sure what you are doing, leave this | |
1163 | option alone! | |
1164 | ||
1165 | config VMSPLIT_3G | |
1166 | bool "3G/1G user/kernel split" | |
63ce446c | 1167 | config VMSPLIT_3G_OPT |
bbeedfda | 1168 | depends on !ARM_LPAE |
63ce446c | 1169 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1170 | config VMSPLIT_2G |
1171 | bool "2G/2G user/kernel split" | |
1172 | config VMSPLIT_1G | |
1173 | bool "1G/3G user/kernel split" | |
1174 | endchoice | |
1175 | ||
1176 | config PAGE_OFFSET | |
1177 | hex | |
006fa259 | 1178 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1179 | default 0x40000000 if VMSPLIT_1G |
1180 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1181 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1182 | default 0xC0000000 |
1183 | ||
c12366ba LW |
1184 | config KASAN_SHADOW_OFFSET |
1185 | hex | |
1186 | depends on KASAN | |
1187 | default 0x1f000000 if PAGE_OFFSET=0x40000000 | |
1188 | default 0x5f000000 if PAGE_OFFSET=0x80000000 | |
1189 | default 0x9f000000 if PAGE_OFFSET=0xC0000000 | |
1190 | default 0x8f000000 if PAGE_OFFSET=0xB0000000 | |
1191 | default 0xffffffff | |
1192 | ||
1da177e4 LT |
1193 | config NR_CPUS |
1194 | int "Maximum number of CPUs (2-32)" | |
d624833f AB |
1195 | range 2 16 if DEBUG_KMAP_LOCAL |
1196 | range 2 32 if !DEBUG_KMAP_LOCAL | |
1da177e4 LT |
1197 | depends on SMP |
1198 | default "4" | |
d624833f AB |
1199 | help |
1200 | The maximum number of CPUs that the kernel can support. | |
1201 | Up to 32 CPUs can be supported, or up to 16 if kmap_local() | |
1202 | debugging is enabled, which uses half of the per-CPU fixmap | |
1203 | slots as guard regions. | |
1da177e4 | 1204 | |
a054a811 | 1205 | config HOTPLUG_CPU |
00b7dede | 1206 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1207 | depends on SMP |
1b5ba350 | 1208 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1209 | help |
1210 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1211 | can be controlled through /sys/devices/system/cpu. | |
1212 | ||
2bdd424f WD |
1213 | config ARM_PSCI |
1214 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1215 | depends on HAVE_ARM_SMCCC |
be120397 | 1216 | select ARM_PSCI_FW |
2bdd424f WD |
1217 | help |
1218 | Say Y here if you want Linux to communicate with system firmware | |
1219 | implementing the PSCI specification for CPU-centric power | |
1220 | management operations described in ARM document number ARM DEN | |
1221 | 0022A ("Power State Coordination Interface System Software on | |
1222 | ARM processors"). | |
1223 | ||
2a6ad871 MR |
1224 | # The GPIO number here must be sorted by descending number. In case of |
1225 | # a multiplatform kernel, we just want the highest value required by the | |
1226 | # selected platforms. | |
44986ab0 PDSN |
1227 | config ARCH_NR_GPIO |
1228 | int | |
910499e1 | 1229 | default 2048 if ARCH_INTEL_SOCFPGA |
d9be9ceb | 1230 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
a3ee4fea | 1231 | ARCH_ZYNQ || ARCH_ASPEED |
aa42587a TF |
1232 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1233 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1234 | default 416 if ARCH_SUNXI |
06b851e5 | 1235 | default 392 if ARCH_U8500 |
01bb914c | 1236 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1237 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1238 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1239 | default 0 |
1240 | help | |
1241 | Maximum number of GPIOs in the system. | |
1242 | ||
1243 | If unsure, leave the default value. | |
1244 | ||
c9218b16 | 1245 | config HZ_FIXED |
f8065813 | 1246 | int |
1164f672 | 1247 | default 128 if SOC_AT91RM9200 |
47d84682 | 1248 | default 0 |
c9218b16 RK |
1249 | |
1250 | choice | |
47d84682 | 1251 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1252 | prompt "Timer frequency" |
1253 | ||
1254 | config HZ_100 | |
1255 | bool "100 Hz" | |
1256 | ||
1257 | config HZ_200 | |
1258 | bool "200 Hz" | |
1259 | ||
1260 | config HZ_250 | |
1261 | bool "250 Hz" | |
1262 | ||
1263 | config HZ_300 | |
1264 | bool "300 Hz" | |
1265 | ||
1266 | config HZ_500 | |
1267 | bool "500 Hz" | |
1268 | ||
1269 | config HZ_1000 | |
1270 | bool "1000 Hz" | |
1271 | ||
1272 | endchoice | |
1273 | ||
1274 | config HZ | |
1275 | int | |
47d84682 | 1276 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1277 | default 100 if HZ_100 |
1278 | default 200 if HZ_200 | |
1279 | default 250 if HZ_250 | |
1280 | default 300 if HZ_300 | |
1281 | default 500 if HZ_500 | |
1282 | default 1000 | |
1283 | ||
1284 | config SCHED_HRTICK | |
1285 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1286 | |
16c79651 | 1287 | config THUMB2_KERNEL |
bc7dea00 | 1288 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1289 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1290 | default y if CPU_THUMBONLY |
89bace65 | 1291 | select ARM_UNWIND |
16c79651 CM |
1292 | help |
1293 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1294 | Thumb-2 mode. |
16c79651 CM |
1295 | |
1296 | If unsure, say N. | |
1297 | ||
42f25bdd NP |
1298 | config ARM_PATCH_IDIV |
1299 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1300 | depends on CPU_32v7 && !XIP_KERNEL | |
1301 | default y | |
1302 | help | |
1303 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1304 | __aeabi_uidiv() when it needs to perform division on signed | |
1305 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1306 | and udiv instructions that can be used to implement those | |
1307 | functions. | |
1308 | ||
1309 | Enabling this option allows the kernel to modify itself to | |
1310 | replace the first two instructions of these library functions | |
1311 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1312 | it is running on supports them. Typically this will be faster | |
1313 | and less power intensive than running the original library | |
1314 | code to do integer division. | |
1315 | ||
704bdda0 | 1316 | config AEABI |
a05b9608 ND |
1317 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ |
1318 | !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG | |
1319 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG | |
704bdda0 NP |
1320 | help |
1321 | This option allows for the kernel to be compiled using the latest | |
1322 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1323 | space environment that is also compiled with EABI. | |
1324 | ||
1325 | Since there are major incompatibilities between the legacy ABI and | |
1326 | EABI, especially with regard to structure member alignment, this | |
1327 | option also changes the kernel syscall calling convention to | |
1328 | disambiguate both ABIs and allow for backward compatibility support | |
1329 | (selected with CONFIG_OABI_COMPAT). | |
1330 | ||
1331 | To use this you need GCC version 4.0.0 or later. | |
1332 | ||
6c90c872 | 1333 | config OABI_COMPAT |
a73a3ff1 | 1334 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1335 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1336 | help |
1337 | This option preserves the old syscall interface along with the | |
1338 | new (ARM EABI) one. It also provides a compatibility layer to | |
1339 | intercept syscalls that have structure arguments which layout | |
1340 | in memory differs between the legacy ABI and the new ARM EABI | |
1341 | (only for non "thumb" binaries). This option adds a tiny | |
1342 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1343 | |
1344 | The seccomp filter system will not be available when this is | |
1345 | selected, since there is no way yet to sensibly distinguish | |
1346 | between calling conventions during filtering. | |
1347 | ||
6c90c872 NP |
1348 | If you know you'll be using only pure EABI user space then you |
1349 | can say N here. If this option is not selected and you attempt | |
1350 | to execute a legacy ABI binary then the result will be | |
1351 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1352 | at all). If in doubt say N. |
6c90c872 | 1353 | |
fb597f2a GF |
1354 | config ARCH_SELECT_MEMORY_MODEL |
1355 | bool | |
1356 | ||
1357 | config ARCH_FLATMEM_ENABLE | |
05944d74 RK |
1358 | bool |
1359 | ||
05944d74 RK |
1360 | config ARCH_SPARSEMEM_ENABLE |
1361 | bool | |
fb597f2a | 1362 | select SPARSEMEM_STATIC if SPARSEMEM |
07a2f737 | 1363 | |
053a96ca | 1364 | config HIGHMEM |
e8db89a2 RK |
1365 | bool "High Memory Support" |
1366 | depends on MMU | |
2a15ba82 | 1367 | select KMAP_LOCAL |
825c43f5 | 1368 | select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY |
053a96ca NP |
1369 | help |
1370 | The address space of ARM processors is only 4 Gigabytes large | |
1371 | and it has to accommodate user address space, kernel address | |
1372 | space as well as some memory mapped IO. That means that, if you | |
1373 | have a large amount of physical memory and/or IO, not all of the | |
1374 | memory can be "permanently mapped" by the kernel. The physical | |
1375 | memory that is not permanently mapped is called "high memory". | |
1376 | ||
1377 | Depending on the selected kernel/user memory split, minimum | |
1378 | vmalloc space and actual amount of RAM, you may not need this | |
1379 | option which should result in a slightly faster kernel. | |
1380 | ||
1381 | If unsure, say n. | |
1382 | ||
65cec8e3 | 1383 | config HIGHPTE |
9a431bd5 | 1384 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1385 | depends on HIGHMEM |
9a431bd5 | 1386 | default y |
b4d103d1 RK |
1387 | help |
1388 | The VM uses one page of physical memory for each page table. | |
1389 | For systems with a lot of processes, this can use a lot of | |
1390 | precious low memory, eventually leading to low memory being | |
1391 | consumed by page tables. Setting this option will allow | |
1392 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1393 | |
a5e090ac RK |
1394 | config CPU_SW_DOMAIN_PAN |
1395 | bool "Enable use of CPU domains to implement privileged no-access" | |
1396 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1397 | default y |
1398 | help | |
a5e090ac RK |
1399 | Increase kernel security by ensuring that normal kernel accesses |
1400 | are unable to access userspace addresses. This can help prevent | |
1401 | use-after-free bugs becoming an exploitable privilege escalation | |
1402 | by ensuring that magic values (such as LIST_POISON) will always | |
1403 | fault when dereferenced. | |
1404 | ||
1405 | CPUs with low-vector mappings use a best-efforts implementation. | |
1406 | Their lower 1MB needs to remain accessible for the vectors, but | |
1407 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1408 | |
1b8873a0 | 1409 | config HW_PERF_EVENTS |
fa8ad788 MR |
1410 | def_bool y |
1411 | depends on ARM_PMU | |
1b8873a0 | 1412 | |
7d485f64 AB |
1413 | config ARM_MODULE_PLTS |
1414 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1415 | depends on MODULES | |
e7229f7d | 1416 | default y |
7d485f64 AB |
1417 | help |
1418 | Allocate PLTs when loading modules so that jumps and calls whose | |
1419 | targets are too far away for their relative offsets to be encoded | |
1420 | in the instructions themselves can be bounced via veneers in the | |
1421 | module's PLT. This allows modules to be allocated in the generic | |
1422 | vmalloc area after the dedicated module memory area has been | |
1423 | exhausted. The modules will use slightly more memory, but after | |
1424 | rounding up to page size, the actual memory footprint is usually | |
1425 | the same. | |
1426 | ||
e7229f7d AR |
1427 | Disabling this is usually safe for small single-platform |
1428 | configurations. If unsure, say y. | |
7d485f64 | 1429 | |
c1b2d970 | 1430 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1431 | int "Maximum zone order" |
898f08e1 | 1432 | default "12" if SOC_AM33XX |
cc611137 | 1433 | default "9" if SA1111 |
c1b2d970 MD |
1434 | default "11" |
1435 | help | |
1436 | The kernel memory allocator divides physically contiguous memory | |
1437 | blocks into "zones", where each zone is a power of two number of | |
1438 | pages. This option selects the largest power of two that the kernel | |
1439 | keeps in the memory allocator. If you need to allocate very large | |
1440 | blocks of physically contiguous memory, then you may need to | |
1441 | increase this value. | |
1442 | ||
1443 | This config option is actually maximum order plus one. For example, | |
1444 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1445 | ||
1da177e4 | 1446 | config ALIGNMENT_TRAP |
3e3f354b | 1447 | def_bool CPU_CP15_MMU |
e119bfff | 1448 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1449 | help |
84eb8d06 | 1450 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1451 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1452 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1453 | fetch/store instructions will be emulated in software if you say | |
1454 | here, which has a severe performance impact. This is necessary for | |
1455 | correct operation of some network protocols. With an IP-only | |
1456 | configuration it is safe to say N, otherwise say Y. | |
1457 | ||
39ec58f3 | 1458 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1459 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1460 | depends on MMU | |
39ec58f3 LB |
1461 | default y if CPU_FEROCEON |
1462 | help | |
1463 | Implement faster copy_to_user and clear_user methods for CPU | |
1464 | cores where a 8-word STM instruction give significantly higher | |
1465 | memory write throughput than a sequence of individual 32bit stores. | |
1466 | ||
1467 | A possible side effect is a slight increase in scheduling latency | |
1468 | between threads sharing the same address space if they invoke | |
1469 | such copy operations with large buffers. | |
1470 | ||
1471 | However, if the CPU data cache is using a write-allocate mode, | |
1472 | this option is unlikely to provide any performance gain. | |
1473 | ||
02c2433b SS |
1474 | config PARAVIRT |
1475 | bool "Enable paravirtualization code" | |
1476 | help | |
1477 | This changes the kernel so it can modify itself when it is run | |
1478 | under a hypervisor, potentially improving performance significantly | |
1479 | over full virtualization. | |
1480 | ||
1481 | config PARAVIRT_TIME_ACCOUNTING | |
1482 | bool "Paravirtual steal time accounting" | |
1483 | select PARAVIRT | |
02c2433b SS |
1484 | help |
1485 | Select this option to enable fine granularity task steal time | |
1486 | accounting. Time spent executing other tasks in parallel with | |
1487 | the current vCPU is discounted from the vCPU power. To account for | |
1488 | that, there can be a small performance impact. | |
1489 | ||
1490 | If in doubt, say N here. | |
1491 | ||
eff8d644 SS |
1492 | config XEN_DOM0 |
1493 | def_bool y | |
1494 | depends on XEN | |
1495 | ||
1496 | config XEN | |
c2ba1f7d | 1497 | bool "Xen guest support on ARM" |
85323a99 | 1498 | depends on ARM && AEABI && OF |
f880b67d | 1499 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1500 | depends on !GENERIC_ATOMIC64 |
7693decc | 1501 | depends on MMU |
51aaf81f | 1502 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1503 | select ARM_PSCI |
f21254cd | 1504 | select SWIOTLB |
83862ccf | 1505 | select SWIOTLB_XEN |
02c2433b | 1506 | select PARAVIRT |
eff8d644 SS |
1507 | help |
1508 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1509 | ||
f05eb1d2 AB |
1510 | config CC_HAVE_STACKPROTECTOR_TLS |
1511 | def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) | |
1512 | ||
189af465 AB |
1513 | config STACKPROTECTOR_PER_TASK |
1514 | bool "Use a unique stack canary value for each task" | |
9c46929e | 1515 | depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA |
f05eb1d2 AB |
1516 | depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS |
1517 | select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS | |
189af465 AB |
1518 | default y |
1519 | help | |
1520 | Due to the fact that GCC uses an ordinary symbol reference from | |
1521 | which to load the value of the stack canary, this value can only | |
1522 | change at reboot time on SMP systems, and all tasks running in the | |
1523 | kernel's address space are forced to use the same canary value for | |
1524 | the entire duration that the system is up. | |
1525 | ||
1526 | Enable this option to switch to a different method that uses a | |
1527 | different canary value for each task. | |
1528 | ||
1da177e4 LT |
1529 | endmenu |
1530 | ||
1531 | menu "Boot options" | |
1532 | ||
9eb8f674 GL |
1533 | config USE_OF |
1534 | bool "Flattened Device Tree support" | |
b1b3f49c | 1535 | select IRQ_DOMAIN |
9eb8f674 | 1536 | select OF |
9eb8f674 GL |
1537 | help |
1538 | Include support for flattened device tree machine descriptions. | |
1539 | ||
bd51e2f5 NP |
1540 | config ATAGS |
1541 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1542 | default y | |
1543 | help | |
1544 | This is the traditional way of passing data to the kernel at boot | |
1545 | time. If you are solely relying on the flattened device tree (or | |
1546 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1547 | to remove ATAGS support from your kernel binary. If unsure, | |
1548 | leave this to y. | |
1549 | ||
1550 | config DEPRECATED_PARAM_STRUCT | |
1551 | bool "Provide old way to pass kernel parameters" | |
1552 | depends on ATAGS | |
1553 | help | |
1554 | This was deprecated in 2001 and announced to live on for 5 years. | |
1555 | Some old boot loaders still use this way. | |
1556 | ||
1da177e4 LT |
1557 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1558 | # TEXT and BSS so we preserve their values in the config files. | |
1559 | config ZBOOT_ROM_TEXT | |
1560 | hex "Compressed ROM boot loader base address" | |
39c3e304 | 1561 | default 0x0 |
1da177e4 LT |
1562 | help |
1563 | The physical address at which the ROM-able zImage is to be | |
1564 | placed in the target. Platforms which normally make use of | |
1565 | ROM-able zImage formats normally set this to a suitable | |
1566 | value in their defconfig file. | |
1567 | ||
1568 | If ZBOOT_ROM is not enabled, this has no effect. | |
1569 | ||
1570 | config ZBOOT_ROM_BSS | |
1571 | hex "Compressed ROM boot loader BSS address" | |
39c3e304 | 1572 | default 0x0 |
1da177e4 | 1573 | help |
f8c440b2 DF |
1574 | The base address of an area of read/write memory in the target |
1575 | for the ROM-able zImage which must be available while the | |
1576 | decompressor is running. It must be large enough to hold the | |
1577 | entire decompressed kernel plus an additional 128 KiB. | |
1578 | Platforms which normally make use of ROM-able zImage formats | |
1579 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1580 | |
1581 | If ZBOOT_ROM is not enabled, this has no effect. | |
1582 | ||
1583 | config ZBOOT_ROM | |
1584 | bool "Compressed boot loader in ROM/flash" | |
1585 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1586 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1587 | help |
1588 | Say Y here if you intend to execute your compressed kernel image | |
1589 | (zImage) directly from ROM or flash. If unsure, say N. | |
1590 | ||
e2a6a3aa JB |
1591 | config ARM_APPENDED_DTB |
1592 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1593 | depends on OF |
e2a6a3aa JB |
1594 | help |
1595 | With this option, the boot code will look for a device tree binary | |
1596 | (DTB) appended to zImage | |
1597 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1598 | ||
1599 | This is meant as a backward compatibility convenience for those | |
1600 | systems with a bootloader that can't be upgraded to accommodate | |
1601 | the documented boot protocol using a device tree. | |
1602 | ||
1603 | Beware that there is very little in terms of protection against | |
1604 | this option being confused by leftover garbage in memory that might | |
1605 | look like a DTB header after a reboot if no actual DTB is appended | |
1606 | to zImage. Do not leave this option active in a production kernel | |
1607 | if you don't intend to always append a DTB. Proper passing of the | |
1608 | location into r2 of a bootloader provided DTB is always preferable | |
1609 | to this option. | |
1610 | ||
b90b9a38 NP |
1611 | config ARM_ATAG_DTB_COMPAT |
1612 | bool "Supplement the appended DTB with traditional ATAG information" | |
1613 | depends on ARM_APPENDED_DTB | |
1614 | help | |
1615 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1616 | they provide ATAGs with memory configuration, the ramdisk address, | |
1617 | the kernel cmdline string, etc. Such information is dynamically | |
1618 | provided by the bootloader and can't always be stored in a static | |
1619 | DTB. To allow a device tree enabled kernel to be used with such | |
1620 | bootloaders, this option allows zImage to extract the information | |
1621 | from the ATAG list and store it at run time into the appended DTB. | |
1622 | ||
d0f34a11 GR |
1623 | choice |
1624 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1625 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1626 | ||
1627 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1628 | bool "Use bootloader kernel arguments if available" | |
1629 | help | |
1630 | Uses the command-line options passed by the boot loader instead of | |
1631 | the device tree bootargs property. If the boot loader doesn't provide | |
1632 | any, the device tree bootargs property will be used. | |
1633 | ||
1634 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1635 | bool "Extend with bootloader kernel arguments" | |
1636 | help | |
1637 | The command-line arguments provided by the boot loader will be | |
1638 | appended to the the device tree bootargs property. | |
1639 | ||
1640 | endchoice | |
1641 | ||
1da177e4 LT |
1642 | config CMDLINE |
1643 | string "Default kernel command string" | |
1644 | default "" | |
1645 | help | |
3e3f354b | 1646 | On some architectures (e.g. CATS), there is currently no way |
1da177e4 LT |
1647 | for the boot loader to pass arguments to the kernel. For these |
1648 | architectures, you should supply some command-line options at build | |
1649 | time by entering them here. As a minimum, you should specify the | |
1650 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1651 | ||
4394c124 VB |
1652 | choice |
1653 | prompt "Kernel command line type" if CMDLINE != "" | |
1654 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1655 | depends on ATAGS |
4394c124 VB |
1656 | |
1657 | config CMDLINE_FROM_BOOTLOADER | |
1658 | bool "Use bootloader kernel arguments if available" | |
1659 | help | |
1660 | Uses the command-line options passed by the boot loader. If | |
1661 | the boot loader doesn't provide any, the default kernel command | |
1662 | string provided in CMDLINE will be used. | |
1663 | ||
1664 | config CMDLINE_EXTEND | |
1665 | bool "Extend bootloader kernel arguments" | |
1666 | help | |
1667 | The command-line arguments provided by the boot loader will be | |
1668 | appended to the default kernel command string. | |
1669 | ||
92d2040d AH |
1670 | config CMDLINE_FORCE |
1671 | bool "Always use the default kernel command string" | |
92d2040d AH |
1672 | help |
1673 | Always use the default kernel command string, even if the boot | |
1674 | loader passes other arguments to the kernel. | |
1675 | This is useful if you cannot or don't want to change the | |
1676 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1677 | endchoice |
92d2040d | 1678 | |
1da177e4 LT |
1679 | config XIP_KERNEL |
1680 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1681 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1682 | help |
1683 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1684 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1685 | space since the text section of the kernel is not loaded from flash | |
1686 | to RAM. Read-write sections, such as the data section and stack, | |
1687 | are still copied to RAM. The XIP kernel is not compressed since | |
1688 | it has to run directly from flash, so it will take more space to | |
1689 | store it. The flash address used to link the kernel object files, | |
1690 | and for storing it, is configuration dependent. Therefore, if you | |
1691 | say Y here, you must know the proper physical address where to | |
1692 | store the kernel image depending on your own flash memory usage. | |
1693 | ||
1694 | Also note that the make target becomes "make xipImage" rather than | |
1695 | "make zImage" or "make Image". The final kernel binary to put in | |
1696 | ROM memory will be arch/arm/boot/xipImage. | |
1697 | ||
1698 | If unsure, say N. | |
1699 | ||
1700 | config XIP_PHYS_ADDR | |
1701 | hex "XIP Kernel Physical Location" | |
1702 | depends on XIP_KERNEL | |
1703 | default "0x00080000" | |
1704 | help | |
1705 | This is the physical address in your flash memory the kernel will | |
1706 | be linked for and stored to. This address is dependent on your | |
1707 | own flash usage. | |
1708 | ||
ca8b5d97 NP |
1709 | config XIP_DEFLATED_DATA |
1710 | bool "Store kernel .data section compressed in ROM" | |
1711 | depends on XIP_KERNEL | |
1712 | select ZLIB_INFLATE | |
1713 | help | |
1714 | Before the kernel is actually executed, its .data section has to be | |
1715 | copied to RAM from ROM. This option allows for storing that data | |
1716 | in compressed form and decompressed to RAM rather than merely being | |
1717 | copied, saving some precious ROM space. A possible drawback is a | |
1718 | slightly longer boot delay. | |
1719 | ||
c587e4a6 RP |
1720 | config KEXEC |
1721 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1722 | depends on (!SMP || PM_SLEEP_SMP) |
76950f71 | 1723 | depends on MMU |
2965faa5 | 1724 | select KEXEC_CORE |
c587e4a6 RP |
1725 | help |
1726 | kexec is a system call that implements the ability to shutdown your | |
1727 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1728 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1729 | you can start any kernel with it, not just Linux. |
1730 | ||
1731 | It is an ongoing process to be certain the hardware in a machine | |
1732 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1733 | initially work for you. |
c587e4a6 | 1734 | |
4cd9d6f7 RP |
1735 | config ATAGS_PROC |
1736 | bool "Export atags in procfs" | |
bd51e2f5 | 1737 | depends on ATAGS && KEXEC |
b98d7291 | 1738 | default y |
4cd9d6f7 RP |
1739 | help |
1740 | Should the atags used to boot the kernel be exported in an "atags" | |
1741 | file in procfs. Useful with kexec. | |
1742 | ||
cb5d39b3 MW |
1743 | config CRASH_DUMP |
1744 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
1745 | help |
1746 | Generate crash dump after being started by kexec. This should | |
1747 | be normally only set in special crash dump kernels which are | |
1748 | loaded in the main kernel with kexec-tools into a specially | |
1749 | reserved region and then later executed after a crash by | |
1750 | kdump/kexec. The crash dump kernel must be compiled to a | |
1751 | memory address not used by the main kernel | |
1752 | ||
330d4810 | 1753 | For more details see Documentation/admin-guide/kdump/kdump.rst |
cb5d39b3 | 1754 | |
e69edc79 EM |
1755 | config AUTO_ZRELADDR |
1756 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
1757 | help |
1758 | ZRELADDR is the physical address where the decompressed kernel | |
1759 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
0673cb38 GU |
1760 | will be determined at run-time, either by masking the current IP |
1761 | with 0xf8000000, or, if invalid, from the DTB passed in r2. | |
1762 | This assumes the zImage being placed in the first 128MB from | |
1763 | start of memory. | |
e69edc79 | 1764 | |
81a0bc39 RF |
1765 | config EFI_STUB |
1766 | bool | |
1767 | ||
1768 | config EFI | |
1769 | bool "UEFI runtime support" | |
1770 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
1771 | select UCS2_STRING | |
1772 | select EFI_PARAMS_FROM_FDT | |
1773 | select EFI_STUB | |
2e0eb483 | 1774 | select EFI_GENERIC_STUB |
81a0bc39 | 1775 | select EFI_RUNTIME_WRAPPERS |
a7f7f624 | 1776 | help |
81a0bc39 RF |
1777 | This option provides support for runtime services provided |
1778 | by UEFI firmware (such as non-volatile variables, realtime | |
1779 | clock, and platform reset). A UEFI stub is also provided to | |
1780 | allow the kernel to be booted as an EFI application. This | |
1781 | is only useful for kernels that may run on systems that have | |
1782 | UEFI firmware. | |
1783 | ||
bb817bef AB |
1784 | config DMI |
1785 | bool "Enable support for SMBIOS (DMI) tables" | |
1786 | depends on EFI | |
1787 | default y | |
1788 | help | |
1789 | This enables SMBIOS/DMI feature for systems. | |
1790 | ||
1791 | This option is only useful on systems that have UEFI firmware. | |
1792 | However, even with this option, the resultant kernel should | |
1793 | continue to boot on existing non-UEFI platforms. | |
1794 | ||
1795 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
1796 | i.e., the the practice of identifying the platform via DMI to | |
1797 | decide whether certain workarounds for buggy hardware and/or | |
1798 | firmware need to be enabled. This would require the DMI subsystem | |
1799 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
1800 | ||
1da177e4 LT |
1801 | endmenu |
1802 | ||
ac9d7efc | 1803 | menu "CPU Power Management" |
1da177e4 | 1804 | |
1da177e4 | 1805 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 1806 | |
ac9d7efc RK |
1807 | source "drivers/cpuidle/Kconfig" |
1808 | ||
1809 | endmenu | |
1810 | ||
1da177e4 LT |
1811 | menu "Floating point emulation" |
1812 | ||
1813 | comment "At least one emulation must be selected" | |
1814 | ||
1815 | config FPE_NWFPE | |
1816 | bool "NWFPE math emulation" | |
593c252a | 1817 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
a7f7f624 | 1818 | help |
1da177e4 LT |
1819 | Say Y to include the NWFPE floating point emulator in the kernel. |
1820 | This is necessary to run most binaries. Linux does not currently | |
1821 | support floating point hardware so you need to say Y here even if | |
1822 | your machine has an FPA or floating point co-processor podule. | |
1823 | ||
1824 | You may say N here if you are going to load the Acorn FPEmulator | |
1825 | early in the bootup. | |
1826 | ||
1827 | config FPE_NWFPE_XP | |
1828 | bool "Support extended precision" | |
bedf142b | 1829 | depends on FPE_NWFPE |
1da177e4 LT |
1830 | help |
1831 | Say Y to include 80-bit support in the kernel floating-point | |
1832 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
1833 | Note that gcc does not generate 80-bit operations by default, | |
1834 | so in most cases this option only enlarges the size of the | |
1835 | floating point emulator without any good reason. | |
1836 | ||
1837 | You almost surely want to say N here. | |
1838 | ||
1839 | config FPE_FASTFPE | |
1840 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 1841 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
a7f7f624 | 1842 | help |
1da177e4 LT |
1843 | Say Y here to include the FAST floating point emulator in the kernel. |
1844 | This is an experimental much faster emulator which now also has full | |
1845 | precision for the mantissa. It does not support any exceptions. | |
1846 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
1847 | ||
1848 | It should be sufficient for most programs. It may be not suitable | |
1849 | for scientific calculations, but you have to check this for yourself. | |
1850 | If you do not feel you need a faster FP emulation you should better | |
1851 | choose NWFPE. | |
1852 | ||
1853 | config VFP | |
1854 | bool "VFP-format floating point maths" | |
e399b1a4 | 1855 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
1856 | help |
1857 | Say Y to include VFP support code in the kernel. This is needed | |
1858 | if your hardware includes a VFP unit. | |
1859 | ||
dc7a12bd | 1860 | Please see <file:Documentation/arm/vfp/release-notes.rst> for |
1da177e4 LT |
1861 | release notes and additional status information. |
1862 | ||
1863 | Say N if your target does not have VFP hardware. | |
1864 | ||
25ebee02 CM |
1865 | config VFPv3 |
1866 | bool | |
1867 | depends on VFP | |
1868 | default y if CPU_V7 | |
1869 | ||
b5872db4 CM |
1870 | config NEON |
1871 | bool "Advanced SIMD (NEON) Extension support" | |
1872 | depends on VFPv3 && CPU_V7 | |
1873 | help | |
1874 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
1875 | Extension. | |
1876 | ||
73c132c1 AB |
1877 | config KERNEL_MODE_NEON |
1878 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 1879 | depends on NEON && AEABI |
73c132c1 AB |
1880 | help |
1881 | Say Y to include support for NEON in kernel mode. | |
1882 | ||
1da177e4 LT |
1883 | endmenu |
1884 | ||
1da177e4 LT |
1885 | menu "Power management options" |
1886 | ||
eceab4ac | 1887 | source "kernel/power/Kconfig" |
1da177e4 | 1888 | |
f4cb5700 | 1889 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 1890 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 1891 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
1892 | def_bool y |
1893 | ||
15e0d9e3 | 1894 | config ARM_CPU_SUSPEND |
8b6f2499 | 1895 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 1896 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 1897 | |
603fb42a SC |
1898 | config ARCH_HIBERNATION_POSSIBLE |
1899 | bool | |
1900 | depends on MMU | |
1901 | default y if ARCH_SUSPEND_POSSIBLE | |
1902 | ||
1da177e4 LT |
1903 | endmenu |
1904 | ||
652ccae5 AB |
1905 | if CRYPTO |
1906 | source "arch/arm/crypto/Kconfig" | |
1907 | endif | |
2cbd1cc3 SA |
1908 | |
1909 | source "arch/arm/Kconfig.assembler" |