Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
fed240d9 | 6 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND |
aef0f78e | 7 | select ARCH_HAS_BINFMT_FLAT |
2792d84e | 8 | select ARCH_HAS_CURRENT_STACK_POINTER |
c7780ab5 | 9 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
419e2f18 | 10 | select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE |
2b68f6ca | 11 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 12 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 13 | select ARCH_HAS_KEEPINITRD |
75851720 | 14 | select ARCH_HAS_KCOV |
e69244d2 | 15 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 16 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
3010a5ea | 17 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
ea8c64ac | 18 | select ARCH_HAS_PHYS_TO_DMA |
347cb6af | 19 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 20 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
21 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
22 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
31b089bb CH |
23 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU |
24 | select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU | |
dc2acded | 25 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 26 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 27 | select ARCH_HAVE_CUSTOM_GPIO_H |
9aaf9bb7 | 28 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K |
957e3fac | 29 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e545df3 | 30 | select ARCH_KEEP_MEMBLOCK |
d7018848 | 31 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7c703e54 | 32 | select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN |
ad21fc4f LA |
33 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
34 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 35 | select ARCH_SUPPORTS_ATOMIC_RMW |
855f9a8e | 36 | select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE |
017f161a | 37 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 38 | select ARCH_USE_CMPXCHG_LOCKREF |
dce44566 | 39 | select ARCH_USE_MEMTEST |
dba79c3d | 40 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
07431506 | 41 | select ARCH_WANT_GENERAL_HUGETLB |
b1b3f49c | 42 | select ARCH_WANT_IPC_PARSE_VERSION |
59612b24 | 43 | select ARCH_WANT_LD_ORPHAN_WARN |
bdd15a28 | 44 | select BINFMT_FLAT_ARGVP_ENVP_ON_STACK |
10916706 | 45 | select BUILDTIME_TABLE_SORT if MMU |
171b3f0d | 46 | select CLONE_BACKWARDS |
f00790aa | 47 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 48 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 49 | select DMA_DECLARE_COHERENT |
31b089bb | 50 | select DMA_GLOBAL_POOL if !MMU |
2f9237d4 | 51 | select DMA_OPS |
f5ff79fd | 52 | select DMA_NONCOHERENT_MMAP if MMU |
b01aec9b BP |
53 | select EDAC_SUPPORT |
54 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 55 | select GENERIC_ALLOCATOR |
2ef7a295 | 56 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 57 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 58 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
56afcd3d | 59 | select GENERIC_IRQ_IPI if SMP |
ea2d9a96 | 60 | select GENERIC_CPU_AUTOPROBE |
2937367b | 61 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 62 | select GENERIC_IDLE_POLL_SETUP |
234a0f20 | 63 | select GENERIC_IRQ_MULTI_HANDLER |
b1b3f49c RK |
64 | select GENERIC_IRQ_PROBE |
65 | select GENERIC_IRQ_SHOW | |
7c07005e | 66 | select GENERIC_IRQ_SHOW_LEVEL |
914ee966 | 67 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
b1b3f49c | 68 | select GENERIC_PCI_IOMAP |
38ff87f7 | 69 | select GENERIC_SCHED_CLOCK |
b1b3f49c | 70 | select GENERIC_SMP_IDLE_THREAD |
b1b3f49c | 71 | select HARDIRQS_SW_RESEND |
f00790aa | 72 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 73 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee | 74 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
75969686 | 75 | select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL |
437682ee | 76 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU |
42101571 | 77 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL |
e0c25d95 | 78 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
4f5b0c17 | 79 | select HAVE_ARCH_PFN_VALID |
282a181b | 80 | select HAVE_ARCH_SECCOMP |
f00790aa | 81 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 82 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 83 | select HAVE_ARCH_TRACEHOOK |
e8003bf6 | 84 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE |
b329f95d | 85 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 86 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 87 | select HAVE_CONTEXT_TRACKING |
b1b3f49c | 88 | select HAVE_C_RECORDMCOUNT |
4ed308c4 | 89 | select HAVE_BUILDTIME_MCOUNT_SORT |
bc420c6c | 90 | select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL |
b1b3f49c | 91 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 92 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 93 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 94 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 95 | select HAVE_EXIT_THREAD |
67a929e0 | 96 | select HAVE_FAST_GUP if ARM_LPAE |
f00790aa | 97 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
41918ec8 | 98 | select HAVE_FUNCTION_GRAPH_TRACER |
d6800ca7 | 99 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 100 | select HAVE_GCC_PLUGINS |
f00790aa | 101 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
87c46b6c | 102 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 103 | select HAVE_KERNEL_GZIP |
f9b493ac | 104 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 105 | select HAVE_KERNEL_LZMA |
b1b3f49c | 106 | select HAVE_KERNEL_LZO |
a7f464f3 | 107 | select HAVE_KERNEL_XZ |
cb1293e2 | 108 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 109 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 110 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 111 | select HAVE_NMI |
0dc016db | 112 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 113 | select HAVE_PERF_EVENTS |
49863894 WD |
114 | select HAVE_PERF_REGS |
115 | select HAVE_PERF_USER_STACK_DUMP | |
ff2e6d72 | 116 | select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 117 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 118 | select HAVE_RSEQ |
d148eac0 | 119 | select HAVE_STACKPROTECTOR |
b1b3f49c | 120 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 121 | select HAVE_UID16 |
31c1fc81 | 122 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 123 | select IRQ_FORCED_THREADING |
171b3f0d | 124 | select MODULES_USE_ELF_REL |
f616ab59 | 125 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 126 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
127 | select OLD_SIGACTION |
128 | select OLD_SIGSUSPEND3 | |
20f1b79d | 129 | select PCI_SYSCALL if PCI |
b1b3f49c RK |
130 | select PERF_USE_VMALLOC |
131 | select RTC_LIB | |
132 | select SYS_SUPPORTS_APM_EMULATION | |
9c46929e | 133 | select THREAD_INFO_IN_TASK |
d6905849 | 134 | select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS |
4aae683f | 135 | select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M |
171b3f0d RK |
136 | # Above selects are sorted alphabetically; please add new ones |
137 | # according to that. Thanks. | |
1da177e4 LT |
138 | help |
139 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 140 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 141 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 142 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
143 | Europe. There is an ARM Linux project with a web page at |
144 | <http://www.arm.linux.org.uk/>. | |
145 | ||
d6905849 AB |
146 | config ARM_HAS_GROUP_RELOCS |
147 | def_bool y | |
148 | depends on !LD_IS_LLD || LLD_VERSION >= 140000 | |
149 | depends on !COMPILE_TEST | |
150 | help | |
151 | Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group | |
152 | relocations, which have been around for a long time, but were not | |
153 | supported in LLD until version 14. The combined range is -/+ 256 MiB, | |
154 | which is usually sufficient, but not for allyesconfig, so we disable | |
155 | this feature when doing compile testing. | |
156 | ||
74facffe RK |
157 | config ARM_HAS_SG_CHAIN |
158 | bool | |
159 | ||
4ce63fcd | 160 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 161 | bool |
b1b3f49c RK |
162 | select ARM_HAS_SG_CHAIN |
163 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 164 | |
60460abf SWK |
165 | if ARM_DMA_USE_IOMMU |
166 | ||
167 | config ARM_DMA_IOMMU_ALIGNMENT | |
168 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
169 | range 4 9 | |
170 | default 8 | |
171 | help | |
172 | DMA mapping framework by default aligns all buffers to the smallest | |
173 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
174 | size. This works well for buffers up to a few hundreds kilobytes, but | |
175 | for larger buffers it just a waste of address space. Drivers which has | |
176 | relatively small addressing window (like 64Mib) might run out of | |
177 | virtual space with just a few allocations. | |
178 | ||
179 | With this parameter you can specify the maximum PAGE_SIZE order for | |
180 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
181 | specified order. The order is expressed as a power of two multiplied | |
182 | by the PAGE_SIZE. | |
183 | ||
184 | endif | |
185 | ||
75e7153a RB |
186 | config SYS_SUPPORTS_APM_EMULATION |
187 | bool | |
188 | ||
bc581770 LW |
189 | config HAVE_TCM |
190 | bool | |
191 | select GENERIC_ALLOCATOR | |
192 | ||
e119bfff RK |
193 | config HAVE_PROC_CPU |
194 | bool | |
195 | ||
ce816fa8 | 196 | config NO_IOPORT_MAP |
5ea81769 | 197 | bool |
5ea81769 | 198 | |
1da177e4 LT |
199 | config SBUS |
200 | bool | |
201 | ||
f16fb1ec RK |
202 | config STACKTRACE_SUPPORT |
203 | bool | |
204 | default y | |
205 | ||
206 | config LOCKDEP_SUPPORT | |
207 | bool | |
208 | default y | |
209 | ||
f0d1b0b3 DH |
210 | config ARCH_HAS_ILOG2_U32 |
211 | bool | |
f0d1b0b3 DH |
212 | |
213 | config ARCH_HAS_ILOG2_U64 | |
214 | bool | |
f0d1b0b3 | 215 | |
4a1b5733 EV |
216 | config ARCH_HAS_BANDGAP |
217 | bool | |
218 | ||
a5f4c561 SA |
219 | config FIX_EARLYCON_MEM |
220 | def_bool y if MMU | |
221 | ||
b89c3b16 AM |
222 | config GENERIC_HWEIGHT |
223 | bool | |
224 | default y | |
225 | ||
1da177e4 LT |
226 | config GENERIC_CALIBRATE_DELAY |
227 | bool | |
228 | default y | |
229 | ||
a08b6b79 Z |
230 | config ARCH_MAY_HAVE_PC_FDC |
231 | bool | |
232 | ||
c7edc9e3 DL |
233 | config ARCH_SUPPORTS_UPROBES |
234 | def_bool y | |
235 | ||
1da177e4 LT |
236 | config GENERIC_ISA_DMA |
237 | bool | |
238 | ||
1da177e4 LT |
239 | config FIQ |
240 | bool | |
241 | ||
034d2f5a AV |
242 | config ARCH_MTD_XIP |
243 | bool | |
244 | ||
dc21af99 | 245 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
246 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
247 | default y | |
b511d75d | 248 | depends on !XIP_KERNEL && MMU |
dc21af99 | 249 | help |
111e9a5c RK |
250 | Patch phys-to-virt and virt-to-phys translation functions at |
251 | boot and module load time according to the position of the | |
252 | kernel in system memory. | |
dc21af99 | 253 | |
111e9a5c | 254 | This can only be used with non-XIP MMU kernels where the base |
9443076e | 255 | of physical memory is at a 2 MiB boundary. |
dc21af99 | 256 | |
c1becedc RK |
257 | Only disable this option if you know that you do not require |
258 | this feature (eg, building a kernel for a single machine) and | |
259 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 260 | |
c334bc15 RH |
261 | config NEED_MACH_IO_H |
262 | bool | |
263 | help | |
264 | Select this when mach/io.h is required to provide special | |
265 | definitions for this platform. The need for mach/io.h should | |
266 | be avoided when possible. | |
267 | ||
0cdc8b92 | 268 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
269 | bool |
270 | help | |
0cdc8b92 NP |
271 | Select this when mach/memory.h is required to provide special |
272 | definitions for this platform. The need for mach/memory.h should | |
273 | be avoided when possible. | |
dc21af99 | 274 | |
1b9f95f8 | 275 | config PHYS_OFFSET |
974c0724 | 276 | hex "Physical address of main memory" if MMU |
c6f54a9b | 277 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 278 | default DRAM_BASE if !MMU |
06954b6a | 279 | default 0x00000000 if ARCH_FOOTBRIDGE |
c6f54a9b | 280 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
c6e77bb6 AB |
281 | default 0x30000000 if ARCH_S3C24XX |
282 | default 0xa0000000 if ARCH_IOP32X || ARCH_PXA | |
283 | default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 | |
284 | default 0 | |
111e9a5c | 285 | help |
1b9f95f8 NP |
286 | Please provide the physical address corresponding to the |
287 | location of main memory in your system. | |
cada3c08 | 288 | |
87e040b6 SG |
289 | config GENERIC_BUG |
290 | def_bool y | |
291 | depends on BUG | |
292 | ||
1bcad26e KS |
293 | config PGTABLE_LEVELS |
294 | int | |
295 | default 3 if ARM_LPAE | |
296 | default 2 | |
297 | ||
1da177e4 LT |
298 | menu "System Type" |
299 | ||
3c427975 HC |
300 | config MMU |
301 | bool "MMU-based Paged Memory Management Support" | |
302 | default y | |
303 | help | |
304 | Select if you want MMU-based virtualised addressing space | |
305 | support by paged memory management. If unsure, say 'Y'. | |
306 | ||
2f618d5e AB |
307 | config ARM_SINGLE_ARMV7M |
308 | def_bool !MMU | |
309 | select ARM_NVIC | |
310 | select AUTO_ZRELADDR | |
311 | select TIMER_OF | |
312 | select COMMON_CLK | |
313 | select CPU_V7M | |
314 | select NO_IOPORT_MAP | |
315 | select SPARSE_IRQ | |
316 | select USE_OF | |
317 | ||
e0c25d95 DC |
318 | config ARCH_MMAP_RND_BITS_MIN |
319 | default 8 | |
320 | ||
321 | config ARCH_MMAP_RND_BITS_MAX | |
322 | default 14 if PAGE_OFFSET=0x40000000 | |
323 | default 15 if PAGE_OFFSET=0x80000000 | |
324 | default 16 | |
325 | ||
ccf50e23 RK |
326 | # |
327 | # The "ARM system type" choice list is ordered alphabetically by option | |
328 | # text. Please add new entries in the option alphabetic order. | |
329 | # | |
1da177e4 LT |
330 | choice |
331 | prompt "ARM system type" | |
2f618d5e AB |
332 | depends on MMU |
333 | default ARCH_MULTIPLATFORM | |
1da177e4 | 334 | |
387798b3 RH |
335 | config ARCH_MULTIPLATFORM |
336 | bool "Allow multiple platforms to be selected" | |
fb597f2a GF |
337 | select ARCH_FLATMEM_ENABLE |
338 | select ARCH_SPARSEMEM_ENABLE | |
339 | select ARCH_SELECT_MEMORY_MODEL | |
42dc836d | 340 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
341 | select ARM_PATCH_PHYS_VIRT |
342 | select AUTO_ZRELADDR | |
bb0eb050 | 343 | select TIMER_OF |
66314223 | 344 | select COMMON_CLK |
eb01d42a | 345 | select HAVE_PCI |
2eac9c2d | 346 | select PCI_DOMAINS_GENERIC if PCI |
66314223 DN |
347 | select SPARSE_IRQ |
348 | select USE_OF | |
66314223 | 349 | |
e7736d47 LB |
350 | config ARCH_EP93XX |
351 | bool "EP93xx-based" | |
80320927 | 352 | select ARCH_SPARSEMEM_ENABLE |
e7736d47 | 353 | select ARM_AMBA |
cd5bad41 | 354 | imply ARM_PATCH_PHYS_VIRT |
e7736d47 | 355 | select ARM_VIC |
b8824c9a | 356 | select AUTO_ZRELADDR |
000bc178 | 357 | select CLKSRC_MMIO |
b1b3f49c | 358 | select CPU_ARM920T |
5c34a4e8 | 359 | select GPIOLIB |
9645ccc7 | 360 | select COMMON_CLK |
e7736d47 LB |
361 | help |
362 | This enables support for the Cirrus EP93xx series of CPUs. | |
363 | ||
1da177e4 LT |
364 | config ARCH_FOOTBRIDGE |
365 | bool "FootBridge" | |
c750815e | 366 | select CPU_SA110 |
1da177e4 | 367 | select FOOTBRIDGE |
0cdc8b92 | 368 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
369 | help |
370 | Support for systems based on the DC21285 companion chip | |
371 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 372 | |
3f7e5815 LB |
373 | config ARCH_IOP32X |
374 | bool "IOP32x-based" | |
c750815e | 375 | select CPU_XSCALE |
e9004f50 | 376 | select GPIO_IOP |
5c34a4e8 | 377 | select GPIOLIB |
eb01d42a | 378 | select FORCE_PCI |
b1b3f49c | 379 | select PLAT_IOP |
f999b8bd | 380 | help |
3f7e5815 LB |
381 | Support for Intel's 80219 and IOP32X (XScale) family of |
382 | processors. | |
383 | ||
3b938be6 RK |
384 | config ARCH_IXP4XX |
385 | bool "IXP4xx-based" | |
51aaf81f | 386 | select ARCH_SUPPORTS_BIG_ENDIAN |
06954b6a | 387 | select ARM_PATCH_PHYS_VIRT |
c750815e | 388 | select CPU_XSCALE |
55ec465e | 389 | select GPIO_IXP4XX |
5c34a4e8 | 390 | select GPIOLIB |
eb01d42a | 391 | select HAVE_PCI |
55ec465e | 392 | select IXP4XX_IRQ |
65af6667 | 393 | select IXP4XX_TIMER |
06954b6a | 394 | select SPARSE_IRQ |
9296d94d | 395 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 396 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 397 | help |
3b938be6 | 398 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 399 | |
edabd38e SB |
400 | config ARCH_DOVE |
401 | bool "Marvell Dove" | |
756b2531 | 402 | select CPU_PJ4 |
5c34a4e8 | 403 | select GPIOLIB |
eb01d42a | 404 | select HAVE_PCI |
171b3f0d | 405 | select MVEBU_MBUS |
9139acd1 SH |
406 | select PINCTRL |
407 | select PINCTRL_DOVE | |
abcda1dc | 408 | select PLAT_ORION_LEGACY |
0bd86961 | 409 | select SPARSE_IRQ |
c5d431e8 | 410 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 411 | help |
edabd38e | 412 | Support for the Marvell Dove SoC 88AP510 |
788c9700 | 413 | |
1da177e4 | 414 | config ARCH_PXA |
2c8086a5 | 415 | bool "PXA2xx/PXA3xx-based" |
b1b3f49c | 416 | select ARCH_MTD_XIP |
b1b3f49c RK |
417 | select ARM_CPU_SUSPEND if PM |
418 | select AUTO_ZRELADDR | |
a1c0a6ad | 419 | select COMMON_CLK |
389d9b58 | 420 | select CLKSRC_PXA |
234b6ced | 421 | select CLKSRC_MMIO |
bb0eb050 | 422 | select TIMER_OF |
2f202861 | 423 | select CPU_XSCALE if !CPU_XSC3 |
157d2644 | 424 | select GPIO_PXA |
5c34a4e8 | 425 | select GPIOLIB |
d6cf30ca | 426 | select IRQ_DOMAIN |
b1b3f49c RK |
427 | select PLAT_PXA |
428 | select SPARSE_IRQ | |
f999b8bd | 429 | help |
2c8086a5 | 430 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
431 | |
432 | config ARCH_RPC | |
433 | bool "RiscPC" | |
2abd6e34 | 434 | depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 |
1da177e4 | 435 | select ARCH_ACORN |
a08b6b79 | 436 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 437 | select ARCH_SPARSEMEM_ENABLE |
0b40deee | 438 | select ARM_HAS_SG_CHAIN |
fa04e209 | 439 | select CPU_SA110 |
b1b3f49c | 440 | select FIQ |
b1b3f49c RK |
441 | select HAVE_PATA_PLATFORM |
442 | select ISA_DMA_API | |
6239da29 | 443 | select LEGACY_TIMER_TICK |
c334bc15 | 444 | select NEED_MACH_IO_H |
0cdc8b92 | 445 | select NEED_MACH_MEMORY_H |
ce816fa8 | 446 | select NO_IOPORT_MAP |
1da177e4 LT |
447 | help |
448 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
449 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
450 | ||
451 | config ARCH_SA1100 | |
452 | bool "SA1100-based" | |
b1b3f49c | 453 | select ARCH_MTD_XIP |
b1b3f49c | 454 | select ARCH_SPARSEMEM_ENABLE |
b1b3f49c | 455 | select CLKSRC_MMIO |
389d9b58 | 456 | select CLKSRC_PXA |
bb0eb050 | 457 | select TIMER_OF if OF |
d6c82046 | 458 | select COMMON_CLK |
1937f5b9 | 459 | select CPU_FREQ |
b1b3f49c | 460 | select CPU_SA1100 |
5c34a4e8 | 461 | select GPIOLIB |
1eca42b4 | 462 | select IRQ_DOMAIN |
b1b3f49c | 463 | select ISA |
0cdc8b92 | 464 | select NEED_MACH_MEMORY_H |
375dec92 | 465 | select SPARSE_IRQ |
f999b8bd MM |
466 | help |
467 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 468 | |
b130d5c2 KK |
469 | config ARCH_S3C24XX |
470 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 471 | select ATAGS |
4280506a | 472 | select CLKSRC_SAMSUNG_PWM |
880cf071 | 473 | select GPIO_SAMSUNG |
5c34a4e8 | 474 | select GPIOLIB |
c334bc15 | 475 | select NEED_MACH_IO_H |
f6d7cde8 | 476 | select S3C2410_WATCHDOG |
cd8dc7ae | 477 | select SAMSUNG_ATAGS |
ea04d6b4 | 478 | select USE_OF |
f6d7cde8 | 479 | select WATCHDOG |
1da177e4 | 480 | help |
b130d5c2 KK |
481 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
482 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
483 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
484 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 485 | |
a0694861 TL |
486 | config ARCH_OMAP1 |
487 | bool "TI OMAP1" | |
a0694861 | 488 | select ARCH_OMAP |
d6e15d78 | 489 | select CLKSRC_MMIO |
a0694861 | 490 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 491 | select GPIOLIB |
bbd7ffdb | 492 | select HAVE_LEGACY_CLK |
a0694861 TL |
493 | select IRQ_DOMAIN |
494 | select NEED_MACH_IO_H if PCCARD | |
495 | select NEED_MACH_MEMORY_H | |
685e2d08 | 496 | select SPARSE_IRQ |
21f47fbc | 497 | help |
a0694861 | 498 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 499 | |
1da177e4 LT |
500 | endchoice |
501 | ||
387798b3 RH |
502 | menu "Multiple platform selection" |
503 | depends on ARCH_MULTIPLATFORM | |
504 | ||
505 | comment "CPU Core family selection" | |
506 | ||
f8afae40 AB |
507 | config ARCH_MULTI_V4 |
508 | bool "ARMv4 based platforms (FA526)" | |
509 | depends on !ARCH_MULTI_V6_V7 | |
510 | select ARCH_MULTI_V4_V5 | |
511 | select CPU_FA526 | |
512 | ||
387798b3 RH |
513 | config ARCH_MULTI_V4T |
514 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 515 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 516 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
517 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
518 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
519 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
520 | |
521 | config ARCH_MULTI_V5 | |
522 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 523 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 524 | select ARCH_MULTI_V4_V5 |
12567bbd | 525 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
526 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
527 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
528 | |
529 | config ARCH_MULTI_V4_V5 | |
530 | bool | |
531 | ||
532 | config ARCH_MULTI_V6 | |
8dda05cc | 533 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 534 | select ARCH_MULTI_V6_V7 |
42f4754a | 535 | select CPU_V6K |
387798b3 RH |
536 | |
537 | config ARCH_MULTI_V7 | |
8dda05cc | 538 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
539 | default y |
540 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 541 | select CPU_V7 |
90bc8ac7 | 542 | select HAVE_SMP |
387798b3 RH |
543 | |
544 | config ARCH_MULTI_V6_V7 | |
545 | bool | |
9352b05b | 546 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
547 | |
548 | config ARCH_MULTI_CPU_AUTO | |
549 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
550 | select ARCH_MULTI_V5 | |
551 | ||
552 | endmenu | |
553 | ||
05e2a3de | 554 | config ARCH_VIRT |
e3246542 MY |
555 | bool "Dummy Virtual Machine" |
556 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 557 | select ARM_AMBA |
05e2a3de | 558 | select ARM_GIC |
3ee80364 | 559 | select ARM_GIC_V2M if PCI |
0b28f1db | 560 | select ARM_GIC_V3 |
bb29cecb | 561 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 562 | select ARM_PSCI |
4b8b5f25 | 563 | select HAVE_ARM_ARCH_TIMER |
8e2649d0 | 564 | select ARCH_SUPPORTS_BIG_ENDIAN |
05e2a3de | 565 | |
2cf1c348 JC |
566 | config ARCH_AIROHA |
567 | bool "Airoha SoC Support" | |
568 | depends on ARCH_MULTI_V7 | |
569 | select ARM_AMBA | |
570 | select ARM_GIC | |
571 | select ARM_GIC_V3 | |
572 | select ARM_PSCI | |
573 | select HAVE_ARM_ARCH_TIMER | |
574 | select COMMON_CLK | |
575 | help | |
576 | Support for Airoha EN7523 SoCs | |
577 | ||
ccf50e23 RK |
578 | # |
579 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
580 | # Kconfigs may be included either alphabetically (according to the | |
581 | # plat- suffix) or along side the corresponding mach-* source. | |
582 | # | |
6bb8536c AF |
583 | source "arch/arm/mach-actions/Kconfig" |
584 | ||
445d9b30 TZ |
585 | source "arch/arm/mach-alpine/Kconfig" |
586 | ||
590b460c LP |
587 | source "arch/arm/mach-artpec/Kconfig" |
588 | ||
d9bfc86d OR |
589 | source "arch/arm/mach-asm9260/Kconfig" |
590 | ||
a66c51f9 AB |
591 | source "arch/arm/mach-aspeed/Kconfig" |
592 | ||
95b8f20f RK |
593 | source "arch/arm/mach-at91/Kconfig" |
594 | ||
1d22924e AB |
595 | source "arch/arm/mach-axxia/Kconfig" |
596 | ||
8ac49e04 CD |
597 | source "arch/arm/mach-bcm/Kconfig" |
598 | ||
1c37fa10 SH |
599 | source "arch/arm/mach-berlin/Kconfig" |
600 | ||
1da177e4 LT |
601 | source "arch/arm/mach-clps711x/Kconfig" |
602 | ||
d94f944e AV |
603 | source "arch/arm/mach-cns3xxx/Kconfig" |
604 | ||
95b8f20f RK |
605 | source "arch/arm/mach-davinci/Kconfig" |
606 | ||
df8d742e BS |
607 | source "arch/arm/mach-digicolor/Kconfig" |
608 | ||
95b8f20f RK |
609 | source "arch/arm/mach-dove/Kconfig" |
610 | ||
e7736d47 LB |
611 | source "arch/arm/mach-ep93xx/Kconfig" |
612 | ||
a66c51f9 | 613 | source "arch/arm/mach-exynos/Kconfig" |
a66c51f9 | 614 | |
1da177e4 LT |
615 | source "arch/arm/mach-footbridge/Kconfig" |
616 | ||
59d3a193 PZ |
617 | source "arch/arm/mach-gemini/Kconfig" |
618 | ||
387798b3 RH |
619 | source "arch/arm/mach-highbank/Kconfig" |
620 | ||
389ee0c2 HZ |
621 | source "arch/arm/mach-hisi/Kconfig" |
622 | ||
a66c51f9 AB |
623 | source "arch/arm/mach-imx/Kconfig" |
624 | ||
1da177e4 LT |
625 | source "arch/arm/mach-integrator/Kconfig" |
626 | ||
3f7e5815 LB |
627 | source "arch/arm/mach-iop32x/Kconfig" |
628 | ||
1da177e4 LT |
629 | source "arch/arm/mach-ixp4xx/Kconfig" |
630 | ||
828989ad SS |
631 | source "arch/arm/mach-keystone/Kconfig" |
632 | ||
75bf1bd7 | 633 | source "arch/arm/mach-lpc32xx/Kconfig" |
95b8f20f | 634 | |
a66c51f9 AB |
635 | source "arch/arm/mach-mediatek/Kconfig" |
636 | ||
3b8f5030 CC |
637 | source "arch/arm/mach-meson/Kconfig" |
638 | ||
9fb29c73 ST |
639 | source "arch/arm/mach-milbeaut/Kconfig" |
640 | ||
a66c51f9 | 641 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 642 | |
a66c51f9 | 643 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 644 | |
312b62b6 DP |
645 | source "arch/arm/mach-mstar/Kconfig" |
646 | ||
794d15b2 SS |
647 | source "arch/arm/mach-mv78xx0/Kconfig" |
648 | ||
a66c51f9 | 649 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 650 | |
1d3f33d5 SG |
651 | source "arch/arm/mach-mxs/Kconfig" |
652 | ||
95b8f20f | 653 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 654 | |
7bffa14c BH |
655 | source "arch/arm/mach-npcm/Kconfig" |
656 | ||
9851ca57 DT |
657 | source "arch/arm/mach-nspire/Kconfig" |
658 | ||
d48af15e TL |
659 | source "arch/arm/plat-omap/Kconfig" |
660 | ||
661 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 662 | |
1dbae815 TL |
663 | source "arch/arm/mach-omap2/Kconfig" |
664 | ||
9dd0b194 | 665 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 666 | |
a66c51f9 AB |
667 | source "arch/arm/mach-oxnas/Kconfig" |
668 | ||
95b8f20f RK |
669 | source "arch/arm/mach-pxa/Kconfig" |
670 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 671 | |
8fc1b0f8 KG |
672 | source "arch/arm/mach-qcom/Kconfig" |
673 | ||
78e3dbc1 AF |
674 | source "arch/arm/mach-rda/Kconfig" |
675 | ||
86aeee4d AF |
676 | source "arch/arm/mach-realtek/Kconfig" |
677 | ||
95b8f20f RK |
678 | source "arch/arm/mach-realview/Kconfig" |
679 | ||
d63dc051 HS |
680 | source "arch/arm/mach-rockchip/Kconfig" |
681 | ||
71b9114d | 682 | source "arch/arm/mach-s3c/Kconfig" |
a66c51f9 AB |
683 | |
684 | source "arch/arm/mach-s5pv210/Kconfig" | |
685 | ||
95b8f20f | 686 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 687 | |
a66c51f9 AB |
688 | source "arch/arm/mach-shmobile/Kconfig" |
689 | ||
387798b3 RH |
690 | source "arch/arm/mach-socfpga/Kconfig" |
691 | ||
a7ed099f | 692 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 693 | |
65ebcc11 SK |
694 | source "arch/arm/mach-sti/Kconfig" |
695 | ||
bcb84fb4 AT |
696 | source "arch/arm/mach-stm32/Kconfig" |
697 | ||
3b52634f MR |
698 | source "arch/arm/mach-sunxi/Kconfig" |
699 | ||
c5f80065 EG |
700 | source "arch/arm/mach-tegra/Kconfig" |
701 | ||
ba56a987 MY |
702 | source "arch/arm/mach-uniphier/Kconfig" |
703 | ||
95b8f20f | 704 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
705 | |
706 | source "arch/arm/mach-versatile/Kconfig" | |
707 | ||
ceade897 RK |
708 | source "arch/arm/mach-vexpress/Kconfig" |
709 | ||
6f35f9a9 TP |
710 | source "arch/arm/mach-vt8500/Kconfig" |
711 | ||
9a45eb69 JC |
712 | source "arch/arm/mach-zynq/Kconfig" |
713 | ||
499f1640 | 714 | # ARMv7-M architecture |
499f1640 SA |
715 | config ARCH_LPC18XX |
716 | bool "NXP LPC18xx/LPC43xx" | |
717 | depends on ARM_SINGLE_ARMV7M | |
718 | select ARCH_HAS_RESET_CONTROLLER | |
719 | select ARM_AMBA | |
720 | select CLKSRC_LPC32XX | |
721 | select PINCTRL | |
722 | help | |
723 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
724 | high performance microcontrollers. | |
725 | ||
1847119d | 726 | config ARCH_MPS2 |
17bd274e | 727 | bool "ARM MPS2 platform" |
1847119d VM |
728 | depends on ARM_SINGLE_ARMV7M |
729 | select ARM_AMBA | |
730 | select CLKSRC_MPS2 | |
731 | help | |
732 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
733 | with a range of available cores like Cortex-M3/M4/M7. | |
734 | ||
735 | Please, note that depends which Application Note is used memory map | |
736 | for the platform may vary, so adjustment of RAM base might be needed. | |
737 | ||
1da177e4 LT |
738 | # Definitions to make life easier |
739 | config ARCH_ACORN | |
740 | bool | |
741 | ||
7ae1f7ec LB |
742 | config PLAT_IOP |
743 | bool | |
744 | ||
69b02f6a LB |
745 | config PLAT_ORION |
746 | bool | |
bfe45e0b | 747 | select CLKSRC_MMIO |
b1b3f49c | 748 | select COMMON_CLK |
dc7ad3b3 | 749 | select GENERIC_IRQ_CHIP |
278b45b0 | 750 | select IRQ_DOMAIN |
69b02f6a | 751 | |
abcda1dc TP |
752 | config PLAT_ORION_LEGACY |
753 | bool | |
754 | select PLAT_ORION | |
755 | ||
bd5ce433 EM |
756 | config PLAT_PXA |
757 | bool | |
758 | ||
f4b8b319 RK |
759 | config PLAT_VERSATILE |
760 | bool | |
761 | ||
8636a1f9 | 762 | source "arch/arm/mm/Kconfig" |
1da177e4 | 763 | |
afe4b25e | 764 | config IWMMXT |
d93003e8 SH |
765 | bool "Enable iWMMXt support" |
766 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
767 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
768 | help |
769 | Enable support for iWMMXt context switching at run time if | |
770 | running on a CPU that supports it. | |
771 | ||
3b93e7b0 HC |
772 | if !MMU |
773 | source "arch/arm/Kconfig-nommu" | |
774 | endif | |
775 | ||
3e0a07f8 GC |
776 | config PJ4B_ERRATA_4742 |
777 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
778 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
779 | default y | |
780 | help | |
781 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
782 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
783 | the retiring WFI/WFE instructions and the newly issued subsequent | |
784 | instructions. This sensitivity can result in a CPU hang scenario. | |
785 | Workaround: | |
786 | The software must insert either a Data Synchronization Barrier (DSB) | |
787 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
788 | instruction | |
789 | ||
f0c4b8d6 WD |
790 | config ARM_ERRATA_326103 |
791 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
792 | depends on CPU_V6 | |
793 | help | |
794 | Executing a SWP instruction to read-only memory does not set bit 11 | |
795 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
796 | treat the access as a read, preventing a COW from occurring and | |
797 | causing the faulting task to livelock. | |
798 | ||
9cba3ccc CM |
799 | config ARM_ERRATA_411920 |
800 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 801 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
802 | help |
803 | Invalidation of the Instruction Cache operation can | |
804 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
805 | It does not affect the MPCore. This option enables the ARM Ltd. | |
806 | recommended workaround. | |
807 | ||
7ce236fc CM |
808 | config ARM_ERRATA_430973 |
809 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
810 | depends on CPU_V7 | |
811 | help | |
812 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 813 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
814 | interworking branch is replaced with another code sequence at the |
815 | same virtual address, whether due to self-modifying code or virtual | |
816 | to physical address re-mapping, Cortex-A8 does not recover from the | |
817 | stale interworking branch prediction. This results in Cortex-A8 | |
818 | executing the new code sequence in the incorrect ARM or Thumb state. | |
819 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
820 | and also flushes the branch target cache at every context switch. | |
821 | Note that setting specific bits in the ACTLR register may not be | |
822 | available in non-secure mode. | |
823 | ||
855c551f CM |
824 | config ARM_ERRATA_458693 |
825 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
826 | depends on CPU_V7 | |
62e4d357 | 827 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
828 | help |
829 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
830 | erratum. For very specific sequences of memory operations, it is | |
831 | possible for a hazard condition intended for a cache line to instead | |
832 | be incorrectly associated with a different cache line. This false | |
833 | hazard might then cause a processor deadlock. The workaround enables | |
834 | the L1 caching of the NEON accesses and disables the PLD instruction | |
835 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
836 | register may not be available in non-secure mode. | |
837 | ||
0516e464 CM |
838 | config ARM_ERRATA_460075 |
839 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
840 | depends on CPU_V7 | |
62e4d357 | 841 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
842 | help |
843 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
844 | erratum. Any asynchronous access to the L2 cache may encounter a | |
845 | situation in which recent store transactions to the L2 cache are lost | |
846 | and overwritten with stale memory contents from external memory. The | |
847 | workaround disables the write-allocate mode for the L2 cache via the | |
848 | ACTLR register. Note that setting specific bits in the ACTLR register | |
849 | may not be available in non-secure mode. | |
850 | ||
9f05027c WD |
851 | config ARM_ERRATA_742230 |
852 | bool "ARM errata: DMB operation may be faulty" | |
853 | depends on CPU_V7 && SMP | |
62e4d357 | 854 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
855 | help |
856 | This option enables the workaround for the 742230 Cortex-A9 | |
857 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
858 | between two write operations may not ensure the correct visibility | |
859 | ordering of the two writes. This workaround sets a specific bit in | |
860 | the diagnostic register of the Cortex-A9 which causes the DMB | |
861 | instruction to behave as a DSB, ensuring the correct behaviour of | |
862 | the two writes. | |
863 | ||
a672e99b WD |
864 | config ARM_ERRATA_742231 |
865 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
866 | depends on CPU_V7 && SMP | |
62e4d357 | 867 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
868 | help |
869 | This option enables the workaround for the 742231 Cortex-A9 | |
870 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
871 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
872 | accessing some data located in the same cache line, may get corrupted | |
873 | data due to bad handling of the address hazard when the line gets | |
874 | replaced from one of the CPUs at the same time as another CPU is | |
875 | accessing it. This workaround sets specific bits in the diagnostic | |
876 | register of the Cortex-A9 which reduces the linefill issuing | |
877 | capabilities of the processor. | |
878 | ||
69155794 JM |
879 | config ARM_ERRATA_643719 |
880 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
881 | depends on CPU_V7 && SMP | |
e5a5de44 | 882 | default y |
69155794 JM |
883 | help |
884 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
885 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
886 | register returns zero when it should return one. The workaround | |
887 | corrects this value, ensuring cache maintenance operations which use | |
888 | it behave as intended and avoiding data corruption. | |
889 | ||
cdf357f1 WD |
890 | config ARM_ERRATA_720789 |
891 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 892 | depends on CPU_V7 |
cdf357f1 WD |
893 | help |
894 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
895 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
896 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
897 | As a consequence of this erratum, some TLB entries which should be | |
898 | invalidated are not, resulting in an incoherency in the system page | |
899 | tables. The workaround changes the TLB flushing routines to invalidate | |
900 | entries regardless of the ASID. | |
475d92fc WD |
901 | |
902 | config ARM_ERRATA_743622 | |
903 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
904 | depends on CPU_V7 | |
62e4d357 | 905 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
906 | help |
907 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 908 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
909 | optimisation in the Cortex-A9 Store Buffer may lead to data |
910 | corruption. This workaround sets a specific bit in the diagnostic | |
911 | register of the Cortex-A9 which disables the Store Buffer | |
912 | optimisation, preventing the defect from occurring. This has no | |
913 | visible impact on the overall performance or power consumption of the | |
914 | processor. | |
915 | ||
9a27c27c WD |
916 | config ARM_ERRATA_751472 |
917 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 918 | depends on CPU_V7 |
62e4d357 | 919 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
920 | help |
921 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
922 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
923 | completion of a following broadcasted operation if the second | |
924 | operation is received by a CPU before the ICIALLUIS has completed, | |
925 | potentially leading to corrupted entries in the cache or TLB. | |
926 | ||
fcbdc5fe WD |
927 | config ARM_ERRATA_754322 |
928 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
929 | depends on CPU_V7 | |
930 | help | |
931 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
932 | r3p*) erratum. A speculative memory access may cause a page table walk | |
933 | which starts prior to an ASID switch but completes afterwards. This | |
934 | can populate the micro-TLB with a stale entry which may be hit with | |
935 | the new ASID. This workaround places two dsb instructions in the mm | |
936 | switching code so that no page table walks can cross the ASID switch. | |
937 | ||
5dab26af WD |
938 | config ARM_ERRATA_754327 |
939 | bool "ARM errata: no automatic Store Buffer drain" | |
940 | depends on CPU_V7 && SMP | |
941 | help | |
942 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
943 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
944 | mechanism and therefore a livelock may occur if an external agent | |
945 | continuously polls a memory location waiting to observe an update. | |
946 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
947 | written polling loops from denying visibility of updates to memory. | |
948 | ||
145e10e1 CM |
949 | config ARM_ERRATA_364296 |
950 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 951 | depends on CPU_V6 |
145e10e1 CM |
952 | help |
953 | This options enables the workaround for the 364296 ARM1136 | |
954 | r0p2 erratum (possible cache data corruption with | |
955 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
956 | the auxiliary control register and the FI bit in the control | |
957 | register, thus disabling hit-under-miss without putting the | |
958 | processor into full low interrupt latency mode. ARM11MPCore | |
959 | is not affected. | |
960 | ||
f630c1bd WD |
961 | config ARM_ERRATA_764369 |
962 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
963 | depends on CPU_V7 && SMP | |
964 | help | |
965 | This option enables the workaround for erratum 764369 | |
966 | affecting Cortex-A9 MPCore with two or more processors (all | |
967 | current revisions). Under certain timing circumstances, a data | |
968 | cache line maintenance operation by MVA targeting an Inner | |
969 | Shareable memory region may fail to proceed up to either the | |
970 | Point of Coherency or to the Point of Unification of the | |
971 | system. This workaround adds a DSB instruction before the | |
972 | relevant cache maintenance functions and sets a specific bit | |
973 | in the diagnostic control register of the SCU. | |
974 | ||
7253b85c SH |
975 | config ARM_ERRATA_775420 |
976 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
977 | depends on CPU_V7 | |
978 | help | |
979 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
cb73737e | 980 | r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance |
7253b85c SH |
981 | operation aborts with MMU exception, it might cause the processor |
982 | to deadlock. This workaround puts DSB before executing ISB if | |
983 | an abort may occur on cache maintenance. | |
984 | ||
93dc6887 CM |
985 | config ARM_ERRATA_798181 |
986 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
987 | depends on CPU_V7 && SMP | |
988 | help | |
989 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
990 | adequately shooting down all use of the old entries. This | |
991 | option enables the Linux kernel workaround for this erratum | |
992 | which sends an IPI to the CPUs that are running the same ASID | |
993 | as the one being invalidated. | |
994 | ||
84b6504f WD |
995 | config ARM_ERRATA_773022 |
996 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
997 | depends on CPU_V7 | |
998 | help | |
999 | This option enables the workaround for the 773022 Cortex-A15 | |
1000 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1001 | loop buffer may deliver incorrect instructions. This | |
1002 | workaround disables the loop buffer to avoid the erratum. | |
1003 | ||
62c0f4a5 DA |
1004 | config ARM_ERRATA_818325_852422 |
1005 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1006 | depends on CPU_V7 | |
1007 | help | |
1008 | This option enables the workaround for: | |
1009 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1010 | instruction might deadlock. Fixed in r0p1. | |
1011 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1012 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1013 | any Cortex-A12 cores yet. | |
1014 | This workaround for all both errata involves setting bit[12] of the | |
1015 | Feature Register. This bit disables an optimisation applied to a | |
1016 | sequence of 2 instructions that use opposing condition codes. | |
1017 | ||
416bcf21 DA |
1018 | config ARM_ERRATA_821420 |
1019 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1020 | depends on CPU_V7 | |
1021 | help | |
1022 | This option enables the workaround for the 821420 Cortex-A12 | |
1023 | (all revs) erratum. In very rare timing conditions, a sequence | |
1024 | of VMOV to Core registers instructions, for which the second | |
1025 | one is in the shadow of a branch or abort, can lead to a | |
1026 | deadlock when the VMOV instructions are issued out-of-order. | |
1027 | ||
9f6f9354 DA |
1028 | config ARM_ERRATA_825619 |
1029 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1030 | depends on CPU_V7 | |
1031 | help | |
1032 | This option enables the workaround for the 825619 Cortex-A12 | |
1033 | (all revs) erratum. Within rare timing constraints, executing a | |
1034 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1035 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1036 | ||
304009a1 DA |
1037 | config ARM_ERRATA_857271 |
1038 | bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" | |
1039 | depends on CPU_V7 | |
1040 | help | |
1041 | This option enables the workaround for the 857271 Cortex-A12 | |
1042 | (all revs) erratum. Under very rare timing conditions, the CPU might | |
1043 | hang. The workaround is expected to have a < 1% performance impact. | |
1044 | ||
9f6f9354 DA |
1045 | config ARM_ERRATA_852421 |
1046 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1047 | depends on CPU_V7 | |
1048 | help | |
1049 | This option enables the workaround for the 852421 Cortex-A17 | |
1050 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1051 | execution of a DMB ST instruction might fail to properly order | |
1052 | stores from GroupA and stores from GroupB. | |
1053 | ||
62c0f4a5 DA |
1054 | config ARM_ERRATA_852423 |
1055 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1056 | depends on CPU_V7 | |
1057 | help | |
1058 | This option enables the workaround for: | |
1059 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1060 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1061 | any Cortex-A17 cores yet. | |
1062 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1063 | config option from the A12 erratum due to the way errata are checked | |
1064 | for and handled. | |
1065 | ||
304009a1 DA |
1066 | config ARM_ERRATA_857272 |
1067 | bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" | |
1068 | depends on CPU_V7 | |
1069 | help | |
1070 | This option enables the workaround for the 857272 Cortex-A17 erratum. | |
1071 | This erratum is not known to be fixed in any A17 revision. | |
1072 | This is identical to Cortex-A12 erratum 857271. It is a separate | |
1073 | config option from the A12 erratum due to the way errata are checked | |
1074 | for and handled. | |
1075 | ||
1da177e4 LT |
1076 | endmenu |
1077 | ||
1078 | source "arch/arm/common/Kconfig" | |
1079 | ||
1da177e4 LT |
1080 | menu "Bus support" |
1081 | ||
1da177e4 LT |
1082 | config ISA |
1083 | bool | |
1da177e4 LT |
1084 | help |
1085 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1086 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1087 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1088 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1089 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1090 | ||
065909b9 | 1091 | # Select ISA DMA controller support |
1da177e4 LT |
1092 | config ISA_DMA |
1093 | bool | |
065909b9 | 1094 | select ISA_DMA_API |
1da177e4 | 1095 | |
065909b9 | 1096 | # Select ISA DMA interface |
5cae841b AV |
1097 | config ISA_DMA_API |
1098 | bool | |
5cae841b | 1099 | |
b080ac8a MRJ |
1100 | config PCI_NANOENGINE |
1101 | bool "BSE nanoEngine PCI support" | |
1102 | depends on SA1100_NANOENGINE | |
1103 | help | |
1104 | Enable PCI on the BSE nanoEngine board. | |
1105 | ||
779eb41c BG |
1106 | config ARM_ERRATA_814220 |
1107 | bool "ARM errata: Cache maintenance by set/way operations can execute out of order" | |
1108 | depends on CPU_V7 | |
1109 | help | |
1110 | The v7 ARM states that all cache and branch predictor maintenance | |
1111 | operations that do not specify an address execute, relative to | |
1112 | each other, in program order. | |
1113 | However, because of this erratum, an L2 set/way cache maintenance | |
1114 | operation can overtake an L1 set/way cache maintenance operation. | |
1115 | This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, | |
1116 | r0p4, r0p5. | |
1117 | ||
1da177e4 LT |
1118 | endmenu |
1119 | ||
1120 | menu "Kernel Features" | |
1121 | ||
3b55658a DM |
1122 | config HAVE_SMP |
1123 | bool | |
1124 | help | |
1125 | This option should be selected by machines which have an SMP- | |
1126 | capable CPU. | |
1127 | ||
1128 | The only effect of this option is to make the SMP-related | |
1129 | options available to the user for configuration. | |
1130 | ||
1da177e4 | 1131 | config SMP |
bb2d8130 | 1132 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1133 | depends on CPU_V6K || CPU_V7 |
3b55658a | 1134 | depends on HAVE_SMP |
801bb21c | 1135 | depends on MMU || ARM_MPU |
0361748f | 1136 | select IRQ_WORK |
1da177e4 LT |
1137 | help |
1138 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1139 | a system with only one CPU, say N. If you have a system with more |
1140 | than one CPU, say Y. | |
1da177e4 | 1141 | |
4a474157 | 1142 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1143 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1144 | you say Y here, the kernel will run on many, but not all, |
1145 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1146 | will run faster if you say N here. | |
1da177e4 | 1147 | |
cb1aaebe | 1148 | See also <file:Documentation/x86/i386/IO-APIC.rst>, |
4f4cfa6c | 1149 | <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at |
50a23e6e | 1150 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1151 | |
1152 | If you don't know what to do here, say N. | |
1153 | ||
f00ec48f | 1154 | config SMP_ON_UP |
5744ff43 | 1155 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1156 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1157 | default y |
1158 | help | |
1159 | SMP kernels contain instructions which fail on non-SMP processors. | |
1160 | Enabling this option allows the kernel to modify itself to make | |
1161 | these instructions safe. Disabling it allows about 1K of space | |
1162 | savings. | |
1163 | ||
1164 | If you don't know what to do here, say Y. | |
1165 | ||
50596b75 AB |
1166 | |
1167 | config CURRENT_POINTER_IN_TPIDRURO | |
1168 | def_bool y | |
b87cf911 | 1169 | depends on CPU_32v6K && !CPU_V6 |
50596b75 | 1170 | |
d4664b6c AB |
1171 | config IRQSTACKS |
1172 | def_bool y | |
9974f857 AB |
1173 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
1174 | select HAVE_SOFTIRQ_ON_OWN_STACK | |
50596b75 | 1175 | |
c9018aab VG |
1176 | config ARM_CPU_TOPOLOGY |
1177 | bool "Support cpu topology definition" | |
1178 | depends on SMP && CPU_V7 | |
1179 | default y | |
1180 | help | |
1181 | Support ARM cpu topology definition. The MPIDR register defines | |
1182 | affinity between processors which is then used to describe the cpu | |
1183 | topology of an ARM System. | |
1184 | ||
1185 | config SCHED_MC | |
1186 | bool "Multi-core scheduler support" | |
1187 | depends on ARM_CPU_TOPOLOGY | |
1188 | help | |
1189 | Multi-core scheduler support improves the CPU scheduler's decision | |
1190 | making when dealing with multi-core CPU chips at a cost of slightly | |
1191 | increased overhead in some places. If unsure say N here. | |
1192 | ||
1193 | config SCHED_SMT | |
1194 | bool "SMT scheduler support" | |
1195 | depends on ARM_CPU_TOPOLOGY | |
1196 | help | |
1197 | Improves the CPU scheduler's decision making when dealing with | |
1198 | MultiThreading at a cost of slightly increased overhead in some | |
1199 | places. If unsure say N here. | |
1200 | ||
a8cbcd92 RK |
1201 | config HAVE_ARM_SCU |
1202 | bool | |
a8cbcd92 | 1203 | help |
8f433ec4 | 1204 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 1205 | |
8a4da6e3 | 1206 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1207 | bool "Architected timer support" |
1208 | depends on CPU_V7 | |
8a4da6e3 | 1209 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1210 | help |
1211 | This option enables support for the ARM architected timer | |
1212 | ||
f32f4ce2 RK |
1213 | config HAVE_ARM_TWD |
1214 | bool | |
f32f4ce2 RK |
1215 | help |
1216 | This options enables support for the ARM timer and watchdog unit | |
1217 | ||
e8db288e NP |
1218 | config MCPM |
1219 | bool "Multi-Cluster Power Management" | |
1220 | depends on CPU_V7 && SMP | |
1221 | help | |
1222 | This option provides the common power management infrastructure | |
1223 | for (multi-)cluster based systems, such as big.LITTLE based | |
1224 | systems. | |
1225 | ||
ebf4a5c5 HZ |
1226 | config MCPM_QUAD_CLUSTER |
1227 | bool | |
1228 | depends on MCPM | |
1229 | help | |
1230 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1231 | to 2 clusters by default. | |
1232 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1233 | option to allow the additional clusters to be managed. | |
1234 | ||
1c33be57 NP |
1235 | config BIG_LITTLE |
1236 | bool "big.LITTLE support (Experimental)" | |
1237 | depends on CPU_V7 && SMP | |
1238 | select MCPM | |
1239 | help | |
1240 | This option enables support selections for the big.LITTLE | |
1241 | system architecture. | |
1242 | ||
1243 | config BL_SWITCHER | |
1244 | bool "big.LITTLE switcher support" | |
6c044fec | 1245 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1246 | select CPU_PM |
1c33be57 NP |
1247 | help |
1248 | The big.LITTLE "switcher" provides the core functionality to | |
1249 | transparently handle transition between a cluster of A15's | |
1250 | and a cluster of A7's in a big.LITTLE system. | |
1251 | ||
b22537c6 NP |
1252 | config BL_SWITCHER_DUMMY_IF |
1253 | tristate "Simple big.LITTLE switcher user interface" | |
1254 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1255 | help | |
1256 | This is a simple and dummy char dev interface to control | |
1257 | the big.LITTLE switcher core code. It is meant for | |
1258 | debugging purposes only. | |
1259 | ||
8d5796d2 LB |
1260 | choice |
1261 | prompt "Memory split" | |
006fa259 | 1262 | depends on MMU |
8d5796d2 LB |
1263 | default VMSPLIT_3G |
1264 | help | |
1265 | Select the desired split between kernel and user memory. | |
1266 | ||
1267 | If you are not absolutely sure what you are doing, leave this | |
1268 | option alone! | |
1269 | ||
1270 | config VMSPLIT_3G | |
1271 | bool "3G/1G user/kernel split" | |
63ce446c | 1272 | config VMSPLIT_3G_OPT |
bbeedfda | 1273 | depends on !ARM_LPAE |
63ce446c | 1274 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1275 | config VMSPLIT_2G |
1276 | bool "2G/2G user/kernel split" | |
1277 | config VMSPLIT_1G | |
1278 | bool "1G/3G user/kernel split" | |
1279 | endchoice | |
1280 | ||
1281 | config PAGE_OFFSET | |
1282 | hex | |
006fa259 | 1283 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1284 | default 0x40000000 if VMSPLIT_1G |
1285 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1286 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1287 | default 0xC0000000 |
1288 | ||
c12366ba LW |
1289 | config KASAN_SHADOW_OFFSET |
1290 | hex | |
1291 | depends on KASAN | |
1292 | default 0x1f000000 if PAGE_OFFSET=0x40000000 | |
1293 | default 0x5f000000 if PAGE_OFFSET=0x80000000 | |
1294 | default 0x9f000000 if PAGE_OFFSET=0xC0000000 | |
1295 | default 0x8f000000 if PAGE_OFFSET=0xB0000000 | |
1296 | default 0xffffffff | |
1297 | ||
1da177e4 LT |
1298 | config NR_CPUS |
1299 | int "Maximum number of CPUs (2-32)" | |
d624833f AB |
1300 | range 2 16 if DEBUG_KMAP_LOCAL |
1301 | range 2 32 if !DEBUG_KMAP_LOCAL | |
1da177e4 LT |
1302 | depends on SMP |
1303 | default "4" | |
d624833f AB |
1304 | help |
1305 | The maximum number of CPUs that the kernel can support. | |
1306 | Up to 32 CPUs can be supported, or up to 16 if kmap_local() | |
1307 | debugging is enabled, which uses half of the per-CPU fixmap | |
1308 | slots as guard regions. | |
1da177e4 | 1309 | |
a054a811 | 1310 | config HOTPLUG_CPU |
00b7dede | 1311 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1312 | depends on SMP |
1b5ba350 | 1313 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1314 | help |
1315 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1316 | can be controlled through /sys/devices/system/cpu. | |
1317 | ||
2bdd424f WD |
1318 | config ARM_PSCI |
1319 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1320 | depends on HAVE_ARM_SMCCC |
be120397 | 1321 | select ARM_PSCI_FW |
2bdd424f WD |
1322 | help |
1323 | Say Y here if you want Linux to communicate with system firmware | |
1324 | implementing the PSCI specification for CPU-centric power | |
1325 | management operations described in ARM document number ARM DEN | |
1326 | 0022A ("Power State Coordination Interface System Software on | |
1327 | ARM processors"). | |
1328 | ||
2a6ad871 MR |
1329 | # The GPIO number here must be sorted by descending number. In case of |
1330 | # a multiplatform kernel, we just want the highest value required by the | |
1331 | # selected platforms. | |
44986ab0 PDSN |
1332 | config ARCH_NR_GPIO |
1333 | int | |
910499e1 | 1334 | default 2048 if ARCH_INTEL_SOCFPGA |
d9be9ceb | 1335 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
a3ee4fea | 1336 | ARCH_ZYNQ || ARCH_ASPEED |
aa42587a TF |
1337 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1338 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1339 | default 416 if ARCH_SUNXI |
06b851e5 | 1340 | default 392 if ARCH_U8500 |
01bb914c | 1341 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1342 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1343 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1344 | default 0 |
1345 | help | |
1346 | Maximum number of GPIOs in the system. | |
1347 | ||
1348 | If unsure, leave the default value. | |
1349 | ||
c9218b16 | 1350 | config HZ_FIXED |
f8065813 | 1351 | int |
1164f672 | 1352 | default 128 if SOC_AT91RM9200 |
47d84682 | 1353 | default 0 |
c9218b16 RK |
1354 | |
1355 | choice | |
47d84682 | 1356 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1357 | prompt "Timer frequency" |
1358 | ||
1359 | config HZ_100 | |
1360 | bool "100 Hz" | |
1361 | ||
1362 | config HZ_200 | |
1363 | bool "200 Hz" | |
1364 | ||
1365 | config HZ_250 | |
1366 | bool "250 Hz" | |
1367 | ||
1368 | config HZ_300 | |
1369 | bool "300 Hz" | |
1370 | ||
1371 | config HZ_500 | |
1372 | bool "500 Hz" | |
1373 | ||
1374 | config HZ_1000 | |
1375 | bool "1000 Hz" | |
1376 | ||
1377 | endchoice | |
1378 | ||
1379 | config HZ | |
1380 | int | |
47d84682 | 1381 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1382 | default 100 if HZ_100 |
1383 | default 200 if HZ_200 | |
1384 | default 250 if HZ_250 | |
1385 | default 300 if HZ_300 | |
1386 | default 500 if HZ_500 | |
1387 | default 1000 | |
1388 | ||
1389 | config SCHED_HRTICK | |
1390 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1391 | |
16c79651 | 1392 | config THUMB2_KERNEL |
bc7dea00 | 1393 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1394 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1395 | default y if CPU_THUMBONLY |
89bace65 | 1396 | select ARM_UNWIND |
16c79651 CM |
1397 | help |
1398 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1399 | Thumb-2 mode. |
16c79651 CM |
1400 | |
1401 | If unsure, say N. | |
1402 | ||
42f25bdd NP |
1403 | config ARM_PATCH_IDIV |
1404 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1405 | depends on CPU_32v7 && !XIP_KERNEL | |
1406 | default y | |
1407 | help | |
1408 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1409 | __aeabi_uidiv() when it needs to perform division on signed | |
1410 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1411 | and udiv instructions that can be used to implement those | |
1412 | functions. | |
1413 | ||
1414 | Enabling this option allows the kernel to modify itself to | |
1415 | replace the first two instructions of these library functions | |
1416 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1417 | it is running on supports them. Typically this will be faster | |
1418 | and less power intensive than running the original library | |
1419 | code to do integer division. | |
1420 | ||
704bdda0 | 1421 | config AEABI |
a05b9608 ND |
1422 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ |
1423 | !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG | |
1424 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG | |
704bdda0 NP |
1425 | help |
1426 | This option allows for the kernel to be compiled using the latest | |
1427 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1428 | space environment that is also compiled with EABI. | |
1429 | ||
1430 | Since there are major incompatibilities between the legacy ABI and | |
1431 | EABI, especially with regard to structure member alignment, this | |
1432 | option also changes the kernel syscall calling convention to | |
1433 | disambiguate both ABIs and allow for backward compatibility support | |
1434 | (selected with CONFIG_OABI_COMPAT). | |
1435 | ||
1436 | To use this you need GCC version 4.0.0 or later. | |
1437 | ||
6c90c872 | 1438 | config OABI_COMPAT |
a73a3ff1 | 1439 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1440 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1441 | help |
1442 | This option preserves the old syscall interface along with the | |
1443 | new (ARM EABI) one. It also provides a compatibility layer to | |
1444 | intercept syscalls that have structure arguments which layout | |
1445 | in memory differs between the legacy ABI and the new ARM EABI | |
1446 | (only for non "thumb" binaries). This option adds a tiny | |
1447 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1448 | |
1449 | The seccomp filter system will not be available when this is | |
1450 | selected, since there is no way yet to sensibly distinguish | |
1451 | between calling conventions during filtering. | |
1452 | ||
6c90c872 NP |
1453 | If you know you'll be using only pure EABI user space then you |
1454 | can say N here. If this option is not selected and you attempt | |
1455 | to execute a legacy ABI binary then the result will be | |
1456 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1457 | at all). If in doubt say N. |
6c90c872 | 1458 | |
fb597f2a GF |
1459 | config ARCH_SELECT_MEMORY_MODEL |
1460 | bool | |
1461 | ||
1462 | config ARCH_FLATMEM_ENABLE | |
05944d74 RK |
1463 | bool |
1464 | ||
05944d74 RK |
1465 | config ARCH_SPARSEMEM_ENABLE |
1466 | bool | |
fb597f2a | 1467 | select SPARSEMEM_STATIC if SPARSEMEM |
07a2f737 | 1468 | |
053a96ca | 1469 | config HIGHMEM |
e8db89a2 RK |
1470 | bool "High Memory Support" |
1471 | depends on MMU | |
2a15ba82 | 1472 | select KMAP_LOCAL |
825c43f5 | 1473 | select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY |
053a96ca NP |
1474 | help |
1475 | The address space of ARM processors is only 4 Gigabytes large | |
1476 | and it has to accommodate user address space, kernel address | |
1477 | space as well as some memory mapped IO. That means that, if you | |
1478 | have a large amount of physical memory and/or IO, not all of the | |
1479 | memory can be "permanently mapped" by the kernel. The physical | |
1480 | memory that is not permanently mapped is called "high memory". | |
1481 | ||
1482 | Depending on the selected kernel/user memory split, minimum | |
1483 | vmalloc space and actual amount of RAM, you may not need this | |
1484 | option which should result in a slightly faster kernel. | |
1485 | ||
1486 | If unsure, say n. | |
1487 | ||
65cec8e3 | 1488 | config HIGHPTE |
9a431bd5 | 1489 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1490 | depends on HIGHMEM |
9a431bd5 | 1491 | default y |
b4d103d1 RK |
1492 | help |
1493 | The VM uses one page of physical memory for each page table. | |
1494 | For systems with a lot of processes, this can use a lot of | |
1495 | precious low memory, eventually leading to low memory being | |
1496 | consumed by page tables. Setting this option will allow | |
1497 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1498 | |
a5e090ac RK |
1499 | config CPU_SW_DOMAIN_PAN |
1500 | bool "Enable use of CPU domains to implement privileged no-access" | |
1501 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1502 | default y |
1503 | help | |
a5e090ac RK |
1504 | Increase kernel security by ensuring that normal kernel accesses |
1505 | are unable to access userspace addresses. This can help prevent | |
1506 | use-after-free bugs becoming an exploitable privilege escalation | |
1507 | by ensuring that magic values (such as LIST_POISON) will always | |
1508 | fault when dereferenced. | |
1509 | ||
1510 | CPUs with low-vector mappings use a best-efforts implementation. | |
1511 | Their lower 1MB needs to remain accessible for the vectors, but | |
1512 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1513 | |
1b8873a0 | 1514 | config HW_PERF_EVENTS |
fa8ad788 MR |
1515 | def_bool y |
1516 | depends on ARM_PMU | |
1b8873a0 | 1517 | |
7d485f64 AB |
1518 | config ARM_MODULE_PLTS |
1519 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1520 | depends on MODULES | |
e7229f7d | 1521 | default y |
7d485f64 AB |
1522 | help |
1523 | Allocate PLTs when loading modules so that jumps and calls whose | |
1524 | targets are too far away for their relative offsets to be encoded | |
1525 | in the instructions themselves can be bounced via veneers in the | |
1526 | module's PLT. This allows modules to be allocated in the generic | |
1527 | vmalloc area after the dedicated module memory area has been | |
1528 | exhausted. The modules will use slightly more memory, but after | |
1529 | rounding up to page size, the actual memory footprint is usually | |
1530 | the same. | |
1531 | ||
e7229f7d AR |
1532 | Disabling this is usually safe for small single-platform |
1533 | configurations. If unsure, say y. | |
7d485f64 | 1534 | |
c1b2d970 | 1535 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1536 | int "Maximum zone order" |
898f08e1 | 1537 | default "12" if SOC_AM33XX |
cc611137 | 1538 | default "9" if SA1111 |
c1b2d970 MD |
1539 | default "11" |
1540 | help | |
1541 | The kernel memory allocator divides physically contiguous memory | |
1542 | blocks into "zones", where each zone is a power of two number of | |
1543 | pages. This option selects the largest power of two that the kernel | |
1544 | keeps in the memory allocator. If you need to allocate very large | |
1545 | blocks of physically contiguous memory, then you may need to | |
1546 | increase this value. | |
1547 | ||
1548 | This config option is actually maximum order plus one. For example, | |
1549 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1550 | ||
1da177e4 | 1551 | config ALIGNMENT_TRAP |
3e3f354b | 1552 | def_bool CPU_CP15_MMU |
e119bfff | 1553 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1554 | help |
84eb8d06 | 1555 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1556 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1557 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1558 | fetch/store instructions will be emulated in software if you say | |
1559 | here, which has a severe performance impact. This is necessary for | |
1560 | correct operation of some network protocols. With an IP-only | |
1561 | configuration it is safe to say N, otherwise say Y. | |
1562 | ||
39ec58f3 | 1563 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1564 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1565 | depends on MMU | |
39ec58f3 LB |
1566 | default y if CPU_FEROCEON |
1567 | help | |
1568 | Implement faster copy_to_user and clear_user methods for CPU | |
1569 | cores where a 8-word STM instruction give significantly higher | |
1570 | memory write throughput than a sequence of individual 32bit stores. | |
1571 | ||
1572 | A possible side effect is a slight increase in scheduling latency | |
1573 | between threads sharing the same address space if they invoke | |
1574 | such copy operations with large buffers. | |
1575 | ||
1576 | However, if the CPU data cache is using a write-allocate mode, | |
1577 | this option is unlikely to provide any performance gain. | |
1578 | ||
02c2433b SS |
1579 | config PARAVIRT |
1580 | bool "Enable paravirtualization code" | |
1581 | help | |
1582 | This changes the kernel so it can modify itself when it is run | |
1583 | under a hypervisor, potentially improving performance significantly | |
1584 | over full virtualization. | |
1585 | ||
1586 | config PARAVIRT_TIME_ACCOUNTING | |
1587 | bool "Paravirtual steal time accounting" | |
1588 | select PARAVIRT | |
02c2433b SS |
1589 | help |
1590 | Select this option to enable fine granularity task steal time | |
1591 | accounting. Time spent executing other tasks in parallel with | |
1592 | the current vCPU is discounted from the vCPU power. To account for | |
1593 | that, there can be a small performance impact. | |
1594 | ||
1595 | If in doubt, say N here. | |
1596 | ||
eff8d644 SS |
1597 | config XEN_DOM0 |
1598 | def_bool y | |
1599 | depends on XEN | |
1600 | ||
1601 | config XEN | |
c2ba1f7d | 1602 | bool "Xen guest support on ARM" |
85323a99 | 1603 | depends on ARM && AEABI && OF |
f880b67d | 1604 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1605 | depends on !GENERIC_ATOMIC64 |
7693decc | 1606 | depends on MMU |
51aaf81f | 1607 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1608 | select ARM_PSCI |
f21254cd | 1609 | select SWIOTLB |
83862ccf | 1610 | select SWIOTLB_XEN |
02c2433b | 1611 | select PARAVIRT |
eff8d644 SS |
1612 | help |
1613 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1614 | ||
f05eb1d2 AB |
1615 | config CC_HAVE_STACKPROTECTOR_TLS |
1616 | def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) | |
1617 | ||
189af465 AB |
1618 | config STACKPROTECTOR_PER_TASK |
1619 | bool "Use a unique stack canary value for each task" | |
9c46929e | 1620 | depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA |
f05eb1d2 AB |
1621 | depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS |
1622 | select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS | |
189af465 AB |
1623 | default y |
1624 | help | |
1625 | Due to the fact that GCC uses an ordinary symbol reference from | |
1626 | which to load the value of the stack canary, this value can only | |
1627 | change at reboot time on SMP systems, and all tasks running in the | |
1628 | kernel's address space are forced to use the same canary value for | |
1629 | the entire duration that the system is up. | |
1630 | ||
1631 | Enable this option to switch to a different method that uses a | |
1632 | different canary value for each task. | |
1633 | ||
1da177e4 LT |
1634 | endmenu |
1635 | ||
1636 | menu "Boot options" | |
1637 | ||
9eb8f674 GL |
1638 | config USE_OF |
1639 | bool "Flattened Device Tree support" | |
b1b3f49c | 1640 | select IRQ_DOMAIN |
9eb8f674 | 1641 | select OF |
9eb8f674 GL |
1642 | help |
1643 | Include support for flattened device tree machine descriptions. | |
1644 | ||
bd51e2f5 NP |
1645 | config ATAGS |
1646 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1647 | default y | |
1648 | help | |
1649 | This is the traditional way of passing data to the kernel at boot | |
1650 | time. If you are solely relying on the flattened device tree (or | |
1651 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1652 | to remove ATAGS support from your kernel binary. If unsure, | |
1653 | leave this to y. | |
1654 | ||
1655 | config DEPRECATED_PARAM_STRUCT | |
1656 | bool "Provide old way to pass kernel parameters" | |
1657 | depends on ATAGS | |
1658 | help | |
1659 | This was deprecated in 2001 and announced to live on for 5 years. | |
1660 | Some old boot loaders still use this way. | |
1661 | ||
1da177e4 LT |
1662 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1663 | # TEXT and BSS so we preserve their values in the config files. | |
1664 | config ZBOOT_ROM_TEXT | |
1665 | hex "Compressed ROM boot loader base address" | |
39c3e304 | 1666 | default 0x0 |
1da177e4 LT |
1667 | help |
1668 | The physical address at which the ROM-able zImage is to be | |
1669 | placed in the target. Platforms which normally make use of | |
1670 | ROM-able zImage formats normally set this to a suitable | |
1671 | value in their defconfig file. | |
1672 | ||
1673 | If ZBOOT_ROM is not enabled, this has no effect. | |
1674 | ||
1675 | config ZBOOT_ROM_BSS | |
1676 | hex "Compressed ROM boot loader BSS address" | |
39c3e304 | 1677 | default 0x0 |
1da177e4 | 1678 | help |
f8c440b2 DF |
1679 | The base address of an area of read/write memory in the target |
1680 | for the ROM-able zImage which must be available while the | |
1681 | decompressor is running. It must be large enough to hold the | |
1682 | entire decompressed kernel plus an additional 128 KiB. | |
1683 | Platforms which normally make use of ROM-able zImage formats | |
1684 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1685 | |
1686 | If ZBOOT_ROM is not enabled, this has no effect. | |
1687 | ||
1688 | config ZBOOT_ROM | |
1689 | bool "Compressed boot loader in ROM/flash" | |
1690 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1691 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1692 | help |
1693 | Say Y here if you intend to execute your compressed kernel image | |
1694 | (zImage) directly from ROM or flash. If unsure, say N. | |
1695 | ||
e2a6a3aa JB |
1696 | config ARM_APPENDED_DTB |
1697 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1698 | depends on OF |
e2a6a3aa JB |
1699 | help |
1700 | With this option, the boot code will look for a device tree binary | |
1701 | (DTB) appended to zImage | |
1702 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1703 | ||
1704 | This is meant as a backward compatibility convenience for those | |
1705 | systems with a bootloader that can't be upgraded to accommodate | |
1706 | the documented boot protocol using a device tree. | |
1707 | ||
1708 | Beware that there is very little in terms of protection against | |
1709 | this option being confused by leftover garbage in memory that might | |
1710 | look like a DTB header after a reboot if no actual DTB is appended | |
1711 | to zImage. Do not leave this option active in a production kernel | |
1712 | if you don't intend to always append a DTB. Proper passing of the | |
1713 | location into r2 of a bootloader provided DTB is always preferable | |
1714 | to this option. | |
1715 | ||
b90b9a38 NP |
1716 | config ARM_ATAG_DTB_COMPAT |
1717 | bool "Supplement the appended DTB with traditional ATAG information" | |
1718 | depends on ARM_APPENDED_DTB | |
1719 | help | |
1720 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1721 | they provide ATAGs with memory configuration, the ramdisk address, | |
1722 | the kernel cmdline string, etc. Such information is dynamically | |
1723 | provided by the bootloader and can't always be stored in a static | |
1724 | DTB. To allow a device tree enabled kernel to be used with such | |
1725 | bootloaders, this option allows zImage to extract the information | |
1726 | from the ATAG list and store it at run time into the appended DTB. | |
1727 | ||
d0f34a11 GR |
1728 | choice |
1729 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1730 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1731 | ||
1732 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1733 | bool "Use bootloader kernel arguments if available" | |
1734 | help | |
1735 | Uses the command-line options passed by the boot loader instead of | |
1736 | the device tree bootargs property. If the boot loader doesn't provide | |
1737 | any, the device tree bootargs property will be used. | |
1738 | ||
1739 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1740 | bool "Extend with bootloader kernel arguments" | |
1741 | help | |
1742 | The command-line arguments provided by the boot loader will be | |
1743 | appended to the the device tree bootargs property. | |
1744 | ||
1745 | endchoice | |
1746 | ||
1da177e4 LT |
1747 | config CMDLINE |
1748 | string "Default kernel command string" | |
1749 | default "" | |
1750 | help | |
3e3f354b | 1751 | On some architectures (e.g. CATS), there is currently no way |
1da177e4 LT |
1752 | for the boot loader to pass arguments to the kernel. For these |
1753 | architectures, you should supply some command-line options at build | |
1754 | time by entering them here. As a minimum, you should specify the | |
1755 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1756 | ||
4394c124 VB |
1757 | choice |
1758 | prompt "Kernel command line type" if CMDLINE != "" | |
1759 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1760 | depends on ATAGS |
4394c124 VB |
1761 | |
1762 | config CMDLINE_FROM_BOOTLOADER | |
1763 | bool "Use bootloader kernel arguments if available" | |
1764 | help | |
1765 | Uses the command-line options passed by the boot loader. If | |
1766 | the boot loader doesn't provide any, the default kernel command | |
1767 | string provided in CMDLINE will be used. | |
1768 | ||
1769 | config CMDLINE_EXTEND | |
1770 | bool "Extend bootloader kernel arguments" | |
1771 | help | |
1772 | The command-line arguments provided by the boot loader will be | |
1773 | appended to the default kernel command string. | |
1774 | ||
92d2040d AH |
1775 | config CMDLINE_FORCE |
1776 | bool "Always use the default kernel command string" | |
92d2040d AH |
1777 | help |
1778 | Always use the default kernel command string, even if the boot | |
1779 | loader passes other arguments to the kernel. | |
1780 | This is useful if you cannot or don't want to change the | |
1781 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1782 | endchoice |
92d2040d | 1783 | |
1da177e4 LT |
1784 | config XIP_KERNEL |
1785 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1786 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1787 | help |
1788 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1789 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1790 | space since the text section of the kernel is not loaded from flash | |
1791 | to RAM. Read-write sections, such as the data section and stack, | |
1792 | are still copied to RAM. The XIP kernel is not compressed since | |
1793 | it has to run directly from flash, so it will take more space to | |
1794 | store it. The flash address used to link the kernel object files, | |
1795 | and for storing it, is configuration dependent. Therefore, if you | |
1796 | say Y here, you must know the proper physical address where to | |
1797 | store the kernel image depending on your own flash memory usage. | |
1798 | ||
1799 | Also note that the make target becomes "make xipImage" rather than | |
1800 | "make zImage" or "make Image". The final kernel binary to put in | |
1801 | ROM memory will be arch/arm/boot/xipImage. | |
1802 | ||
1803 | If unsure, say N. | |
1804 | ||
1805 | config XIP_PHYS_ADDR | |
1806 | hex "XIP Kernel Physical Location" | |
1807 | depends on XIP_KERNEL | |
1808 | default "0x00080000" | |
1809 | help | |
1810 | This is the physical address in your flash memory the kernel will | |
1811 | be linked for and stored to. This address is dependent on your | |
1812 | own flash usage. | |
1813 | ||
ca8b5d97 NP |
1814 | config XIP_DEFLATED_DATA |
1815 | bool "Store kernel .data section compressed in ROM" | |
1816 | depends on XIP_KERNEL | |
1817 | select ZLIB_INFLATE | |
1818 | help | |
1819 | Before the kernel is actually executed, its .data section has to be | |
1820 | copied to RAM from ROM. This option allows for storing that data | |
1821 | in compressed form and decompressed to RAM rather than merely being | |
1822 | copied, saving some precious ROM space. A possible drawback is a | |
1823 | slightly longer boot delay. | |
1824 | ||
c587e4a6 RP |
1825 | config KEXEC |
1826 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1827 | depends on (!SMP || PM_SLEEP_SMP) |
76950f71 | 1828 | depends on MMU |
2965faa5 | 1829 | select KEXEC_CORE |
c587e4a6 RP |
1830 | help |
1831 | kexec is a system call that implements the ability to shutdown your | |
1832 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1833 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1834 | you can start any kernel with it, not just Linux. |
1835 | ||
1836 | It is an ongoing process to be certain the hardware in a machine | |
1837 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1838 | initially work for you. |
c587e4a6 | 1839 | |
4cd9d6f7 RP |
1840 | config ATAGS_PROC |
1841 | bool "Export atags in procfs" | |
bd51e2f5 | 1842 | depends on ATAGS && KEXEC |
b98d7291 | 1843 | default y |
4cd9d6f7 RP |
1844 | help |
1845 | Should the atags used to boot the kernel be exported in an "atags" | |
1846 | file in procfs. Useful with kexec. | |
1847 | ||
cb5d39b3 MW |
1848 | config CRASH_DUMP |
1849 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
1850 | help |
1851 | Generate crash dump after being started by kexec. This should | |
1852 | be normally only set in special crash dump kernels which are | |
1853 | loaded in the main kernel with kexec-tools into a specially | |
1854 | reserved region and then later executed after a crash by | |
1855 | kdump/kexec. The crash dump kernel must be compiled to a | |
1856 | memory address not used by the main kernel | |
1857 | ||
330d4810 | 1858 | For more details see Documentation/admin-guide/kdump/kdump.rst |
cb5d39b3 | 1859 | |
e69edc79 EM |
1860 | config AUTO_ZRELADDR |
1861 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
1862 | help |
1863 | ZRELADDR is the physical address where the decompressed kernel | |
1864 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
0673cb38 GU |
1865 | will be determined at run-time, either by masking the current IP |
1866 | with 0xf8000000, or, if invalid, from the DTB passed in r2. | |
1867 | This assumes the zImage being placed in the first 128MB from | |
1868 | start of memory. | |
e69edc79 | 1869 | |
81a0bc39 RF |
1870 | config EFI_STUB |
1871 | bool | |
1872 | ||
1873 | config EFI | |
1874 | bool "UEFI runtime support" | |
1875 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
1876 | select UCS2_STRING | |
1877 | select EFI_PARAMS_FROM_FDT | |
1878 | select EFI_STUB | |
2e0eb483 | 1879 | select EFI_GENERIC_STUB |
81a0bc39 | 1880 | select EFI_RUNTIME_WRAPPERS |
a7f7f624 | 1881 | help |
81a0bc39 RF |
1882 | This option provides support for runtime services provided |
1883 | by UEFI firmware (such as non-volatile variables, realtime | |
1884 | clock, and platform reset). A UEFI stub is also provided to | |
1885 | allow the kernel to be booted as an EFI application. This | |
1886 | is only useful for kernels that may run on systems that have | |
1887 | UEFI firmware. | |
1888 | ||
bb817bef AB |
1889 | config DMI |
1890 | bool "Enable support for SMBIOS (DMI) tables" | |
1891 | depends on EFI | |
1892 | default y | |
1893 | help | |
1894 | This enables SMBIOS/DMI feature for systems. | |
1895 | ||
1896 | This option is only useful on systems that have UEFI firmware. | |
1897 | However, even with this option, the resultant kernel should | |
1898 | continue to boot on existing non-UEFI platforms. | |
1899 | ||
1900 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
1901 | i.e., the the practice of identifying the platform via DMI to | |
1902 | decide whether certain workarounds for buggy hardware and/or | |
1903 | firmware need to be enabled. This would require the DMI subsystem | |
1904 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
1905 | ||
1da177e4 LT |
1906 | endmenu |
1907 | ||
ac9d7efc | 1908 | menu "CPU Power Management" |
1da177e4 | 1909 | |
1da177e4 | 1910 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 1911 | |
ac9d7efc RK |
1912 | source "drivers/cpuidle/Kconfig" |
1913 | ||
1914 | endmenu | |
1915 | ||
1da177e4 LT |
1916 | menu "Floating point emulation" |
1917 | ||
1918 | comment "At least one emulation must be selected" | |
1919 | ||
1920 | config FPE_NWFPE | |
1921 | bool "NWFPE math emulation" | |
593c252a | 1922 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
a7f7f624 | 1923 | help |
1da177e4 LT |
1924 | Say Y to include the NWFPE floating point emulator in the kernel. |
1925 | This is necessary to run most binaries. Linux does not currently | |
1926 | support floating point hardware so you need to say Y here even if | |
1927 | your machine has an FPA or floating point co-processor podule. | |
1928 | ||
1929 | You may say N here if you are going to load the Acorn FPEmulator | |
1930 | early in the bootup. | |
1931 | ||
1932 | config FPE_NWFPE_XP | |
1933 | bool "Support extended precision" | |
bedf142b | 1934 | depends on FPE_NWFPE |
1da177e4 LT |
1935 | help |
1936 | Say Y to include 80-bit support in the kernel floating-point | |
1937 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
1938 | Note that gcc does not generate 80-bit operations by default, | |
1939 | so in most cases this option only enlarges the size of the | |
1940 | floating point emulator without any good reason. | |
1941 | ||
1942 | You almost surely want to say N here. | |
1943 | ||
1944 | config FPE_FASTFPE | |
1945 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 1946 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
a7f7f624 | 1947 | help |
1da177e4 LT |
1948 | Say Y here to include the FAST floating point emulator in the kernel. |
1949 | This is an experimental much faster emulator which now also has full | |
1950 | precision for the mantissa. It does not support any exceptions. | |
1951 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
1952 | ||
1953 | It should be sufficient for most programs. It may be not suitable | |
1954 | for scientific calculations, but you have to check this for yourself. | |
1955 | If you do not feel you need a faster FP emulation you should better | |
1956 | choose NWFPE. | |
1957 | ||
1958 | config VFP | |
1959 | bool "VFP-format floating point maths" | |
e399b1a4 | 1960 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
1961 | help |
1962 | Say Y to include VFP support code in the kernel. This is needed | |
1963 | if your hardware includes a VFP unit. | |
1964 | ||
dc7a12bd | 1965 | Please see <file:Documentation/arm/vfp/release-notes.rst> for |
1da177e4 LT |
1966 | release notes and additional status information. |
1967 | ||
1968 | Say N if your target does not have VFP hardware. | |
1969 | ||
25ebee02 CM |
1970 | config VFPv3 |
1971 | bool | |
1972 | depends on VFP | |
1973 | default y if CPU_V7 | |
1974 | ||
b5872db4 CM |
1975 | config NEON |
1976 | bool "Advanced SIMD (NEON) Extension support" | |
1977 | depends on VFPv3 && CPU_V7 | |
1978 | help | |
1979 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
1980 | Extension. | |
1981 | ||
73c132c1 AB |
1982 | config KERNEL_MODE_NEON |
1983 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 1984 | depends on NEON && AEABI |
73c132c1 AB |
1985 | help |
1986 | Say Y to include support for NEON in kernel mode. | |
1987 | ||
1da177e4 LT |
1988 | endmenu |
1989 | ||
1da177e4 LT |
1990 | menu "Power management options" |
1991 | ||
eceab4ac | 1992 | source "kernel/power/Kconfig" |
1da177e4 | 1993 | |
f4cb5700 | 1994 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 1995 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 1996 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
1997 | def_bool y |
1998 | ||
15e0d9e3 | 1999 | config ARM_CPU_SUSPEND |
8b6f2499 | 2000 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 2001 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 2002 | |
603fb42a SC |
2003 | config ARCH_HIBERNATION_POSSIBLE |
2004 | bool | |
2005 | depends on MMU | |
2006 | default y if ARCH_SUSPEND_POSSIBLE | |
2007 | ||
1da177e4 LT |
2008 | endmenu |
2009 | ||
652ccae5 AB |
2010 | if CRYPTO |
2011 | source "arch/arm/crypto/Kconfig" | |
2012 | endif | |
2cbd1cc3 SA |
2013 | |
2014 | source "arch/arm/Kconfig.assembler" |