Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
aef0f78e | 6 | select ARCH_HAS_BINFMT_FLAT |
c7780ab5 | 7 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
419e2f18 | 8 | select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE |
2b68f6ca | 9 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 10 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 11 | select ARCH_HAS_KEEPINITRD |
75851720 | 12 | select ARCH_HAS_KCOV |
e69244d2 | 13 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 14 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
3010a5ea | 15 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
ea8c64ac | 16 | select ARCH_HAS_PHYS_TO_DMA |
347cb6af | 17 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 18 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
19 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
20 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
936376f8 CH |
21 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB |
22 | select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB | |
dc2acded | 23 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 24 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 25 | select ARCH_HAVE_CUSTOM_GPIO_H |
9aaf9bb7 | 26 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K |
957e3fac | 27 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e545df3 | 28 | select ARCH_KEEP_MEMBLOCK |
d7018848 | 29 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7c703e54 | 30 | select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN |
ad21fc4f LA |
31 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
32 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 33 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 34 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 35 | select ARCH_USE_CMPXCHG_LOCKREF |
dba79c3d | 36 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
b1b3f49c | 37 | select ARCH_WANT_IPC_PARSE_VERSION |
59612b24 | 38 | select ARCH_WANT_LD_ORPHAN_WARN |
bdd15a28 | 39 | select BINFMT_FLAT_ARGVP_ENVP_ON_STACK |
10916706 | 40 | select BUILDTIME_TABLE_SORT if MMU |
171b3f0d | 41 | select CLONE_BACKWARDS |
f00790aa | 42 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 43 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 44 | select DMA_DECLARE_COHERENT |
2f9237d4 | 45 | select DMA_OPS |
f0edfea8 | 46 | select DMA_REMAP if MMU |
b01aec9b BP |
47 | select EDAC_SUPPORT |
48 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 49 | select GENERIC_ALLOCATOR |
2ef7a295 | 50 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 51 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 52 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
56afcd3d | 53 | select GENERIC_IRQ_IPI if SMP |
ea2d9a96 | 54 | select GENERIC_CPU_AUTOPROBE |
2937367b | 55 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 56 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
57 | select GENERIC_IRQ_PROBE |
58 | select GENERIC_IRQ_SHOW | |
7c07005e | 59 | select GENERIC_IRQ_SHOW_LEVEL |
914ee966 | 60 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
b1b3f49c | 61 | select GENERIC_PCI_IOMAP |
38ff87f7 | 62 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
63 | select GENERIC_SMP_IDLE_THREAD |
64 | select GENERIC_STRNCPY_FROM_USER | |
65 | select GENERIC_STRNLEN_USER | |
a71b092a | 66 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 67 | select HARDIRQS_SW_RESEND |
f00790aa | 68 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 69 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee AB |
70 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
71 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU | |
42101571 | 72 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL |
e0c25d95 | 73 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
4f5b0c17 | 74 | select HAVE_ARCH_PFN_VALID |
282a181b | 75 | select HAVE_ARCH_SECCOMP |
f00790aa | 76 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 77 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 78 | select HAVE_ARCH_TRACEHOOK |
b329f95d | 79 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 80 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 81 | select HAVE_CONTEXT_TRACKING |
b1b3f49c | 82 | select HAVE_C_RECORDMCOUNT |
bc420c6c | 83 | select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL |
b1b3f49c | 84 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 85 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 86 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 87 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 88 | select HAVE_EXIT_THREAD |
67a929e0 | 89 | select HAVE_FAST_GUP if ARM_LPAE |
f00790aa | 90 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
50362162 | 91 | select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG |
3511af0a | 92 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 93 | select HAVE_GCC_PLUGINS |
f00790aa | 94 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
b1b3f49c | 95 | select HAVE_IDE if PCI || ISA || PCMCIA |
87c46b6c | 96 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 97 | select HAVE_KERNEL_GZIP |
f9b493ac | 98 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 99 | select HAVE_KERNEL_LZMA |
b1b3f49c | 100 | select HAVE_KERNEL_LZO |
a7f464f3 | 101 | select HAVE_KERNEL_XZ |
cb1293e2 | 102 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 103 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 104 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 105 | select HAVE_NMI |
0dc016db | 106 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 107 | select HAVE_PERF_EVENTS |
49863894 WD |
108 | select HAVE_PERF_REGS |
109 | select HAVE_PERF_USER_STACK_DUMP | |
ff2e6d72 | 110 | select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 111 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 112 | select HAVE_RSEQ |
d148eac0 | 113 | select HAVE_STACKPROTECTOR |
b1b3f49c | 114 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 115 | select HAVE_UID16 |
31c1fc81 | 116 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 117 | select IRQ_FORCED_THREADING |
171b3f0d | 118 | select MODULES_USE_ELF_REL |
f616ab59 | 119 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 120 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
121 | select OLD_SIGACTION |
122 | select OLD_SIGSUSPEND3 | |
20f1b79d | 123 | select PCI_SYSCALL if PCI |
b1b3f49c RK |
124 | select PERF_USE_VMALLOC |
125 | select RTC_LIB | |
5e6e9852 | 126 | select SET_FS |
b1b3f49c | 127 | select SYS_SUPPORTS_APM_EMULATION |
171b3f0d RK |
128 | # Above selects are sorted alphabetically; please add new ones |
129 | # according to that. Thanks. | |
1da177e4 LT |
130 | help |
131 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 132 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 133 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 134 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
135 | Europe. There is an ARM Linux project with a web page at |
136 | <http://www.arm.linux.org.uk/>. | |
137 | ||
74facffe RK |
138 | config ARM_HAS_SG_CHAIN |
139 | bool | |
140 | ||
4ce63fcd | 141 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 142 | bool |
b1b3f49c RK |
143 | select ARM_HAS_SG_CHAIN |
144 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 145 | |
60460abf SWK |
146 | if ARM_DMA_USE_IOMMU |
147 | ||
148 | config ARM_DMA_IOMMU_ALIGNMENT | |
149 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
150 | range 4 9 | |
151 | default 8 | |
152 | help | |
153 | DMA mapping framework by default aligns all buffers to the smallest | |
154 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
155 | size. This works well for buffers up to a few hundreds kilobytes, but | |
156 | for larger buffers it just a waste of address space. Drivers which has | |
157 | relatively small addressing window (like 64Mib) might run out of | |
158 | virtual space with just a few allocations. | |
159 | ||
160 | With this parameter you can specify the maximum PAGE_SIZE order for | |
161 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
162 | specified order. The order is expressed as a power of two multiplied | |
163 | by the PAGE_SIZE. | |
164 | ||
165 | endif | |
166 | ||
75e7153a RB |
167 | config SYS_SUPPORTS_APM_EMULATION |
168 | bool | |
169 | ||
bc581770 LW |
170 | config HAVE_TCM |
171 | bool | |
172 | select GENERIC_ALLOCATOR | |
173 | ||
e119bfff RK |
174 | config HAVE_PROC_CPU |
175 | bool | |
176 | ||
ce816fa8 | 177 | config NO_IOPORT_MAP |
5ea81769 | 178 | bool |
5ea81769 | 179 | |
1da177e4 LT |
180 | config SBUS |
181 | bool | |
182 | ||
f16fb1ec RK |
183 | config STACKTRACE_SUPPORT |
184 | bool | |
185 | default y | |
186 | ||
187 | config LOCKDEP_SUPPORT | |
188 | bool | |
189 | default y | |
190 | ||
7ad1bcb2 RK |
191 | config TRACE_IRQFLAGS_SUPPORT |
192 | bool | |
cb1293e2 | 193 | default !CPU_V7M |
7ad1bcb2 | 194 | |
f0d1b0b3 DH |
195 | config ARCH_HAS_ILOG2_U32 |
196 | bool | |
f0d1b0b3 DH |
197 | |
198 | config ARCH_HAS_ILOG2_U64 | |
199 | bool | |
f0d1b0b3 | 200 | |
4a1b5733 EV |
201 | config ARCH_HAS_BANDGAP |
202 | bool | |
203 | ||
a5f4c561 SA |
204 | config FIX_EARLYCON_MEM |
205 | def_bool y if MMU | |
206 | ||
b89c3b16 AM |
207 | config GENERIC_HWEIGHT |
208 | bool | |
209 | default y | |
210 | ||
1da177e4 LT |
211 | config GENERIC_CALIBRATE_DELAY |
212 | bool | |
213 | default y | |
214 | ||
a08b6b79 Z |
215 | config ARCH_MAY_HAVE_PC_FDC |
216 | bool | |
217 | ||
5ac6da66 CL |
218 | config ZONE_DMA |
219 | bool | |
5ac6da66 | 220 | |
c7edc9e3 DL |
221 | config ARCH_SUPPORTS_UPROBES |
222 | def_bool y | |
223 | ||
58af4a24 RH |
224 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
225 | bool | |
226 | ||
1da177e4 LT |
227 | config GENERIC_ISA_DMA |
228 | bool | |
229 | ||
1da177e4 LT |
230 | config FIQ |
231 | bool | |
232 | ||
13a5045d RH |
233 | config NEED_RET_TO_USER |
234 | bool | |
235 | ||
034d2f5a AV |
236 | config ARCH_MTD_XIP |
237 | bool | |
238 | ||
dc21af99 | 239 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
240 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
241 | default y | |
b511d75d | 242 | depends on !XIP_KERNEL && MMU |
dc21af99 | 243 | help |
111e9a5c RK |
244 | Patch phys-to-virt and virt-to-phys translation functions at |
245 | boot and module load time according to the position of the | |
246 | kernel in system memory. | |
dc21af99 | 247 | |
111e9a5c | 248 | This can only be used with non-XIP MMU kernels where the base |
9443076e | 249 | of physical memory is at a 2 MiB boundary. |
dc21af99 | 250 | |
c1becedc RK |
251 | Only disable this option if you know that you do not require |
252 | this feature (eg, building a kernel for a single machine) and | |
253 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 254 | |
c334bc15 RH |
255 | config NEED_MACH_IO_H |
256 | bool | |
257 | help | |
258 | Select this when mach/io.h is required to provide special | |
259 | definitions for this platform. The need for mach/io.h should | |
260 | be avoided when possible. | |
261 | ||
0cdc8b92 | 262 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
263 | bool |
264 | help | |
0cdc8b92 NP |
265 | Select this when mach/memory.h is required to provide special |
266 | definitions for this platform. The need for mach/memory.h should | |
267 | be avoided when possible. | |
dc21af99 | 268 | |
1b9f95f8 | 269 | config PHYS_OFFSET |
974c0724 | 270 | hex "Physical address of main memory" if MMU |
c6f54a9b | 271 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 272 | default DRAM_BASE if !MMU |
3e3f354b | 273 | default 0x00000000 if ARCH_FOOTBRIDGE |
c6f54a9b UKK |
274 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
275 | default 0x20000000 if ARCH_S5PV210 | |
b8824c9a | 276 | default 0xc0000000 if ARCH_SA1100 |
111e9a5c | 277 | help |
1b9f95f8 NP |
278 | Please provide the physical address corresponding to the |
279 | location of main memory in your system. | |
cada3c08 | 280 | |
87e040b6 SG |
281 | config GENERIC_BUG |
282 | def_bool y | |
283 | depends on BUG | |
284 | ||
1bcad26e KS |
285 | config PGTABLE_LEVELS |
286 | int | |
287 | default 3 if ARM_LPAE | |
288 | default 2 | |
289 | ||
1da177e4 LT |
290 | menu "System Type" |
291 | ||
3c427975 HC |
292 | config MMU |
293 | bool "MMU-based Paged Memory Management Support" | |
294 | default y | |
295 | help | |
296 | Select if you want MMU-based virtualised addressing space | |
297 | support by paged memory management. If unsure, say 'Y'. | |
298 | ||
e0c25d95 DC |
299 | config ARCH_MMAP_RND_BITS_MIN |
300 | default 8 | |
301 | ||
302 | config ARCH_MMAP_RND_BITS_MAX | |
303 | default 14 if PAGE_OFFSET=0x40000000 | |
304 | default 15 if PAGE_OFFSET=0x80000000 | |
305 | default 16 | |
306 | ||
ccf50e23 RK |
307 | # |
308 | # The "ARM system type" choice list is ordered alphabetically by option | |
309 | # text. Please add new entries in the option alphabetic order. | |
310 | # | |
1da177e4 LT |
311 | choice |
312 | prompt "ARM system type" | |
70722803 | 313 | default ARM_SINGLE_ARMV7M if !MMU |
1420b22b | 314 | default ARCH_MULTIPLATFORM if MMU |
1da177e4 | 315 | |
387798b3 RH |
316 | config ARCH_MULTIPLATFORM |
317 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 318 | depends on MMU |
fb597f2a GF |
319 | select ARCH_FLATMEM_ENABLE |
320 | select ARCH_SPARSEMEM_ENABLE | |
321 | select ARCH_SELECT_MEMORY_MODEL | |
42dc836d | 322 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
323 | select ARM_PATCH_PHYS_VIRT |
324 | select AUTO_ZRELADDR | |
bb0eb050 | 325 | select TIMER_OF |
66314223 | 326 | select COMMON_CLK |
4c301f9b | 327 | select GENERIC_IRQ_MULTI_HANDLER |
eb01d42a | 328 | select HAVE_PCI |
2eac9c2d | 329 | select PCI_DOMAINS_GENERIC if PCI |
66314223 DN |
330 | select SPARSE_IRQ |
331 | select USE_OF | |
66314223 | 332 | |
9c77bc43 SA |
333 | config ARM_SINGLE_ARMV7M |
334 | bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" | |
335 | depends on !MMU | |
9c77bc43 | 336 | select ARM_NVIC |
499f1640 | 337 | select AUTO_ZRELADDR |
bb0eb050 | 338 | select TIMER_OF |
9c77bc43 SA |
339 | select COMMON_CLK |
340 | select CPU_V7M | |
9c77bc43 SA |
341 | select NO_IOPORT_MAP |
342 | select SPARSE_IRQ | |
343 | select USE_OF | |
344 | ||
e7736d47 LB |
345 | config ARCH_EP93XX |
346 | bool "EP93xx-based" | |
80320927 | 347 | select ARCH_SPARSEMEM_ENABLE |
e7736d47 | 348 | select ARM_AMBA |
cd5bad41 | 349 | imply ARM_PATCH_PHYS_VIRT |
e7736d47 | 350 | select ARM_VIC |
b8824c9a | 351 | select AUTO_ZRELADDR |
6d803ba7 | 352 | select CLKDEV_LOOKUP |
000bc178 | 353 | select CLKSRC_MMIO |
b1b3f49c | 354 | select CPU_ARM920T |
5c34a4e8 | 355 | select GPIOLIB |
bbd7ffdb | 356 | select HAVE_LEGACY_CLK |
e7736d47 LB |
357 | help |
358 | This enables support for the Cirrus EP93xx series of CPUs. | |
359 | ||
1da177e4 LT |
360 | config ARCH_FOOTBRIDGE |
361 | bool "FootBridge" | |
c750815e | 362 | select CPU_SA110 |
1da177e4 | 363 | select FOOTBRIDGE |
d0ee9f40 | 364 | select HAVE_IDE |
8ef6e620 | 365 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 366 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
367 | help |
368 | Support for systems based on the DC21285 companion chip | |
369 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 370 | |
3f7e5815 LB |
371 | config ARCH_IOP32X |
372 | bool "IOP32x-based" | |
a4f7e763 | 373 | depends on MMU |
c750815e | 374 | select CPU_XSCALE |
e9004f50 | 375 | select GPIO_IOP |
5c34a4e8 | 376 | select GPIOLIB |
13a5045d | 377 | select NEED_RET_TO_USER |
eb01d42a | 378 | select FORCE_PCI |
b1b3f49c | 379 | select PLAT_IOP |
f999b8bd | 380 | help |
3f7e5815 LB |
381 | Support for Intel's 80219 and IOP32X (XScale) family of |
382 | processors. | |
383 | ||
3b938be6 RK |
384 | config ARCH_IXP4XX |
385 | bool "IXP4xx-based" | |
a4f7e763 | 386 | depends on MMU |
58af4a24 | 387 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
51aaf81f | 388 | select ARCH_SUPPORTS_BIG_ENDIAN |
c750815e | 389 | select CPU_XSCALE |
b1b3f49c | 390 | select DMABOUNCE if PCI |
98ac0cc2 | 391 | select GENERIC_IRQ_MULTI_HANDLER |
55ec465e | 392 | select GPIO_IXP4XX |
5c34a4e8 | 393 | select GPIOLIB |
eb01d42a | 394 | select HAVE_PCI |
55ec465e | 395 | select IXP4XX_IRQ |
65af6667 | 396 | select IXP4XX_TIMER |
c334bc15 | 397 | select NEED_MACH_IO_H |
9296d94d | 398 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 399 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 400 | help |
3b938be6 | 401 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 402 | |
edabd38e SB |
403 | config ARCH_DOVE |
404 | bool "Marvell Dove" | |
756b2531 | 405 | select CPU_PJ4 |
4c301f9b | 406 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 407 | select GPIOLIB |
eb01d42a | 408 | select HAVE_PCI |
171b3f0d | 409 | select MVEBU_MBUS |
9139acd1 SH |
410 | select PINCTRL |
411 | select PINCTRL_DOVE | |
abcda1dc | 412 | select PLAT_ORION_LEGACY |
0bd86961 | 413 | select SPARSE_IRQ |
c5d431e8 | 414 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 415 | help |
edabd38e | 416 | Support for the Marvell Dove SoC 88AP510 |
788c9700 | 417 | |
1da177e4 | 418 | config ARCH_PXA |
2c8086a5 | 419 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 420 | depends on MMU |
b1b3f49c | 421 | select ARCH_MTD_XIP |
b1b3f49c RK |
422 | select ARM_CPU_SUSPEND if PM |
423 | select AUTO_ZRELADDR | |
a1c0a6ad | 424 | select COMMON_CLK |
389d9b58 | 425 | select CLKSRC_PXA |
234b6ced | 426 | select CLKSRC_MMIO |
bb0eb050 | 427 | select TIMER_OF |
2f202861 | 428 | select CPU_XSCALE if !CPU_XSC3 |
4c301f9b | 429 | select GENERIC_IRQ_MULTI_HANDLER |
157d2644 | 430 | select GPIO_PXA |
5c34a4e8 | 431 | select GPIOLIB |
d0ee9f40 | 432 | select HAVE_IDE |
d6cf30ca | 433 | select IRQ_DOMAIN |
b1b3f49c RK |
434 | select PLAT_PXA |
435 | select SPARSE_IRQ | |
f999b8bd | 436 | help |
2c8086a5 | 437 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
438 | |
439 | config ARCH_RPC | |
440 | bool "RiscPC" | |
868e87cc | 441 | depends on MMU |
1da177e4 | 442 | select ARCH_ACORN |
a08b6b79 | 443 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 444 | select ARCH_SPARSEMEM_ENABLE |
0b40deee | 445 | select ARM_HAS_SG_CHAIN |
fa04e209 | 446 | select CPU_SA110 |
b1b3f49c | 447 | select FIQ |
d0ee9f40 | 448 | select HAVE_IDE |
b1b3f49c RK |
449 | select HAVE_PATA_PLATFORM |
450 | select ISA_DMA_API | |
6239da29 | 451 | select LEGACY_TIMER_TICK |
c334bc15 | 452 | select NEED_MACH_IO_H |
0cdc8b92 | 453 | select NEED_MACH_MEMORY_H |
ce816fa8 | 454 | select NO_IOPORT_MAP |
1da177e4 LT |
455 | help |
456 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
457 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
458 | ||
459 | config ARCH_SA1100 | |
460 | bool "SA1100-based" | |
b1b3f49c | 461 | select ARCH_MTD_XIP |
b1b3f49c | 462 | select ARCH_SPARSEMEM_ENABLE |
b1b3f49c | 463 | select CLKSRC_MMIO |
389d9b58 | 464 | select CLKSRC_PXA |
bb0eb050 | 465 | select TIMER_OF if OF |
d6c82046 | 466 | select COMMON_CLK |
1937f5b9 | 467 | select CPU_FREQ |
b1b3f49c | 468 | select CPU_SA1100 |
4c301f9b | 469 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 470 | select GPIOLIB |
d0ee9f40 | 471 | select HAVE_IDE |
1eca42b4 | 472 | select IRQ_DOMAIN |
b1b3f49c | 473 | select ISA |
0cdc8b92 | 474 | select NEED_MACH_MEMORY_H |
375dec92 | 475 | select SPARSE_IRQ |
f999b8bd MM |
476 | help |
477 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 478 | |
b130d5c2 KK |
479 | config ARCH_S3C24XX |
480 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 481 | select ATAGS |
4280506a | 482 | select CLKSRC_SAMSUNG_PWM |
880cf071 | 483 | select GPIO_SAMSUNG |
5c34a4e8 | 484 | select GPIOLIB |
4c301f9b | 485 | select GENERIC_IRQ_MULTI_HANDLER |
20676c15 | 486 | select HAVE_S3C2410_I2C if I2C |
b1b3f49c | 487 | select HAVE_S3C_RTC if RTC_CLASS |
c334bc15 | 488 | select NEED_MACH_IO_H |
f6d7cde8 | 489 | select S3C2410_WATCHDOG |
cd8dc7ae | 490 | select SAMSUNG_ATAGS |
ea04d6b4 | 491 | select USE_OF |
f6d7cde8 | 492 | select WATCHDOG |
1da177e4 | 493 | help |
b130d5c2 KK |
494 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
495 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
496 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
497 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 498 | |
a0694861 TL |
499 | config ARCH_OMAP1 |
500 | bool "TI OMAP1" | |
00a36698 | 501 | depends on MMU |
a0694861 | 502 | select ARCH_OMAP |
b1b3f49c | 503 | select CLKDEV_LOOKUP |
d6e15d78 | 504 | select CLKSRC_MMIO |
a0694861 | 505 | select GENERIC_IRQ_CHIP |
4c301f9b | 506 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 507 | select GPIOLIB |
a0694861 | 508 | select HAVE_IDE |
bbd7ffdb | 509 | select HAVE_LEGACY_CLK |
a0694861 TL |
510 | select IRQ_DOMAIN |
511 | select NEED_MACH_IO_H if PCCARD | |
512 | select NEED_MACH_MEMORY_H | |
685e2d08 | 513 | select SPARSE_IRQ |
21f47fbc | 514 | help |
a0694861 | 515 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 516 | |
1da177e4 LT |
517 | endchoice |
518 | ||
387798b3 RH |
519 | menu "Multiple platform selection" |
520 | depends on ARCH_MULTIPLATFORM | |
521 | ||
522 | comment "CPU Core family selection" | |
523 | ||
f8afae40 AB |
524 | config ARCH_MULTI_V4 |
525 | bool "ARMv4 based platforms (FA526)" | |
526 | depends on !ARCH_MULTI_V6_V7 | |
527 | select ARCH_MULTI_V4_V5 | |
528 | select CPU_FA526 | |
529 | ||
387798b3 RH |
530 | config ARCH_MULTI_V4T |
531 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 532 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 533 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
534 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
535 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
536 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
537 | |
538 | config ARCH_MULTI_V5 | |
539 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 540 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 541 | select ARCH_MULTI_V4_V5 |
12567bbd | 542 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
543 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
544 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
545 | |
546 | config ARCH_MULTI_V4_V5 | |
547 | bool | |
548 | ||
549 | config ARCH_MULTI_V6 | |
8dda05cc | 550 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 551 | select ARCH_MULTI_V6_V7 |
42f4754a | 552 | select CPU_V6K |
387798b3 RH |
553 | |
554 | config ARCH_MULTI_V7 | |
8dda05cc | 555 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
556 | default y |
557 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 558 | select CPU_V7 |
90bc8ac7 | 559 | select HAVE_SMP |
387798b3 RH |
560 | |
561 | config ARCH_MULTI_V6_V7 | |
562 | bool | |
9352b05b | 563 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
564 | |
565 | config ARCH_MULTI_CPU_AUTO | |
566 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
567 | select ARCH_MULTI_V5 | |
568 | ||
569 | endmenu | |
570 | ||
05e2a3de | 571 | config ARCH_VIRT |
e3246542 MY |
572 | bool "Dummy Virtual Machine" |
573 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 574 | select ARM_AMBA |
05e2a3de | 575 | select ARM_GIC |
3ee80364 | 576 | select ARM_GIC_V2M if PCI |
0b28f1db | 577 | select ARM_GIC_V3 |
bb29cecb | 578 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 579 | select ARM_PSCI |
4b8b5f25 | 580 | select HAVE_ARM_ARCH_TIMER |
8e2649d0 | 581 | select ARCH_SUPPORTS_BIG_ENDIAN |
05e2a3de | 582 | |
ccf50e23 RK |
583 | # |
584 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
585 | # Kconfigs may be included either alphabetically (according to the | |
586 | # plat- suffix) or along side the corresponding mach-* source. | |
587 | # | |
6bb8536c AF |
588 | source "arch/arm/mach-actions/Kconfig" |
589 | ||
445d9b30 TZ |
590 | source "arch/arm/mach-alpine/Kconfig" |
591 | ||
590b460c LP |
592 | source "arch/arm/mach-artpec/Kconfig" |
593 | ||
d9bfc86d OR |
594 | source "arch/arm/mach-asm9260/Kconfig" |
595 | ||
a66c51f9 AB |
596 | source "arch/arm/mach-aspeed/Kconfig" |
597 | ||
95b8f20f RK |
598 | source "arch/arm/mach-at91/Kconfig" |
599 | ||
1d22924e AB |
600 | source "arch/arm/mach-axxia/Kconfig" |
601 | ||
8ac49e04 CD |
602 | source "arch/arm/mach-bcm/Kconfig" |
603 | ||
1c37fa10 SH |
604 | source "arch/arm/mach-berlin/Kconfig" |
605 | ||
1da177e4 LT |
606 | source "arch/arm/mach-clps711x/Kconfig" |
607 | ||
d94f944e AV |
608 | source "arch/arm/mach-cns3xxx/Kconfig" |
609 | ||
95b8f20f RK |
610 | source "arch/arm/mach-davinci/Kconfig" |
611 | ||
df8d742e BS |
612 | source "arch/arm/mach-digicolor/Kconfig" |
613 | ||
95b8f20f RK |
614 | source "arch/arm/mach-dove/Kconfig" |
615 | ||
e7736d47 LB |
616 | source "arch/arm/mach-ep93xx/Kconfig" |
617 | ||
a66c51f9 | 618 | source "arch/arm/mach-exynos/Kconfig" |
a66c51f9 | 619 | |
1da177e4 LT |
620 | source "arch/arm/mach-footbridge/Kconfig" |
621 | ||
59d3a193 PZ |
622 | source "arch/arm/mach-gemini/Kconfig" |
623 | ||
387798b3 RH |
624 | source "arch/arm/mach-highbank/Kconfig" |
625 | ||
389ee0c2 HZ |
626 | source "arch/arm/mach-hisi/Kconfig" |
627 | ||
a66c51f9 AB |
628 | source "arch/arm/mach-imx/Kconfig" |
629 | ||
1da177e4 LT |
630 | source "arch/arm/mach-integrator/Kconfig" |
631 | ||
3f7e5815 LB |
632 | source "arch/arm/mach-iop32x/Kconfig" |
633 | ||
1da177e4 LT |
634 | source "arch/arm/mach-ixp4xx/Kconfig" |
635 | ||
828989ad SS |
636 | source "arch/arm/mach-keystone/Kconfig" |
637 | ||
75bf1bd7 | 638 | source "arch/arm/mach-lpc32xx/Kconfig" |
95b8f20f | 639 | |
a66c51f9 AB |
640 | source "arch/arm/mach-mediatek/Kconfig" |
641 | ||
3b8f5030 CC |
642 | source "arch/arm/mach-meson/Kconfig" |
643 | ||
9fb29c73 ST |
644 | source "arch/arm/mach-milbeaut/Kconfig" |
645 | ||
a66c51f9 | 646 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 647 | |
a66c51f9 | 648 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 649 | |
312b62b6 DP |
650 | source "arch/arm/mach-mstar/Kconfig" |
651 | ||
794d15b2 SS |
652 | source "arch/arm/mach-mv78xx0/Kconfig" |
653 | ||
a66c51f9 | 654 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 655 | |
1d3f33d5 SG |
656 | source "arch/arm/mach-mxs/Kconfig" |
657 | ||
95b8f20f | 658 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 659 | |
7bffa14c BH |
660 | source "arch/arm/mach-npcm/Kconfig" |
661 | ||
9851ca57 DT |
662 | source "arch/arm/mach-nspire/Kconfig" |
663 | ||
d48af15e TL |
664 | source "arch/arm/plat-omap/Kconfig" |
665 | ||
666 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 667 | |
1dbae815 TL |
668 | source "arch/arm/mach-omap2/Kconfig" |
669 | ||
9dd0b194 | 670 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 671 | |
a66c51f9 AB |
672 | source "arch/arm/mach-oxnas/Kconfig" |
673 | ||
95b8f20f RK |
674 | source "arch/arm/mach-pxa/Kconfig" |
675 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 676 | |
8fc1b0f8 KG |
677 | source "arch/arm/mach-qcom/Kconfig" |
678 | ||
78e3dbc1 AF |
679 | source "arch/arm/mach-rda/Kconfig" |
680 | ||
86aeee4d AF |
681 | source "arch/arm/mach-realtek/Kconfig" |
682 | ||
95b8f20f RK |
683 | source "arch/arm/mach-realview/Kconfig" |
684 | ||
d63dc051 HS |
685 | source "arch/arm/mach-rockchip/Kconfig" |
686 | ||
71b9114d | 687 | source "arch/arm/mach-s3c/Kconfig" |
a66c51f9 AB |
688 | |
689 | source "arch/arm/mach-s5pv210/Kconfig" | |
690 | ||
95b8f20f | 691 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 692 | |
a66c51f9 AB |
693 | source "arch/arm/mach-shmobile/Kconfig" |
694 | ||
387798b3 RH |
695 | source "arch/arm/mach-socfpga/Kconfig" |
696 | ||
a7ed099f | 697 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 698 | |
65ebcc11 SK |
699 | source "arch/arm/mach-sti/Kconfig" |
700 | ||
bcb84fb4 AT |
701 | source "arch/arm/mach-stm32/Kconfig" |
702 | ||
3b52634f MR |
703 | source "arch/arm/mach-sunxi/Kconfig" |
704 | ||
c5f80065 EG |
705 | source "arch/arm/mach-tegra/Kconfig" |
706 | ||
ba56a987 MY |
707 | source "arch/arm/mach-uniphier/Kconfig" |
708 | ||
95b8f20f | 709 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
710 | |
711 | source "arch/arm/mach-versatile/Kconfig" | |
712 | ||
ceade897 RK |
713 | source "arch/arm/mach-vexpress/Kconfig" |
714 | ||
6f35f9a9 TP |
715 | source "arch/arm/mach-vt8500/Kconfig" |
716 | ||
9a45eb69 JC |
717 | source "arch/arm/mach-zynq/Kconfig" |
718 | ||
499f1640 | 719 | # ARMv7-M architecture |
499f1640 SA |
720 | config ARCH_LPC18XX |
721 | bool "NXP LPC18xx/LPC43xx" | |
722 | depends on ARM_SINGLE_ARMV7M | |
723 | select ARCH_HAS_RESET_CONTROLLER | |
724 | select ARM_AMBA | |
725 | select CLKSRC_LPC32XX | |
726 | select PINCTRL | |
727 | help | |
728 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
729 | high performance microcontrollers. | |
730 | ||
1847119d | 731 | config ARCH_MPS2 |
17bd274e | 732 | bool "ARM MPS2 platform" |
1847119d VM |
733 | depends on ARM_SINGLE_ARMV7M |
734 | select ARM_AMBA | |
735 | select CLKSRC_MPS2 | |
736 | help | |
737 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
738 | with a range of available cores like Cortex-M3/M4/M7. | |
739 | ||
740 | Please, note that depends which Application Note is used memory map | |
741 | for the platform may vary, so adjustment of RAM base might be needed. | |
742 | ||
1da177e4 LT |
743 | # Definitions to make life easier |
744 | config ARCH_ACORN | |
745 | bool | |
746 | ||
7ae1f7ec LB |
747 | config PLAT_IOP |
748 | bool | |
749 | ||
69b02f6a LB |
750 | config PLAT_ORION |
751 | bool | |
bfe45e0b | 752 | select CLKSRC_MMIO |
b1b3f49c | 753 | select COMMON_CLK |
dc7ad3b3 | 754 | select GENERIC_IRQ_CHIP |
278b45b0 | 755 | select IRQ_DOMAIN |
69b02f6a | 756 | |
abcda1dc TP |
757 | config PLAT_ORION_LEGACY |
758 | bool | |
759 | select PLAT_ORION | |
760 | ||
bd5ce433 EM |
761 | config PLAT_PXA |
762 | bool | |
763 | ||
f4b8b319 RK |
764 | config PLAT_VERSATILE |
765 | bool | |
766 | ||
8636a1f9 | 767 | source "arch/arm/mm/Kconfig" |
1da177e4 | 768 | |
afe4b25e | 769 | config IWMMXT |
d93003e8 SH |
770 | bool "Enable iWMMXt support" |
771 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
772 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
773 | help |
774 | Enable support for iWMMXt context switching at run time if | |
775 | running on a CPU that supports it. | |
776 | ||
3b93e7b0 HC |
777 | if !MMU |
778 | source "arch/arm/Kconfig-nommu" | |
779 | endif | |
780 | ||
3e0a07f8 GC |
781 | config PJ4B_ERRATA_4742 |
782 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
783 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
784 | default y | |
785 | help | |
786 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
787 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
788 | the retiring WFI/WFE instructions and the newly issued subsequent | |
789 | instructions. This sensitivity can result in a CPU hang scenario. | |
790 | Workaround: | |
791 | The software must insert either a Data Synchronization Barrier (DSB) | |
792 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
793 | instruction | |
794 | ||
f0c4b8d6 WD |
795 | config ARM_ERRATA_326103 |
796 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
797 | depends on CPU_V6 | |
798 | help | |
799 | Executing a SWP instruction to read-only memory does not set bit 11 | |
800 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
801 | treat the access as a read, preventing a COW from occurring and | |
802 | causing the faulting task to livelock. | |
803 | ||
9cba3ccc CM |
804 | config ARM_ERRATA_411920 |
805 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 806 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
807 | help |
808 | Invalidation of the Instruction Cache operation can | |
809 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
810 | It does not affect the MPCore. This option enables the ARM Ltd. | |
811 | recommended workaround. | |
812 | ||
7ce236fc CM |
813 | config ARM_ERRATA_430973 |
814 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
815 | depends on CPU_V7 | |
816 | help | |
817 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 818 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
819 | interworking branch is replaced with another code sequence at the |
820 | same virtual address, whether due to self-modifying code or virtual | |
821 | to physical address re-mapping, Cortex-A8 does not recover from the | |
822 | stale interworking branch prediction. This results in Cortex-A8 | |
823 | executing the new code sequence in the incorrect ARM or Thumb state. | |
824 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
825 | and also flushes the branch target cache at every context switch. | |
826 | Note that setting specific bits in the ACTLR register may not be | |
827 | available in non-secure mode. | |
828 | ||
855c551f CM |
829 | config ARM_ERRATA_458693 |
830 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
831 | depends on CPU_V7 | |
62e4d357 | 832 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
833 | help |
834 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
835 | erratum. For very specific sequences of memory operations, it is | |
836 | possible for a hazard condition intended for a cache line to instead | |
837 | be incorrectly associated with a different cache line. This false | |
838 | hazard might then cause a processor deadlock. The workaround enables | |
839 | the L1 caching of the NEON accesses and disables the PLD instruction | |
840 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
841 | register may not be available in non-secure mode. | |
842 | ||
0516e464 CM |
843 | config ARM_ERRATA_460075 |
844 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
845 | depends on CPU_V7 | |
62e4d357 | 846 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
847 | help |
848 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
849 | erratum. Any asynchronous access to the L2 cache may encounter a | |
850 | situation in which recent store transactions to the L2 cache are lost | |
851 | and overwritten with stale memory contents from external memory. The | |
852 | workaround disables the write-allocate mode for the L2 cache via the | |
853 | ACTLR register. Note that setting specific bits in the ACTLR register | |
854 | may not be available in non-secure mode. | |
855 | ||
9f05027c WD |
856 | config ARM_ERRATA_742230 |
857 | bool "ARM errata: DMB operation may be faulty" | |
858 | depends on CPU_V7 && SMP | |
62e4d357 | 859 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
860 | help |
861 | This option enables the workaround for the 742230 Cortex-A9 | |
862 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
863 | between two write operations may not ensure the correct visibility | |
864 | ordering of the two writes. This workaround sets a specific bit in | |
865 | the diagnostic register of the Cortex-A9 which causes the DMB | |
866 | instruction to behave as a DSB, ensuring the correct behaviour of | |
867 | the two writes. | |
868 | ||
a672e99b WD |
869 | config ARM_ERRATA_742231 |
870 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
871 | depends on CPU_V7 && SMP | |
62e4d357 | 872 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
873 | help |
874 | This option enables the workaround for the 742231 Cortex-A9 | |
875 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
876 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
877 | accessing some data located in the same cache line, may get corrupted | |
878 | data due to bad handling of the address hazard when the line gets | |
879 | replaced from one of the CPUs at the same time as another CPU is | |
880 | accessing it. This workaround sets specific bits in the diagnostic | |
881 | register of the Cortex-A9 which reduces the linefill issuing | |
882 | capabilities of the processor. | |
883 | ||
69155794 JM |
884 | config ARM_ERRATA_643719 |
885 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
886 | depends on CPU_V7 && SMP | |
e5a5de44 | 887 | default y |
69155794 JM |
888 | help |
889 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
890 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
891 | register returns zero when it should return one. The workaround | |
892 | corrects this value, ensuring cache maintenance operations which use | |
893 | it behave as intended and avoiding data corruption. | |
894 | ||
cdf357f1 WD |
895 | config ARM_ERRATA_720789 |
896 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 897 | depends on CPU_V7 |
cdf357f1 WD |
898 | help |
899 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
900 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
901 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
902 | As a consequence of this erratum, some TLB entries which should be | |
903 | invalidated are not, resulting in an incoherency in the system page | |
904 | tables. The workaround changes the TLB flushing routines to invalidate | |
905 | entries regardless of the ASID. | |
475d92fc WD |
906 | |
907 | config ARM_ERRATA_743622 | |
908 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
909 | depends on CPU_V7 | |
62e4d357 | 910 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
911 | help |
912 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 913 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
914 | optimisation in the Cortex-A9 Store Buffer may lead to data |
915 | corruption. This workaround sets a specific bit in the diagnostic | |
916 | register of the Cortex-A9 which disables the Store Buffer | |
917 | optimisation, preventing the defect from occurring. This has no | |
918 | visible impact on the overall performance or power consumption of the | |
919 | processor. | |
920 | ||
9a27c27c WD |
921 | config ARM_ERRATA_751472 |
922 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 923 | depends on CPU_V7 |
62e4d357 | 924 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
925 | help |
926 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
927 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
928 | completion of a following broadcasted operation if the second | |
929 | operation is received by a CPU before the ICIALLUIS has completed, | |
930 | potentially leading to corrupted entries in the cache or TLB. | |
931 | ||
fcbdc5fe WD |
932 | config ARM_ERRATA_754322 |
933 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
934 | depends on CPU_V7 | |
935 | help | |
936 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
937 | r3p*) erratum. A speculative memory access may cause a page table walk | |
938 | which starts prior to an ASID switch but completes afterwards. This | |
939 | can populate the micro-TLB with a stale entry which may be hit with | |
940 | the new ASID. This workaround places two dsb instructions in the mm | |
941 | switching code so that no page table walks can cross the ASID switch. | |
942 | ||
5dab26af WD |
943 | config ARM_ERRATA_754327 |
944 | bool "ARM errata: no automatic Store Buffer drain" | |
945 | depends on CPU_V7 && SMP | |
946 | help | |
947 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
948 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
949 | mechanism and therefore a livelock may occur if an external agent | |
950 | continuously polls a memory location waiting to observe an update. | |
951 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
952 | written polling loops from denying visibility of updates to memory. | |
953 | ||
145e10e1 CM |
954 | config ARM_ERRATA_364296 |
955 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 956 | depends on CPU_V6 |
145e10e1 CM |
957 | help |
958 | This options enables the workaround for the 364296 ARM1136 | |
959 | r0p2 erratum (possible cache data corruption with | |
960 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
961 | the auxiliary control register and the FI bit in the control | |
962 | register, thus disabling hit-under-miss without putting the | |
963 | processor into full low interrupt latency mode. ARM11MPCore | |
964 | is not affected. | |
965 | ||
f630c1bd WD |
966 | config ARM_ERRATA_764369 |
967 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
968 | depends on CPU_V7 && SMP | |
969 | help | |
970 | This option enables the workaround for erratum 764369 | |
971 | affecting Cortex-A9 MPCore with two or more processors (all | |
972 | current revisions). Under certain timing circumstances, a data | |
973 | cache line maintenance operation by MVA targeting an Inner | |
974 | Shareable memory region may fail to proceed up to either the | |
975 | Point of Coherency or to the Point of Unification of the | |
976 | system. This workaround adds a DSB instruction before the | |
977 | relevant cache maintenance functions and sets a specific bit | |
978 | in the diagnostic control register of the SCU. | |
979 | ||
7253b85c SH |
980 | config ARM_ERRATA_775420 |
981 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
982 | depends on CPU_V7 | |
983 | help | |
984 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
cb73737e | 985 | r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance |
7253b85c SH |
986 | operation aborts with MMU exception, it might cause the processor |
987 | to deadlock. This workaround puts DSB before executing ISB if | |
988 | an abort may occur on cache maintenance. | |
989 | ||
93dc6887 CM |
990 | config ARM_ERRATA_798181 |
991 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
992 | depends on CPU_V7 && SMP | |
993 | help | |
994 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
995 | adequately shooting down all use of the old entries. This | |
996 | option enables the Linux kernel workaround for this erratum | |
997 | which sends an IPI to the CPUs that are running the same ASID | |
998 | as the one being invalidated. | |
999 | ||
84b6504f WD |
1000 | config ARM_ERRATA_773022 |
1001 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1002 | depends on CPU_V7 | |
1003 | help | |
1004 | This option enables the workaround for the 773022 Cortex-A15 | |
1005 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1006 | loop buffer may deliver incorrect instructions. This | |
1007 | workaround disables the loop buffer to avoid the erratum. | |
1008 | ||
62c0f4a5 DA |
1009 | config ARM_ERRATA_818325_852422 |
1010 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1011 | depends on CPU_V7 | |
1012 | help | |
1013 | This option enables the workaround for: | |
1014 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1015 | instruction might deadlock. Fixed in r0p1. | |
1016 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1017 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1018 | any Cortex-A12 cores yet. | |
1019 | This workaround for all both errata involves setting bit[12] of the | |
1020 | Feature Register. This bit disables an optimisation applied to a | |
1021 | sequence of 2 instructions that use opposing condition codes. | |
1022 | ||
416bcf21 DA |
1023 | config ARM_ERRATA_821420 |
1024 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1025 | depends on CPU_V7 | |
1026 | help | |
1027 | This option enables the workaround for the 821420 Cortex-A12 | |
1028 | (all revs) erratum. In very rare timing conditions, a sequence | |
1029 | of VMOV to Core registers instructions, for which the second | |
1030 | one is in the shadow of a branch or abort, can lead to a | |
1031 | deadlock when the VMOV instructions are issued out-of-order. | |
1032 | ||
9f6f9354 DA |
1033 | config ARM_ERRATA_825619 |
1034 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1035 | depends on CPU_V7 | |
1036 | help | |
1037 | This option enables the workaround for the 825619 Cortex-A12 | |
1038 | (all revs) erratum. Within rare timing constraints, executing a | |
1039 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1040 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1041 | ||
304009a1 DA |
1042 | config ARM_ERRATA_857271 |
1043 | bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" | |
1044 | depends on CPU_V7 | |
1045 | help | |
1046 | This option enables the workaround for the 857271 Cortex-A12 | |
1047 | (all revs) erratum. Under very rare timing conditions, the CPU might | |
1048 | hang. The workaround is expected to have a < 1% performance impact. | |
1049 | ||
9f6f9354 DA |
1050 | config ARM_ERRATA_852421 |
1051 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1052 | depends on CPU_V7 | |
1053 | help | |
1054 | This option enables the workaround for the 852421 Cortex-A17 | |
1055 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1056 | execution of a DMB ST instruction might fail to properly order | |
1057 | stores from GroupA and stores from GroupB. | |
1058 | ||
62c0f4a5 DA |
1059 | config ARM_ERRATA_852423 |
1060 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1061 | depends on CPU_V7 | |
1062 | help | |
1063 | This option enables the workaround for: | |
1064 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1065 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1066 | any Cortex-A17 cores yet. | |
1067 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1068 | config option from the A12 erratum due to the way errata are checked | |
1069 | for and handled. | |
1070 | ||
304009a1 DA |
1071 | config ARM_ERRATA_857272 |
1072 | bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" | |
1073 | depends on CPU_V7 | |
1074 | help | |
1075 | This option enables the workaround for the 857272 Cortex-A17 erratum. | |
1076 | This erratum is not known to be fixed in any A17 revision. | |
1077 | This is identical to Cortex-A12 erratum 857271. It is a separate | |
1078 | config option from the A12 erratum due to the way errata are checked | |
1079 | for and handled. | |
1080 | ||
1da177e4 LT |
1081 | endmenu |
1082 | ||
1083 | source "arch/arm/common/Kconfig" | |
1084 | ||
1da177e4 LT |
1085 | menu "Bus support" |
1086 | ||
1da177e4 LT |
1087 | config ISA |
1088 | bool | |
1da177e4 LT |
1089 | help |
1090 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1091 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1092 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1093 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1094 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1095 | ||
065909b9 | 1096 | # Select ISA DMA controller support |
1da177e4 LT |
1097 | config ISA_DMA |
1098 | bool | |
065909b9 | 1099 | select ISA_DMA_API |
1da177e4 | 1100 | |
065909b9 | 1101 | # Select ISA DMA interface |
5cae841b AV |
1102 | config ISA_DMA_API |
1103 | bool | |
5cae841b | 1104 | |
b080ac8a MRJ |
1105 | config PCI_NANOENGINE |
1106 | bool "BSE nanoEngine PCI support" | |
1107 | depends on SA1100_NANOENGINE | |
1108 | help | |
1109 | Enable PCI on the BSE nanoEngine board. | |
1110 | ||
779eb41c BG |
1111 | config ARM_ERRATA_814220 |
1112 | bool "ARM errata: Cache maintenance by set/way operations can execute out of order" | |
1113 | depends on CPU_V7 | |
1114 | help | |
1115 | The v7 ARM states that all cache and branch predictor maintenance | |
1116 | operations that do not specify an address execute, relative to | |
1117 | each other, in program order. | |
1118 | However, because of this erratum, an L2 set/way cache maintenance | |
1119 | operation can overtake an L1 set/way cache maintenance operation. | |
1120 | This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, | |
1121 | r0p4, r0p5. | |
1122 | ||
1da177e4 LT |
1123 | endmenu |
1124 | ||
1125 | menu "Kernel Features" | |
1126 | ||
3b55658a DM |
1127 | config HAVE_SMP |
1128 | bool | |
1129 | help | |
1130 | This option should be selected by machines which have an SMP- | |
1131 | capable CPU. | |
1132 | ||
1133 | The only effect of this option is to make the SMP-related | |
1134 | options available to the user for configuration. | |
1135 | ||
1da177e4 | 1136 | config SMP |
bb2d8130 | 1137 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1138 | depends on CPU_V6K || CPU_V7 |
3b55658a | 1139 | depends on HAVE_SMP |
801bb21c | 1140 | depends on MMU || ARM_MPU |
0361748f | 1141 | select IRQ_WORK |
1da177e4 LT |
1142 | help |
1143 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1144 | a system with only one CPU, say N. If you have a system with more |
1145 | than one CPU, say Y. | |
1da177e4 | 1146 | |
4a474157 | 1147 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1148 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1149 | you say Y here, the kernel will run on many, but not all, |
1150 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1151 | will run faster if you say N here. | |
1da177e4 | 1152 | |
cb1aaebe | 1153 | See also <file:Documentation/x86/i386/IO-APIC.rst>, |
4f4cfa6c | 1154 | <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at |
50a23e6e | 1155 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1156 | |
1157 | If you don't know what to do here, say N. | |
1158 | ||
f00ec48f | 1159 | config SMP_ON_UP |
5744ff43 | 1160 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1161 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1162 | default y |
1163 | help | |
1164 | SMP kernels contain instructions which fail on non-SMP processors. | |
1165 | Enabling this option allows the kernel to modify itself to make | |
1166 | these instructions safe. Disabling it allows about 1K of space | |
1167 | savings. | |
1168 | ||
1169 | If you don't know what to do here, say Y. | |
1170 | ||
c9018aab VG |
1171 | config ARM_CPU_TOPOLOGY |
1172 | bool "Support cpu topology definition" | |
1173 | depends on SMP && CPU_V7 | |
1174 | default y | |
1175 | help | |
1176 | Support ARM cpu topology definition. The MPIDR register defines | |
1177 | affinity between processors which is then used to describe the cpu | |
1178 | topology of an ARM System. | |
1179 | ||
1180 | config SCHED_MC | |
1181 | bool "Multi-core scheduler support" | |
1182 | depends on ARM_CPU_TOPOLOGY | |
1183 | help | |
1184 | Multi-core scheduler support improves the CPU scheduler's decision | |
1185 | making when dealing with multi-core CPU chips at a cost of slightly | |
1186 | increased overhead in some places. If unsure say N here. | |
1187 | ||
1188 | config SCHED_SMT | |
1189 | bool "SMT scheduler support" | |
1190 | depends on ARM_CPU_TOPOLOGY | |
1191 | help | |
1192 | Improves the CPU scheduler's decision making when dealing with | |
1193 | MultiThreading at a cost of slightly increased overhead in some | |
1194 | places. If unsure say N here. | |
1195 | ||
a8cbcd92 RK |
1196 | config HAVE_ARM_SCU |
1197 | bool | |
a8cbcd92 | 1198 | help |
8f433ec4 | 1199 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 1200 | |
8a4da6e3 | 1201 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1202 | bool "Architected timer support" |
1203 | depends on CPU_V7 | |
8a4da6e3 | 1204 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1205 | help |
1206 | This option enables support for the ARM architected timer | |
1207 | ||
f32f4ce2 RK |
1208 | config HAVE_ARM_TWD |
1209 | bool | |
f32f4ce2 RK |
1210 | help |
1211 | This options enables support for the ARM timer and watchdog unit | |
1212 | ||
e8db288e NP |
1213 | config MCPM |
1214 | bool "Multi-Cluster Power Management" | |
1215 | depends on CPU_V7 && SMP | |
1216 | help | |
1217 | This option provides the common power management infrastructure | |
1218 | for (multi-)cluster based systems, such as big.LITTLE based | |
1219 | systems. | |
1220 | ||
ebf4a5c5 HZ |
1221 | config MCPM_QUAD_CLUSTER |
1222 | bool | |
1223 | depends on MCPM | |
1224 | help | |
1225 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1226 | to 2 clusters by default. | |
1227 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1228 | option to allow the additional clusters to be managed. | |
1229 | ||
1c33be57 NP |
1230 | config BIG_LITTLE |
1231 | bool "big.LITTLE support (Experimental)" | |
1232 | depends on CPU_V7 && SMP | |
1233 | select MCPM | |
1234 | help | |
1235 | This option enables support selections for the big.LITTLE | |
1236 | system architecture. | |
1237 | ||
1238 | config BL_SWITCHER | |
1239 | bool "big.LITTLE switcher support" | |
6c044fec | 1240 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1241 | select CPU_PM |
1c33be57 NP |
1242 | help |
1243 | The big.LITTLE "switcher" provides the core functionality to | |
1244 | transparently handle transition between a cluster of A15's | |
1245 | and a cluster of A7's in a big.LITTLE system. | |
1246 | ||
b22537c6 NP |
1247 | config BL_SWITCHER_DUMMY_IF |
1248 | tristate "Simple big.LITTLE switcher user interface" | |
1249 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1250 | help | |
1251 | This is a simple and dummy char dev interface to control | |
1252 | the big.LITTLE switcher core code. It is meant for | |
1253 | debugging purposes only. | |
1254 | ||
8d5796d2 LB |
1255 | choice |
1256 | prompt "Memory split" | |
006fa259 | 1257 | depends on MMU |
8d5796d2 LB |
1258 | default VMSPLIT_3G |
1259 | help | |
1260 | Select the desired split between kernel and user memory. | |
1261 | ||
1262 | If you are not absolutely sure what you are doing, leave this | |
1263 | option alone! | |
1264 | ||
1265 | config VMSPLIT_3G | |
1266 | bool "3G/1G user/kernel split" | |
63ce446c | 1267 | config VMSPLIT_3G_OPT |
bbeedfda | 1268 | depends on !ARM_LPAE |
63ce446c | 1269 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1270 | config VMSPLIT_2G |
1271 | bool "2G/2G user/kernel split" | |
1272 | config VMSPLIT_1G | |
1273 | bool "1G/3G user/kernel split" | |
1274 | endchoice | |
1275 | ||
1276 | config PAGE_OFFSET | |
1277 | hex | |
006fa259 | 1278 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1279 | default 0x40000000 if VMSPLIT_1G |
1280 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1281 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1282 | default 0xC0000000 |
1283 | ||
c12366ba LW |
1284 | config KASAN_SHADOW_OFFSET |
1285 | hex | |
1286 | depends on KASAN | |
1287 | default 0x1f000000 if PAGE_OFFSET=0x40000000 | |
1288 | default 0x5f000000 if PAGE_OFFSET=0x80000000 | |
1289 | default 0x9f000000 if PAGE_OFFSET=0xC0000000 | |
1290 | default 0x8f000000 if PAGE_OFFSET=0xB0000000 | |
1291 | default 0xffffffff | |
1292 | ||
1da177e4 LT |
1293 | config NR_CPUS |
1294 | int "Maximum number of CPUs (2-32)" | |
1295 | range 2 32 | |
1296 | depends on SMP | |
1297 | default "4" | |
1298 | ||
a054a811 | 1299 | config HOTPLUG_CPU |
00b7dede | 1300 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1301 | depends on SMP |
1b5ba350 | 1302 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1303 | help |
1304 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1305 | can be controlled through /sys/devices/system/cpu. | |
1306 | ||
2bdd424f WD |
1307 | config ARM_PSCI |
1308 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1309 | depends on HAVE_ARM_SMCCC |
be120397 | 1310 | select ARM_PSCI_FW |
2bdd424f WD |
1311 | help |
1312 | Say Y here if you want Linux to communicate with system firmware | |
1313 | implementing the PSCI specification for CPU-centric power | |
1314 | management operations described in ARM document number ARM DEN | |
1315 | 0022A ("Power State Coordination Interface System Software on | |
1316 | ARM processors"). | |
1317 | ||
2a6ad871 MR |
1318 | # The GPIO number here must be sorted by descending number. In case of |
1319 | # a multiplatform kernel, we just want the highest value required by the | |
1320 | # selected platforms. | |
44986ab0 PDSN |
1321 | config ARCH_NR_GPIO |
1322 | int | |
139358be | 1323 | default 2048 if ARCH_SOCFPGA |
d9be9ceb | 1324 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
a3ee4fea | 1325 | ARCH_ZYNQ || ARCH_ASPEED |
aa42587a TF |
1326 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1327 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1328 | default 416 if ARCH_SUNXI |
06b851e5 | 1329 | default 392 if ARCH_U8500 |
01bb914c | 1330 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1331 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1332 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1333 | default 0 |
1334 | help | |
1335 | Maximum number of GPIOs in the system. | |
1336 | ||
1337 | If unsure, leave the default value. | |
1338 | ||
c9218b16 | 1339 | config HZ_FIXED |
f8065813 | 1340 | int |
1164f672 | 1341 | default 128 if SOC_AT91RM9200 |
47d84682 | 1342 | default 0 |
c9218b16 RK |
1343 | |
1344 | choice | |
47d84682 | 1345 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1346 | prompt "Timer frequency" |
1347 | ||
1348 | config HZ_100 | |
1349 | bool "100 Hz" | |
1350 | ||
1351 | config HZ_200 | |
1352 | bool "200 Hz" | |
1353 | ||
1354 | config HZ_250 | |
1355 | bool "250 Hz" | |
1356 | ||
1357 | config HZ_300 | |
1358 | bool "300 Hz" | |
1359 | ||
1360 | config HZ_500 | |
1361 | bool "500 Hz" | |
1362 | ||
1363 | config HZ_1000 | |
1364 | bool "1000 Hz" | |
1365 | ||
1366 | endchoice | |
1367 | ||
1368 | config HZ | |
1369 | int | |
47d84682 | 1370 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1371 | default 100 if HZ_100 |
1372 | default 200 if HZ_200 | |
1373 | default 250 if HZ_250 | |
1374 | default 300 if HZ_300 | |
1375 | default 500 if HZ_500 | |
1376 | default 1000 | |
1377 | ||
1378 | config SCHED_HRTICK | |
1379 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1380 | |
16c79651 | 1381 | config THUMB2_KERNEL |
bc7dea00 | 1382 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1383 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1384 | default y if CPU_THUMBONLY |
89bace65 | 1385 | select ARM_UNWIND |
16c79651 CM |
1386 | help |
1387 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1388 | Thumb-2 mode. |
16c79651 CM |
1389 | |
1390 | If unsure, say N. | |
1391 | ||
42f25bdd NP |
1392 | config ARM_PATCH_IDIV |
1393 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1394 | depends on CPU_32v7 && !XIP_KERNEL | |
1395 | default y | |
1396 | help | |
1397 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1398 | __aeabi_uidiv() when it needs to perform division on signed | |
1399 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1400 | and udiv instructions that can be used to implement those | |
1401 | functions. | |
1402 | ||
1403 | Enabling this option allows the kernel to modify itself to | |
1404 | replace the first two instructions of these library functions | |
1405 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1406 | it is running on supports them. Typically this will be faster | |
1407 | and less power intensive than running the original library | |
1408 | code to do integer division. | |
1409 | ||
704bdda0 | 1410 | config AEABI |
a05b9608 ND |
1411 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ |
1412 | !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG | |
1413 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG | |
704bdda0 NP |
1414 | help |
1415 | This option allows for the kernel to be compiled using the latest | |
1416 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1417 | space environment that is also compiled with EABI. | |
1418 | ||
1419 | Since there are major incompatibilities between the legacy ABI and | |
1420 | EABI, especially with regard to structure member alignment, this | |
1421 | option also changes the kernel syscall calling convention to | |
1422 | disambiguate both ABIs and allow for backward compatibility support | |
1423 | (selected with CONFIG_OABI_COMPAT). | |
1424 | ||
1425 | To use this you need GCC version 4.0.0 or later. | |
1426 | ||
6c90c872 | 1427 | config OABI_COMPAT |
a73a3ff1 | 1428 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1429 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1430 | help |
1431 | This option preserves the old syscall interface along with the | |
1432 | new (ARM EABI) one. It also provides a compatibility layer to | |
1433 | intercept syscalls that have structure arguments which layout | |
1434 | in memory differs between the legacy ABI and the new ARM EABI | |
1435 | (only for non "thumb" binaries). This option adds a tiny | |
1436 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1437 | |
1438 | The seccomp filter system will not be available when this is | |
1439 | selected, since there is no way yet to sensibly distinguish | |
1440 | between calling conventions during filtering. | |
1441 | ||
6c90c872 NP |
1442 | If you know you'll be using only pure EABI user space then you |
1443 | can say N here. If this option is not selected and you attempt | |
1444 | to execute a legacy ABI binary then the result will be | |
1445 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1446 | at all). If in doubt say N. |
6c90c872 | 1447 | |
fb597f2a GF |
1448 | config ARCH_SELECT_MEMORY_MODEL |
1449 | bool | |
1450 | ||
1451 | config ARCH_FLATMEM_ENABLE | |
05944d74 RK |
1452 | bool |
1453 | ||
05944d74 RK |
1454 | config ARCH_SPARSEMEM_ENABLE |
1455 | bool | |
fb597f2a | 1456 | select SPARSEMEM_STATIC if SPARSEMEM |
07a2f737 | 1457 | |
053a96ca | 1458 | config HIGHMEM |
e8db89a2 RK |
1459 | bool "High Memory Support" |
1460 | depends on MMU | |
2a15ba82 | 1461 | select KMAP_LOCAL |
053a96ca NP |
1462 | help |
1463 | The address space of ARM processors is only 4 Gigabytes large | |
1464 | and it has to accommodate user address space, kernel address | |
1465 | space as well as some memory mapped IO. That means that, if you | |
1466 | have a large amount of physical memory and/or IO, not all of the | |
1467 | memory can be "permanently mapped" by the kernel. The physical | |
1468 | memory that is not permanently mapped is called "high memory". | |
1469 | ||
1470 | Depending on the selected kernel/user memory split, minimum | |
1471 | vmalloc space and actual amount of RAM, you may not need this | |
1472 | option which should result in a slightly faster kernel. | |
1473 | ||
1474 | If unsure, say n. | |
1475 | ||
65cec8e3 | 1476 | config HIGHPTE |
9a431bd5 | 1477 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1478 | depends on HIGHMEM |
9a431bd5 | 1479 | default y |
b4d103d1 RK |
1480 | help |
1481 | The VM uses one page of physical memory for each page table. | |
1482 | For systems with a lot of processes, this can use a lot of | |
1483 | precious low memory, eventually leading to low memory being | |
1484 | consumed by page tables. Setting this option will allow | |
1485 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1486 | |
a5e090ac RK |
1487 | config CPU_SW_DOMAIN_PAN |
1488 | bool "Enable use of CPU domains to implement privileged no-access" | |
1489 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1490 | default y |
1491 | help | |
a5e090ac RK |
1492 | Increase kernel security by ensuring that normal kernel accesses |
1493 | are unable to access userspace addresses. This can help prevent | |
1494 | use-after-free bugs becoming an exploitable privilege escalation | |
1495 | by ensuring that magic values (such as LIST_POISON) will always | |
1496 | fault when dereferenced. | |
1497 | ||
1498 | CPUs with low-vector mappings use a best-efforts implementation. | |
1499 | Their lower 1MB needs to remain accessible for the vectors, but | |
1500 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1501 | |
1b8873a0 | 1502 | config HW_PERF_EVENTS |
fa8ad788 MR |
1503 | def_bool y |
1504 | depends on ARM_PMU | |
1b8873a0 | 1505 | |
1355e2a6 CM |
1506 | config SYS_SUPPORTS_HUGETLBFS |
1507 | def_bool y | |
1508 | depends on ARM_LPAE | |
1509 | ||
8d962507 CM |
1510 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1511 | def_bool y | |
1512 | depends on ARM_LPAE | |
1513 | ||
4bfab203 SC |
1514 | config ARCH_WANT_GENERAL_HUGETLB |
1515 | def_bool y | |
1516 | ||
7d485f64 AB |
1517 | config ARM_MODULE_PLTS |
1518 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1519 | depends on MODULES | |
e7229f7d | 1520 | default y |
7d485f64 AB |
1521 | help |
1522 | Allocate PLTs when loading modules so that jumps and calls whose | |
1523 | targets are too far away for their relative offsets to be encoded | |
1524 | in the instructions themselves can be bounced via veneers in the | |
1525 | module's PLT. This allows modules to be allocated in the generic | |
1526 | vmalloc area after the dedicated module memory area has been | |
1527 | exhausted. The modules will use slightly more memory, but after | |
1528 | rounding up to page size, the actual memory footprint is usually | |
1529 | the same. | |
1530 | ||
e7229f7d AR |
1531 | Disabling this is usually safe for small single-platform |
1532 | configurations. If unsure, say y. | |
7d485f64 | 1533 | |
c1b2d970 | 1534 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1535 | int "Maximum zone order" |
898f08e1 | 1536 | default "12" if SOC_AM33XX |
cc611137 | 1537 | default "9" if SA1111 |
c1b2d970 MD |
1538 | default "11" |
1539 | help | |
1540 | The kernel memory allocator divides physically contiguous memory | |
1541 | blocks into "zones", where each zone is a power of two number of | |
1542 | pages. This option selects the largest power of two that the kernel | |
1543 | keeps in the memory allocator. If you need to allocate very large | |
1544 | blocks of physically contiguous memory, then you may need to | |
1545 | increase this value. | |
1546 | ||
1547 | This config option is actually maximum order plus one. For example, | |
1548 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1549 | ||
1da177e4 | 1550 | config ALIGNMENT_TRAP |
3e3f354b | 1551 | def_bool CPU_CP15_MMU |
e119bfff | 1552 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1553 | help |
84eb8d06 | 1554 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1555 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1556 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1557 | fetch/store instructions will be emulated in software if you say | |
1558 | here, which has a severe performance impact. This is necessary for | |
1559 | correct operation of some network protocols. With an IP-only | |
1560 | configuration it is safe to say N, otherwise say Y. | |
1561 | ||
39ec58f3 | 1562 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1563 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1564 | depends on MMU | |
39ec58f3 LB |
1565 | default y if CPU_FEROCEON |
1566 | help | |
1567 | Implement faster copy_to_user and clear_user methods for CPU | |
1568 | cores where a 8-word STM instruction give significantly higher | |
1569 | memory write throughput than a sequence of individual 32bit stores. | |
1570 | ||
1571 | A possible side effect is a slight increase in scheduling latency | |
1572 | between threads sharing the same address space if they invoke | |
1573 | such copy operations with large buffers. | |
1574 | ||
1575 | However, if the CPU data cache is using a write-allocate mode, | |
1576 | this option is unlikely to provide any performance gain. | |
1577 | ||
02c2433b SS |
1578 | config PARAVIRT |
1579 | bool "Enable paravirtualization code" | |
1580 | help | |
1581 | This changes the kernel so it can modify itself when it is run | |
1582 | under a hypervisor, potentially improving performance significantly | |
1583 | over full virtualization. | |
1584 | ||
1585 | config PARAVIRT_TIME_ACCOUNTING | |
1586 | bool "Paravirtual steal time accounting" | |
1587 | select PARAVIRT | |
02c2433b SS |
1588 | help |
1589 | Select this option to enable fine granularity task steal time | |
1590 | accounting. Time spent executing other tasks in parallel with | |
1591 | the current vCPU is discounted from the vCPU power. To account for | |
1592 | that, there can be a small performance impact. | |
1593 | ||
1594 | If in doubt, say N here. | |
1595 | ||
eff8d644 SS |
1596 | config XEN_DOM0 |
1597 | def_bool y | |
1598 | depends on XEN | |
1599 | ||
1600 | config XEN | |
c2ba1f7d | 1601 | bool "Xen guest support on ARM" |
85323a99 | 1602 | depends on ARM && AEABI && OF |
f880b67d | 1603 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1604 | depends on !GENERIC_ATOMIC64 |
7693decc | 1605 | depends on MMU |
51aaf81f | 1606 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1607 | select ARM_PSCI |
f21254cd | 1608 | select SWIOTLB |
83862ccf | 1609 | select SWIOTLB_XEN |
02c2433b | 1610 | select PARAVIRT |
eff8d644 SS |
1611 | help |
1612 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1613 | ||
189af465 AB |
1614 | config STACKPROTECTOR_PER_TASK |
1615 | bool "Use a unique stack canary value for each task" | |
1616 | depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA | |
1617 | select GCC_PLUGIN_ARM_SSP_PER_TASK | |
1618 | default y | |
1619 | help | |
1620 | Due to the fact that GCC uses an ordinary symbol reference from | |
1621 | which to load the value of the stack canary, this value can only | |
1622 | change at reboot time on SMP systems, and all tasks running in the | |
1623 | kernel's address space are forced to use the same canary value for | |
1624 | the entire duration that the system is up. | |
1625 | ||
1626 | Enable this option to switch to a different method that uses a | |
1627 | different canary value for each task. | |
1628 | ||
1da177e4 LT |
1629 | endmenu |
1630 | ||
1631 | menu "Boot options" | |
1632 | ||
9eb8f674 GL |
1633 | config USE_OF |
1634 | bool "Flattened Device Tree support" | |
b1b3f49c | 1635 | select IRQ_DOMAIN |
9eb8f674 | 1636 | select OF |
9eb8f674 GL |
1637 | help |
1638 | Include support for flattened device tree machine descriptions. | |
1639 | ||
bd51e2f5 NP |
1640 | config ATAGS |
1641 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1642 | default y | |
1643 | help | |
1644 | This is the traditional way of passing data to the kernel at boot | |
1645 | time. If you are solely relying on the flattened device tree (or | |
1646 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1647 | to remove ATAGS support from your kernel binary. If unsure, | |
1648 | leave this to y. | |
1649 | ||
1650 | config DEPRECATED_PARAM_STRUCT | |
1651 | bool "Provide old way to pass kernel parameters" | |
1652 | depends on ATAGS | |
1653 | help | |
1654 | This was deprecated in 2001 and announced to live on for 5 years. | |
1655 | Some old boot loaders still use this way. | |
1656 | ||
1da177e4 LT |
1657 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1658 | # TEXT and BSS so we preserve their values in the config files. | |
1659 | config ZBOOT_ROM_TEXT | |
1660 | hex "Compressed ROM boot loader base address" | |
39c3e304 | 1661 | default 0x0 |
1da177e4 LT |
1662 | help |
1663 | The physical address at which the ROM-able zImage is to be | |
1664 | placed in the target. Platforms which normally make use of | |
1665 | ROM-able zImage formats normally set this to a suitable | |
1666 | value in their defconfig file. | |
1667 | ||
1668 | If ZBOOT_ROM is not enabled, this has no effect. | |
1669 | ||
1670 | config ZBOOT_ROM_BSS | |
1671 | hex "Compressed ROM boot loader BSS address" | |
39c3e304 | 1672 | default 0x0 |
1da177e4 | 1673 | help |
f8c440b2 DF |
1674 | The base address of an area of read/write memory in the target |
1675 | for the ROM-able zImage which must be available while the | |
1676 | decompressor is running. It must be large enough to hold the | |
1677 | entire decompressed kernel plus an additional 128 KiB. | |
1678 | Platforms which normally make use of ROM-able zImage formats | |
1679 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1680 | |
1681 | If ZBOOT_ROM is not enabled, this has no effect. | |
1682 | ||
1683 | config ZBOOT_ROM | |
1684 | bool "Compressed boot loader in ROM/flash" | |
1685 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1686 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1687 | help |
1688 | Say Y here if you intend to execute your compressed kernel image | |
1689 | (zImage) directly from ROM or flash. If unsure, say N. | |
1690 | ||
e2a6a3aa JB |
1691 | config ARM_APPENDED_DTB |
1692 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1693 | depends on OF |
e2a6a3aa JB |
1694 | help |
1695 | With this option, the boot code will look for a device tree binary | |
1696 | (DTB) appended to zImage | |
1697 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1698 | ||
1699 | This is meant as a backward compatibility convenience for those | |
1700 | systems with a bootloader that can't be upgraded to accommodate | |
1701 | the documented boot protocol using a device tree. | |
1702 | ||
1703 | Beware that there is very little in terms of protection against | |
1704 | this option being confused by leftover garbage in memory that might | |
1705 | look like a DTB header after a reboot if no actual DTB is appended | |
1706 | to zImage. Do not leave this option active in a production kernel | |
1707 | if you don't intend to always append a DTB. Proper passing of the | |
1708 | location into r2 of a bootloader provided DTB is always preferable | |
1709 | to this option. | |
1710 | ||
b90b9a38 NP |
1711 | config ARM_ATAG_DTB_COMPAT |
1712 | bool "Supplement the appended DTB with traditional ATAG information" | |
1713 | depends on ARM_APPENDED_DTB | |
1714 | help | |
1715 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1716 | they provide ATAGs with memory configuration, the ramdisk address, | |
1717 | the kernel cmdline string, etc. Such information is dynamically | |
1718 | provided by the bootloader and can't always be stored in a static | |
1719 | DTB. To allow a device tree enabled kernel to be used with such | |
1720 | bootloaders, this option allows zImage to extract the information | |
1721 | from the ATAG list and store it at run time into the appended DTB. | |
1722 | ||
d0f34a11 GR |
1723 | choice |
1724 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1725 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1726 | ||
1727 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1728 | bool "Use bootloader kernel arguments if available" | |
1729 | help | |
1730 | Uses the command-line options passed by the boot loader instead of | |
1731 | the device tree bootargs property. If the boot loader doesn't provide | |
1732 | any, the device tree bootargs property will be used. | |
1733 | ||
1734 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1735 | bool "Extend with bootloader kernel arguments" | |
1736 | help | |
1737 | The command-line arguments provided by the boot loader will be | |
1738 | appended to the the device tree bootargs property. | |
1739 | ||
1740 | endchoice | |
1741 | ||
1da177e4 LT |
1742 | config CMDLINE |
1743 | string "Default kernel command string" | |
1744 | default "" | |
1745 | help | |
3e3f354b | 1746 | On some architectures (e.g. CATS), there is currently no way |
1da177e4 LT |
1747 | for the boot loader to pass arguments to the kernel. For these |
1748 | architectures, you should supply some command-line options at build | |
1749 | time by entering them here. As a minimum, you should specify the | |
1750 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1751 | ||
4394c124 VB |
1752 | choice |
1753 | prompt "Kernel command line type" if CMDLINE != "" | |
1754 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1755 | depends on ATAGS |
4394c124 VB |
1756 | |
1757 | config CMDLINE_FROM_BOOTLOADER | |
1758 | bool "Use bootloader kernel arguments if available" | |
1759 | help | |
1760 | Uses the command-line options passed by the boot loader. If | |
1761 | the boot loader doesn't provide any, the default kernel command | |
1762 | string provided in CMDLINE will be used. | |
1763 | ||
1764 | config CMDLINE_EXTEND | |
1765 | bool "Extend bootloader kernel arguments" | |
1766 | help | |
1767 | The command-line arguments provided by the boot loader will be | |
1768 | appended to the default kernel command string. | |
1769 | ||
92d2040d AH |
1770 | config CMDLINE_FORCE |
1771 | bool "Always use the default kernel command string" | |
92d2040d AH |
1772 | help |
1773 | Always use the default kernel command string, even if the boot | |
1774 | loader passes other arguments to the kernel. | |
1775 | This is useful if you cannot or don't want to change the | |
1776 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1777 | endchoice |
92d2040d | 1778 | |
1da177e4 LT |
1779 | config XIP_KERNEL |
1780 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1781 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1782 | help |
1783 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1784 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1785 | space since the text section of the kernel is not loaded from flash | |
1786 | to RAM. Read-write sections, such as the data section and stack, | |
1787 | are still copied to RAM. The XIP kernel is not compressed since | |
1788 | it has to run directly from flash, so it will take more space to | |
1789 | store it. The flash address used to link the kernel object files, | |
1790 | and for storing it, is configuration dependent. Therefore, if you | |
1791 | say Y here, you must know the proper physical address where to | |
1792 | store the kernel image depending on your own flash memory usage. | |
1793 | ||
1794 | Also note that the make target becomes "make xipImage" rather than | |
1795 | "make zImage" or "make Image". The final kernel binary to put in | |
1796 | ROM memory will be arch/arm/boot/xipImage. | |
1797 | ||
1798 | If unsure, say N. | |
1799 | ||
1800 | config XIP_PHYS_ADDR | |
1801 | hex "XIP Kernel Physical Location" | |
1802 | depends on XIP_KERNEL | |
1803 | default "0x00080000" | |
1804 | help | |
1805 | This is the physical address in your flash memory the kernel will | |
1806 | be linked for and stored to. This address is dependent on your | |
1807 | own flash usage. | |
1808 | ||
ca8b5d97 NP |
1809 | config XIP_DEFLATED_DATA |
1810 | bool "Store kernel .data section compressed in ROM" | |
1811 | depends on XIP_KERNEL | |
1812 | select ZLIB_INFLATE | |
1813 | help | |
1814 | Before the kernel is actually executed, its .data section has to be | |
1815 | copied to RAM from ROM. This option allows for storing that data | |
1816 | in compressed form and decompressed to RAM rather than merely being | |
1817 | copied, saving some precious ROM space. A possible drawback is a | |
1818 | slightly longer boot delay. | |
1819 | ||
c587e4a6 RP |
1820 | config KEXEC |
1821 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1822 | depends on (!SMP || PM_SLEEP_SMP) |
76950f71 | 1823 | depends on MMU |
2965faa5 | 1824 | select KEXEC_CORE |
c587e4a6 RP |
1825 | help |
1826 | kexec is a system call that implements the ability to shutdown your | |
1827 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1828 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1829 | you can start any kernel with it, not just Linux. |
1830 | ||
1831 | It is an ongoing process to be certain the hardware in a machine | |
1832 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1833 | initially work for you. |
c587e4a6 | 1834 | |
4cd9d6f7 RP |
1835 | config ATAGS_PROC |
1836 | bool "Export atags in procfs" | |
bd51e2f5 | 1837 | depends on ATAGS && KEXEC |
b98d7291 | 1838 | default y |
4cd9d6f7 RP |
1839 | help |
1840 | Should the atags used to boot the kernel be exported in an "atags" | |
1841 | file in procfs. Useful with kexec. | |
1842 | ||
cb5d39b3 MW |
1843 | config CRASH_DUMP |
1844 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
1845 | help |
1846 | Generate crash dump after being started by kexec. This should | |
1847 | be normally only set in special crash dump kernels which are | |
1848 | loaded in the main kernel with kexec-tools into a specially | |
1849 | reserved region and then later executed after a crash by | |
1850 | kdump/kexec. The crash dump kernel must be compiled to a | |
1851 | memory address not used by the main kernel | |
1852 | ||
330d4810 | 1853 | For more details see Documentation/admin-guide/kdump/kdump.rst |
cb5d39b3 | 1854 | |
e69edc79 EM |
1855 | config AUTO_ZRELADDR |
1856 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
1857 | help |
1858 | ZRELADDR is the physical address where the decompressed kernel | |
1859 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
0673cb38 GU |
1860 | will be determined at run-time, either by masking the current IP |
1861 | with 0xf8000000, or, if invalid, from the DTB passed in r2. | |
1862 | This assumes the zImage being placed in the first 128MB from | |
1863 | start of memory. | |
e69edc79 | 1864 | |
81a0bc39 RF |
1865 | config EFI_STUB |
1866 | bool | |
1867 | ||
1868 | config EFI | |
1869 | bool "UEFI runtime support" | |
1870 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
1871 | select UCS2_STRING | |
1872 | select EFI_PARAMS_FROM_FDT | |
1873 | select EFI_STUB | |
2e0eb483 | 1874 | select EFI_GENERIC_STUB |
81a0bc39 | 1875 | select EFI_RUNTIME_WRAPPERS |
a7f7f624 | 1876 | help |
81a0bc39 RF |
1877 | This option provides support for runtime services provided |
1878 | by UEFI firmware (such as non-volatile variables, realtime | |
1879 | clock, and platform reset). A UEFI stub is also provided to | |
1880 | allow the kernel to be booted as an EFI application. This | |
1881 | is only useful for kernels that may run on systems that have | |
1882 | UEFI firmware. | |
1883 | ||
bb817bef AB |
1884 | config DMI |
1885 | bool "Enable support for SMBIOS (DMI) tables" | |
1886 | depends on EFI | |
1887 | default y | |
1888 | help | |
1889 | This enables SMBIOS/DMI feature for systems. | |
1890 | ||
1891 | This option is only useful on systems that have UEFI firmware. | |
1892 | However, even with this option, the resultant kernel should | |
1893 | continue to boot on existing non-UEFI platforms. | |
1894 | ||
1895 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
1896 | i.e., the the practice of identifying the platform via DMI to | |
1897 | decide whether certain workarounds for buggy hardware and/or | |
1898 | firmware need to be enabled. This would require the DMI subsystem | |
1899 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
1900 | ||
1da177e4 LT |
1901 | endmenu |
1902 | ||
ac9d7efc | 1903 | menu "CPU Power Management" |
1da177e4 | 1904 | |
1da177e4 | 1905 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 1906 | |
ac9d7efc RK |
1907 | source "drivers/cpuidle/Kconfig" |
1908 | ||
1909 | endmenu | |
1910 | ||
1da177e4 LT |
1911 | menu "Floating point emulation" |
1912 | ||
1913 | comment "At least one emulation must be selected" | |
1914 | ||
1915 | config FPE_NWFPE | |
1916 | bool "NWFPE math emulation" | |
593c252a | 1917 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
a7f7f624 | 1918 | help |
1da177e4 LT |
1919 | Say Y to include the NWFPE floating point emulator in the kernel. |
1920 | This is necessary to run most binaries. Linux does not currently | |
1921 | support floating point hardware so you need to say Y here even if | |
1922 | your machine has an FPA or floating point co-processor podule. | |
1923 | ||
1924 | You may say N here if you are going to load the Acorn FPEmulator | |
1925 | early in the bootup. | |
1926 | ||
1927 | config FPE_NWFPE_XP | |
1928 | bool "Support extended precision" | |
bedf142b | 1929 | depends on FPE_NWFPE |
1da177e4 LT |
1930 | help |
1931 | Say Y to include 80-bit support in the kernel floating-point | |
1932 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
1933 | Note that gcc does not generate 80-bit operations by default, | |
1934 | so in most cases this option only enlarges the size of the | |
1935 | floating point emulator without any good reason. | |
1936 | ||
1937 | You almost surely want to say N here. | |
1938 | ||
1939 | config FPE_FASTFPE | |
1940 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 1941 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
a7f7f624 | 1942 | help |
1da177e4 LT |
1943 | Say Y here to include the FAST floating point emulator in the kernel. |
1944 | This is an experimental much faster emulator which now also has full | |
1945 | precision for the mantissa. It does not support any exceptions. | |
1946 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
1947 | ||
1948 | It should be sufficient for most programs. It may be not suitable | |
1949 | for scientific calculations, but you have to check this for yourself. | |
1950 | If you do not feel you need a faster FP emulation you should better | |
1951 | choose NWFPE. | |
1952 | ||
1953 | config VFP | |
1954 | bool "VFP-format floating point maths" | |
e399b1a4 | 1955 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
1956 | help |
1957 | Say Y to include VFP support code in the kernel. This is needed | |
1958 | if your hardware includes a VFP unit. | |
1959 | ||
dc7a12bd | 1960 | Please see <file:Documentation/arm/vfp/release-notes.rst> for |
1da177e4 LT |
1961 | release notes and additional status information. |
1962 | ||
1963 | Say N if your target does not have VFP hardware. | |
1964 | ||
25ebee02 CM |
1965 | config VFPv3 |
1966 | bool | |
1967 | depends on VFP | |
1968 | default y if CPU_V7 | |
1969 | ||
b5872db4 CM |
1970 | config NEON |
1971 | bool "Advanced SIMD (NEON) Extension support" | |
1972 | depends on VFPv3 && CPU_V7 | |
1973 | help | |
1974 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
1975 | Extension. | |
1976 | ||
73c132c1 AB |
1977 | config KERNEL_MODE_NEON |
1978 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 1979 | depends on NEON && AEABI |
73c132c1 AB |
1980 | help |
1981 | Say Y to include support for NEON in kernel mode. | |
1982 | ||
1da177e4 LT |
1983 | endmenu |
1984 | ||
1da177e4 LT |
1985 | menu "Power management options" |
1986 | ||
eceab4ac | 1987 | source "kernel/power/Kconfig" |
1da177e4 | 1988 | |
f4cb5700 | 1989 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 1990 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 1991 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
1992 | def_bool y |
1993 | ||
15e0d9e3 | 1994 | config ARM_CPU_SUSPEND |
8b6f2499 | 1995 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 1996 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 1997 | |
603fb42a SC |
1998 | config ARCH_HIBERNATION_POSSIBLE |
1999 | bool | |
2000 | depends on MMU | |
2001 | default y if ARCH_SUSPEND_POSSIBLE | |
2002 | ||
1da177e4 LT |
2003 | endmenu |
2004 | ||
916f743d KG |
2005 | source "drivers/firmware/Kconfig" |
2006 | ||
652ccae5 AB |
2007 | if CRYPTO |
2008 | source "arch/arm/crypto/Kconfig" | |
2009 | endif | |
2cbd1cc3 SA |
2010 | |
2011 | source "arch/arm/Kconfig.assembler" |