Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
1d8f51d4 | 5 | select ARCH_CLOCKSOURCE_DATA |
ec80eb46 | 6 | select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC |
c7780ab5 | 7 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
21266be9 | 8 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
2b68f6ca | 9 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 10 | select ARCH_HAS_FORTIFY_SOURCE |
75851720 | 11 | select ARCH_HAS_KCOV |
e69244d2 | 12 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
3010a5ea | 13 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
ea8c64ac | 14 | select ARCH_HAS_PHYS_TO_DMA |
75851720 | 15 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
16 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
17 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
3d06770e | 18 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 19 | select ARCH_HAVE_CUSTOM_GPIO_H |
957e3fac | 20 | select ARCH_HAS_GCOV_PROFILE_ALL |
d7018848 | 21 | select ARCH_MIGHT_HAVE_PC_PARPORT |
ad21fc4f LA |
22 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
23 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 24 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 25 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 26 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 27 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 28 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 29 | select CLONE_BACKWARDS |
b1b3f49c | 30 | select CPU_PM if (SUSPEND || CPU_IDLE) |
dce5c9e3 | 31 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
002e6745 | 32 | select DMA_DIRECT_OPS if !MMU |
b01aec9b BP |
33 | select EDAC_SUPPORT |
34 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 35 | select GENERIC_ALLOCATOR |
2ef7a295 | 36 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
4477ca45 | 37 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 38 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
ea2d9a96 | 39 | select GENERIC_CPU_AUTOPROBE |
2937367b | 40 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 41 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
42 | select GENERIC_IRQ_PROBE |
43 | select GENERIC_IRQ_SHOW | |
7c07005e | 44 | select GENERIC_IRQ_SHOW_LEVEL |
b1b3f49c | 45 | select GENERIC_PCI_IOMAP |
38ff87f7 | 46 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
47 | select GENERIC_SMP_IDLE_THREAD |
48 | select GENERIC_STRNCPY_FROM_USER | |
49 | select GENERIC_STRNLEN_USER | |
a71b092a | 50 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 51 | select HARDIRQS_SW_RESEND |
7a017721 | 52 | select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) |
0b7857db | 53 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee AB |
54 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
55 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU | |
e0c25d95 | 56 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
91702175 | 57 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
08626a60 | 58 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 59 | select HAVE_ARCH_TRACEHOOK |
b329f95d | 60 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 61 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 62 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
63 | select HAVE_C_RECORDMCOUNT |
64 | select HAVE_DEBUG_KMEMLEAK | |
b1b3f49c | 65 | select HAVE_DMA_CONTIGUOUS if MMU |
437682ee | 66 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 67 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 68 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 69 | select HAVE_EXIT_THREAD |
b1b3f49c | 70 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 71 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 72 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
6b90bd4b | 73 | select HAVE_GCC_PLUGINS |
1fe53268 | 74 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
75 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
76 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 77 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 78 | select HAVE_KERNEL_GZIP |
f9b493ac | 79 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 80 | select HAVE_KERNEL_LZMA |
b1b3f49c | 81 | select HAVE_KERNEL_LZO |
a7f464f3 | 82 | select HAVE_KERNEL_XZ |
cb1293e2 | 83 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
b1b3f49c | 84 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
7d485f64 | 85 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 86 | select HAVE_NMI |
b1b3f49c | 87 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
0dc016db | 88 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 89 | select HAVE_PERF_EVENTS |
49863894 WD |
90 | select HAVE_PERF_REGS |
91 | select HAVE_PERF_USER_STACK_DUMP | |
a0ad5496 | 92 | select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) |
e513f8bf | 93 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 94 | select HAVE_RSEQ |
d148eac0 | 95 | select HAVE_STACKPROTECTOR |
b1b3f49c | 96 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 97 | select HAVE_UID16 |
31c1fc81 | 98 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 99 | select IRQ_FORCED_THREADING |
171b3f0d | 100 | select MODULES_USE_ELF_REL |
f616ab59 | 101 | select NEED_DMA_MAP_STATE |
aa7d5f18 AB |
102 | select OF_EARLY_FLATTREE if OF |
103 | select OF_RESERVED_MEM if OF | |
171b3f0d RK |
104 | select OLD_SIGACTION |
105 | select OLD_SIGSUSPEND3 | |
b1b3f49c | 106 | select PERF_USE_VMALLOC |
b26d07a0 | 107 | select REFCOUNT_FULL |
b1b3f49c RK |
108 | select RTC_LIB |
109 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
110 | # Above selects are sorted alphabetically; please add new ones |
111 | # according to that. Thanks. | |
1da177e4 LT |
112 | help |
113 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 114 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 115 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 116 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
117 | Europe. There is an ARM Linux project with a web page at |
118 | <http://www.arm.linux.org.uk/>. | |
119 | ||
74facffe | 120 | config ARM_HAS_SG_CHAIN |
308c09f1 | 121 | select ARCH_HAS_SG_CHAIN |
74facffe RK |
122 | bool |
123 | ||
4ce63fcd | 124 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 125 | bool |
b1b3f49c RK |
126 | select ARM_HAS_SG_CHAIN |
127 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 128 | |
60460abf SWK |
129 | if ARM_DMA_USE_IOMMU |
130 | ||
131 | config ARM_DMA_IOMMU_ALIGNMENT | |
132 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
133 | range 4 9 | |
134 | default 8 | |
135 | help | |
136 | DMA mapping framework by default aligns all buffers to the smallest | |
137 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
138 | size. This works well for buffers up to a few hundreds kilobytes, but | |
139 | for larger buffers it just a waste of address space. Drivers which has | |
140 | relatively small addressing window (like 64Mib) might run out of | |
141 | virtual space with just a few allocations. | |
142 | ||
143 | With this parameter you can specify the maximum PAGE_SIZE order for | |
144 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
145 | specified order. The order is expressed as a power of two multiplied | |
146 | by the PAGE_SIZE. | |
147 | ||
148 | endif | |
149 | ||
0b05da72 HUK |
150 | config MIGHT_HAVE_PCI |
151 | bool | |
152 | ||
75e7153a RB |
153 | config SYS_SUPPORTS_APM_EMULATION |
154 | bool | |
155 | ||
bc581770 LW |
156 | config HAVE_TCM |
157 | bool | |
158 | select GENERIC_ALLOCATOR | |
159 | ||
e119bfff RK |
160 | config HAVE_PROC_CPU |
161 | bool | |
162 | ||
ce816fa8 | 163 | config NO_IOPORT_MAP |
5ea81769 | 164 | bool |
5ea81769 | 165 | |
1da177e4 LT |
166 | config EISA |
167 | bool | |
168 | ---help--- | |
169 | The Extended Industry Standard Architecture (EISA) bus was | |
170 | developed as an open alternative to the IBM MicroChannel bus. | |
171 | ||
172 | The EISA bus provided some of the features of the IBM MicroChannel | |
173 | bus while maintaining backward compatibility with cards made for | |
174 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
175 | 1995 when it was made obsolete by the PCI bus. | |
176 | ||
177 | Say Y here if you are building a kernel for an EISA-based machine. | |
178 | ||
179 | Otherwise, say N. | |
180 | ||
181 | config SBUS | |
182 | bool | |
183 | ||
f16fb1ec RK |
184 | config STACKTRACE_SUPPORT |
185 | bool | |
186 | default y | |
187 | ||
188 | config LOCKDEP_SUPPORT | |
189 | bool | |
190 | default y | |
191 | ||
7ad1bcb2 RK |
192 | config TRACE_IRQFLAGS_SUPPORT |
193 | bool | |
cb1293e2 | 194 | default !CPU_V7M |
7ad1bcb2 | 195 | |
1da177e4 LT |
196 | config RWSEM_XCHGADD_ALGORITHM |
197 | bool | |
8a87411b | 198 | default y |
1da177e4 | 199 | |
f0d1b0b3 DH |
200 | config ARCH_HAS_ILOG2_U32 |
201 | bool | |
f0d1b0b3 DH |
202 | |
203 | config ARCH_HAS_ILOG2_U64 | |
204 | bool | |
f0d1b0b3 | 205 | |
4a1b5733 EV |
206 | config ARCH_HAS_BANDGAP |
207 | bool | |
208 | ||
a5f4c561 SA |
209 | config FIX_EARLYCON_MEM |
210 | def_bool y if MMU | |
211 | ||
b89c3b16 AM |
212 | config GENERIC_HWEIGHT |
213 | bool | |
214 | default y | |
215 | ||
1da177e4 LT |
216 | config GENERIC_CALIBRATE_DELAY |
217 | bool | |
218 | default y | |
219 | ||
a08b6b79 Z |
220 | config ARCH_MAY_HAVE_PC_FDC |
221 | bool | |
222 | ||
5ac6da66 CL |
223 | config ZONE_DMA |
224 | bool | |
5ac6da66 | 225 | |
c7edc9e3 DL |
226 | config ARCH_SUPPORTS_UPROBES |
227 | def_bool y | |
228 | ||
58af4a24 RH |
229 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
230 | bool | |
231 | ||
1da177e4 LT |
232 | config GENERIC_ISA_DMA |
233 | bool | |
234 | ||
1da177e4 LT |
235 | config FIQ |
236 | bool | |
237 | ||
13a5045d RH |
238 | config NEED_RET_TO_USER |
239 | bool | |
240 | ||
034d2f5a AV |
241 | config ARCH_MTD_XIP |
242 | bool | |
243 | ||
dc21af99 | 244 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
245 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
246 | default y | |
b511d75d | 247 | depends on !XIP_KERNEL && MMU |
dc21af99 | 248 | help |
111e9a5c RK |
249 | Patch phys-to-virt and virt-to-phys translation functions at |
250 | boot and module load time according to the position of the | |
251 | kernel in system memory. | |
dc21af99 | 252 | |
111e9a5c | 253 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 254 | of physical memory is at a 16MB boundary. |
dc21af99 | 255 | |
c1becedc RK |
256 | Only disable this option if you know that you do not require |
257 | this feature (eg, building a kernel for a single machine) and | |
258 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 259 | |
c334bc15 RH |
260 | config NEED_MACH_IO_H |
261 | bool | |
262 | help | |
263 | Select this when mach/io.h is required to provide special | |
264 | definitions for this platform. The need for mach/io.h should | |
265 | be avoided when possible. | |
266 | ||
0cdc8b92 | 267 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
268 | bool |
269 | help | |
0cdc8b92 NP |
270 | Select this when mach/memory.h is required to provide special |
271 | definitions for this platform. The need for mach/memory.h should | |
272 | be avoided when possible. | |
dc21af99 | 273 | |
1b9f95f8 | 274 | config PHYS_OFFSET |
974c0724 | 275 | hex "Physical address of main memory" if MMU |
c6f54a9b | 276 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 277 | default DRAM_BASE if !MMU |
c6f54a9b | 278 | default 0x00000000 if ARCH_EBSA110 || \ |
c6f54a9b UKK |
279 | ARCH_FOOTBRIDGE || \ |
280 | ARCH_INTEGRATOR || \ | |
281 | ARCH_IOP13XX || \ | |
282 | ARCH_KS8695 || \ | |
8f2c0062 | 283 | ARCH_REALVIEW |
c6f54a9b UKK |
284 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
285 | default 0x20000000 if ARCH_S5PV210 | |
b8824c9a | 286 | default 0xc0000000 if ARCH_SA1100 |
111e9a5c | 287 | help |
1b9f95f8 NP |
288 | Please provide the physical address corresponding to the |
289 | location of main memory in your system. | |
cada3c08 | 290 | |
87e040b6 SG |
291 | config GENERIC_BUG |
292 | def_bool y | |
293 | depends on BUG | |
294 | ||
1bcad26e KS |
295 | config PGTABLE_LEVELS |
296 | int | |
297 | default 3 if ARM_LPAE | |
298 | default 2 | |
299 | ||
1da177e4 LT |
300 | menu "System Type" |
301 | ||
3c427975 HC |
302 | config MMU |
303 | bool "MMU-based Paged Memory Management Support" | |
304 | default y | |
305 | help | |
306 | Select if you want MMU-based virtualised addressing space | |
307 | support by paged memory management. If unsure, say 'Y'. | |
308 | ||
e0c25d95 DC |
309 | config ARCH_MMAP_RND_BITS_MIN |
310 | default 8 | |
311 | ||
312 | config ARCH_MMAP_RND_BITS_MAX | |
313 | default 14 if PAGE_OFFSET=0x40000000 | |
314 | default 15 if PAGE_OFFSET=0x80000000 | |
315 | default 16 | |
316 | ||
ccf50e23 RK |
317 | # |
318 | # The "ARM system type" choice list is ordered alphabetically by option | |
319 | # text. Please add new entries in the option alphabetic order. | |
320 | # | |
1da177e4 LT |
321 | choice |
322 | prompt "ARM system type" | |
70722803 | 323 | default ARM_SINGLE_ARMV7M if !MMU |
1420b22b | 324 | default ARCH_MULTIPLATFORM if MMU |
1da177e4 | 325 | |
387798b3 RH |
326 | config ARCH_MULTIPLATFORM |
327 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 328 | depends on MMU |
42dc836d | 329 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
330 | select ARM_PATCH_PHYS_VIRT |
331 | select AUTO_ZRELADDR | |
bb0eb050 | 332 | select TIMER_OF |
66314223 | 333 | select COMMON_CLK |
ddb902cc | 334 | select GENERIC_CLOCKEVENTS |
4c301f9b | 335 | select GENERIC_IRQ_MULTI_HANDLER |
08d38beb | 336 | select MIGHT_HAVE_PCI |
e13688fe | 337 | select PCI_DOMAINS if PCI |
66314223 DN |
338 | select SPARSE_IRQ |
339 | select USE_OF | |
66314223 | 340 | |
9c77bc43 SA |
341 | config ARM_SINGLE_ARMV7M |
342 | bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" | |
343 | depends on !MMU | |
9c77bc43 | 344 | select ARM_NVIC |
499f1640 | 345 | select AUTO_ZRELADDR |
bb0eb050 | 346 | select TIMER_OF |
9c77bc43 SA |
347 | select COMMON_CLK |
348 | select CPU_V7M | |
349 | select GENERIC_CLOCKEVENTS | |
350 | select NO_IOPORT_MAP | |
351 | select SPARSE_IRQ | |
352 | select USE_OF | |
353 | ||
1da177e4 LT |
354 | config ARCH_EBSA110 |
355 | bool "EBSA-110" | |
b1b3f49c | 356 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 357 | select CPU_SA110 |
f7e68bbf | 358 | select ISA |
c334bc15 | 359 | select NEED_MACH_IO_H |
0cdc8b92 | 360 | select NEED_MACH_MEMORY_H |
ce816fa8 | 361 | select NO_IOPORT_MAP |
1da177e4 LT |
362 | help |
363 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 364 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
365 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
366 | parallel port. | |
367 | ||
e7736d47 LB |
368 | config ARCH_EP93XX |
369 | bool "EP93xx-based" | |
80320927 | 370 | select ARCH_SPARSEMEM_ENABLE |
e7736d47 | 371 | select ARM_AMBA |
cd5bad41 | 372 | imply ARM_PATCH_PHYS_VIRT |
e7736d47 | 373 | select ARM_VIC |
b8824c9a | 374 | select AUTO_ZRELADDR |
6d803ba7 | 375 | select CLKDEV_LOOKUP |
000bc178 | 376 | select CLKSRC_MMIO |
b1b3f49c | 377 | select CPU_ARM920T |
000bc178 | 378 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 379 | select GPIOLIB |
e7736d47 LB |
380 | help |
381 | This enables support for the Cirrus EP93xx series of CPUs. | |
382 | ||
1da177e4 LT |
383 | config ARCH_FOOTBRIDGE |
384 | bool "FootBridge" | |
c750815e | 385 | select CPU_SA110 |
1da177e4 | 386 | select FOOTBRIDGE |
4e8d7637 | 387 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 388 | select HAVE_IDE |
8ef6e620 | 389 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 390 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
391 | help |
392 | Support for systems based on the DC21285 companion chip | |
393 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 394 | |
4af6fee1 DS |
395 | config ARCH_NETX |
396 | bool "Hilscher NetX based" | |
b1b3f49c | 397 | select ARM_VIC |
234b6ced | 398 | select CLKSRC_MMIO |
c750815e | 399 | select CPU_ARM926T |
2fcfe6b8 | 400 | select GENERIC_CLOCKEVENTS |
f999b8bd | 401 | help |
4af6fee1 DS |
402 | This enables support for systems based on the Hilscher NetX Soc |
403 | ||
3b938be6 RK |
404 | config ARCH_IOP13XX |
405 | bool "IOP13xx-based" | |
406 | depends on MMU | |
b1b3f49c | 407 | select CPU_XSC3 |
0cdc8b92 | 408 | select NEED_MACH_MEMORY_H |
13a5045d | 409 | select NEED_RET_TO_USER |
b1b3f49c RK |
410 | select PCI |
411 | select PLAT_IOP | |
412 | select VMSPLIT_1G | |
37ebbcff | 413 | select SPARSE_IRQ |
3b938be6 RK |
414 | help |
415 | Support for Intel's IOP13XX (XScale) family of processors. | |
416 | ||
3f7e5815 LB |
417 | config ARCH_IOP32X |
418 | bool "IOP32x-based" | |
a4f7e763 | 419 | depends on MMU |
c750815e | 420 | select CPU_XSCALE |
e9004f50 | 421 | select GPIO_IOP |
5c34a4e8 | 422 | select GPIOLIB |
13a5045d | 423 | select NEED_RET_TO_USER |
f7e68bbf | 424 | select PCI |
b1b3f49c | 425 | select PLAT_IOP |
f999b8bd | 426 | help |
3f7e5815 LB |
427 | Support for Intel's 80219 and IOP32X (XScale) family of |
428 | processors. | |
429 | ||
430 | config ARCH_IOP33X | |
431 | bool "IOP33x-based" | |
432 | depends on MMU | |
c750815e | 433 | select CPU_XSCALE |
e9004f50 | 434 | select GPIO_IOP |
5c34a4e8 | 435 | select GPIOLIB |
13a5045d | 436 | select NEED_RET_TO_USER |
3f7e5815 | 437 | select PCI |
b1b3f49c | 438 | select PLAT_IOP |
3f7e5815 LB |
439 | help |
440 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 441 | |
3b938be6 RK |
442 | config ARCH_IXP4XX |
443 | bool "IXP4xx-based" | |
a4f7e763 | 444 | depends on MMU |
58af4a24 | 445 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
51aaf81f | 446 | select ARCH_SUPPORTS_BIG_ENDIAN |
234b6ced | 447 | select CLKSRC_MMIO |
c750815e | 448 | select CPU_XSCALE |
b1b3f49c | 449 | select DMABOUNCE if PCI |
3b938be6 | 450 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 451 | select GPIOLIB |
0b05da72 | 452 | select MIGHT_HAVE_PCI |
c334bc15 | 453 | select NEED_MACH_IO_H |
9296d94d | 454 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 455 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 456 | help |
3b938be6 | 457 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 458 | |
edabd38e SB |
459 | config ARCH_DOVE |
460 | bool "Marvell Dove" | |
756b2531 | 461 | select CPU_PJ4 |
edabd38e | 462 | select GENERIC_CLOCKEVENTS |
4c301f9b | 463 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 464 | select GPIOLIB |
0f81bd43 | 465 | select MIGHT_HAVE_PCI |
171b3f0d | 466 | select MVEBU_MBUS |
9139acd1 SH |
467 | select PINCTRL |
468 | select PINCTRL_DOVE | |
abcda1dc | 469 | select PLAT_ORION_LEGACY |
0bd86961 | 470 | select SPARSE_IRQ |
c5d431e8 | 471 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 472 | help |
edabd38e | 473 | Support for the Marvell Dove SoC 88AP510 |
788c9700 RK |
474 | |
475 | config ARCH_KS8695 | |
476 | bool "Micrel/Kendin KS8695" | |
c7e783d6 | 477 | select CLKSRC_MMIO |
b1b3f49c | 478 | select CPU_ARM922T |
c7e783d6 | 479 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 480 | select GPIOLIB |
b1b3f49c | 481 | select NEED_MACH_MEMORY_H |
788c9700 RK |
482 | help |
483 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
484 | System-on-Chip devices. | |
485 | ||
788c9700 RK |
486 | config ARCH_W90X900 |
487 | bool "Nuvoton W90X900 CPU" | |
6d803ba7 | 488 | select CLKDEV_LOOKUP |
6fa5d5f7 | 489 | select CLKSRC_MMIO |
b1b3f49c | 490 | select CPU_ARM926T |
58b5369e | 491 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 492 | select GPIOLIB |
788c9700 | 493 | help |
a8bc4ead | 494 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
495 | At present, the w90x900 has been renamed nuc900, regarding | |
496 | the ARM series product line, you can login the following | |
497 | link address to know more. | |
498 | ||
499 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
500 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 501 | |
93e22567 RK |
502 | config ARCH_LPC32XX |
503 | bool "NXP LPC32XX" | |
93e22567 RK |
504 | select ARM_AMBA |
505 | select CLKDEV_LOOKUP | |
c227f127 VZ |
506 | select CLKSRC_LPC32XX |
507 | select COMMON_CLK | |
93e22567 RK |
508 | select CPU_ARM926T |
509 | select GENERIC_CLOCKEVENTS | |
4c301f9b | 510 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 511 | select GPIOLIB |
8cb17b5e | 512 | select SPARSE_IRQ |
93e22567 RK |
513 | select USE_OF |
514 | help | |
515 | Support for the NXP LPC32XX family of processors | |
516 | ||
1da177e4 | 517 | config ARCH_PXA |
2c8086a5 | 518 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 519 | depends on MMU |
b1b3f49c | 520 | select ARCH_MTD_XIP |
b1b3f49c RK |
521 | select ARM_CPU_SUSPEND if PM |
522 | select AUTO_ZRELADDR | |
a1c0a6ad | 523 | select COMMON_CLK |
6d803ba7 | 524 | select CLKDEV_LOOKUP |
389d9b58 | 525 | select CLKSRC_PXA |
234b6ced | 526 | select CLKSRC_MMIO |
bb0eb050 | 527 | select TIMER_OF |
2f202861 | 528 | select CPU_XSCALE if !CPU_XSC3 |
981d0f39 | 529 | select GENERIC_CLOCKEVENTS |
4c301f9b | 530 | select GENERIC_IRQ_MULTI_HANDLER |
157d2644 | 531 | select GPIO_PXA |
5c34a4e8 | 532 | select GPIOLIB |
d0ee9f40 | 533 | select HAVE_IDE |
d6cf30ca | 534 | select IRQ_DOMAIN |
b1b3f49c RK |
535 | select PLAT_PXA |
536 | select SPARSE_IRQ | |
f999b8bd | 537 | help |
2c8086a5 | 538 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
539 | |
540 | config ARCH_RPC | |
541 | bool "RiscPC" | |
868e87cc | 542 | depends on MMU |
1da177e4 | 543 | select ARCH_ACORN |
a08b6b79 | 544 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 545 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 546 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 547 | select CPU_SA110 |
b1b3f49c | 548 | select FIQ |
d0ee9f40 | 549 | select HAVE_IDE |
b1b3f49c RK |
550 | select HAVE_PATA_PLATFORM |
551 | select ISA_DMA_API | |
c334bc15 | 552 | select NEED_MACH_IO_H |
0cdc8b92 | 553 | select NEED_MACH_MEMORY_H |
ce816fa8 | 554 | select NO_IOPORT_MAP |
1da177e4 LT |
555 | help |
556 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
557 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
558 | ||
559 | config ARCH_SA1100 | |
560 | bool "SA1100-based" | |
b1b3f49c | 561 | select ARCH_MTD_XIP |
b1b3f49c RK |
562 | select ARCH_SPARSEMEM_ENABLE |
563 | select CLKDEV_LOOKUP | |
564 | select CLKSRC_MMIO | |
389d9b58 | 565 | select CLKSRC_PXA |
bb0eb050 | 566 | select TIMER_OF if OF |
1937f5b9 | 567 | select CPU_FREQ |
b1b3f49c | 568 | select CPU_SA1100 |
3e238be2 | 569 | select GENERIC_CLOCKEVENTS |
4c301f9b | 570 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 571 | select GPIOLIB |
d0ee9f40 | 572 | select HAVE_IDE |
1eca42b4 | 573 | select IRQ_DOMAIN |
b1b3f49c | 574 | select ISA |
0cdc8b92 | 575 | select NEED_MACH_MEMORY_H |
375dec92 | 576 | select SPARSE_IRQ |
f999b8bd MM |
577 | help |
578 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 579 | |
b130d5c2 KK |
580 | config ARCH_S3C24XX |
581 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 582 | select ATAGS |
b1b3f49c | 583 | select CLKDEV_LOOKUP |
4280506a | 584 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 585 | select GENERIC_CLOCKEVENTS |
880cf071 | 586 | select GPIO_SAMSUNG |
5c34a4e8 | 587 | select GPIOLIB |
4c301f9b | 588 | select GENERIC_IRQ_MULTI_HANDLER |
20676c15 | 589 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 590 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 591 | select HAVE_S3C_RTC if RTC_CLASS |
c334bc15 | 592 | select NEED_MACH_IO_H |
cd8dc7ae | 593 | select SAMSUNG_ATAGS |
ea04d6b4 | 594 | select USE_OF |
1da177e4 | 595 | help |
b130d5c2 KK |
596 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
597 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
598 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
599 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 600 | |
7c6337e2 KH |
601 | config ARCH_DAVINCI |
602 | bool "TI DaVinci" | |
b1b3f49c | 603 | select ARCH_HAS_HOLES_MEMORYMODEL |
27823278 | 604 | select COMMON_CLK |
ce32c5c5 | 605 | select CPU_ARM926T |
20e9969b | 606 | select GENERIC_ALLOCATOR |
b1b3f49c | 607 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 608 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 609 | select GPIOLIB |
b1b3f49c | 610 | select HAVE_IDE |
27823278 DL |
611 | select PM_GENERIC_DOMAINS if PM |
612 | select PM_GENERIC_DOMAINS_OF if PM && OF | |
613 | select RESET_CONTROLLER | |
689e331f | 614 | select USE_OF |
b1b3f49c | 615 | select ZONE_DMA |
7c6337e2 KH |
616 | help |
617 | Support for TI's DaVinci platform. | |
618 | ||
a0694861 TL |
619 | config ARCH_OMAP1 |
620 | bool "TI OMAP1" | |
00a36698 | 621 | depends on MMU |
9af915da | 622 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 623 | select ARCH_OMAP |
b1b3f49c | 624 | select CLKDEV_LOOKUP |
d6e15d78 | 625 | select CLKSRC_MMIO |
b1b3f49c | 626 | select GENERIC_CLOCKEVENTS |
a0694861 | 627 | select GENERIC_IRQ_CHIP |
4c301f9b | 628 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 629 | select GPIOLIB |
a0694861 TL |
630 | select HAVE_IDE |
631 | select IRQ_DOMAIN | |
632 | select NEED_MACH_IO_H if PCCARD | |
633 | select NEED_MACH_MEMORY_H | |
685e2d08 | 634 | select SPARSE_IRQ |
21f47fbc | 635 | help |
a0694861 | 636 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 637 | |
1da177e4 LT |
638 | endchoice |
639 | ||
387798b3 RH |
640 | menu "Multiple platform selection" |
641 | depends on ARCH_MULTIPLATFORM | |
642 | ||
643 | comment "CPU Core family selection" | |
644 | ||
f8afae40 AB |
645 | config ARCH_MULTI_V4 |
646 | bool "ARMv4 based platforms (FA526)" | |
647 | depends on !ARCH_MULTI_V6_V7 | |
648 | select ARCH_MULTI_V4_V5 | |
649 | select CPU_FA526 | |
650 | ||
387798b3 RH |
651 | config ARCH_MULTI_V4T |
652 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 653 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 654 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
655 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
656 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
657 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
658 | |
659 | config ARCH_MULTI_V5 | |
660 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 661 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 662 | select ARCH_MULTI_V4_V5 |
12567bbd | 663 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
664 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
665 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
666 | |
667 | config ARCH_MULTI_V4_V5 | |
668 | bool | |
669 | ||
670 | config ARCH_MULTI_V6 | |
8dda05cc | 671 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 672 | select ARCH_MULTI_V6_V7 |
42f4754a | 673 | select CPU_V6K |
387798b3 RH |
674 | |
675 | config ARCH_MULTI_V7 | |
8dda05cc | 676 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
677 | default y |
678 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 679 | select CPU_V7 |
90bc8ac7 | 680 | select HAVE_SMP |
387798b3 RH |
681 | |
682 | config ARCH_MULTI_V6_V7 | |
683 | bool | |
9352b05b | 684 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
685 | |
686 | config ARCH_MULTI_CPU_AUTO | |
687 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
688 | select ARCH_MULTI_V5 | |
689 | ||
690 | endmenu | |
691 | ||
05e2a3de | 692 | config ARCH_VIRT |
e3246542 MY |
693 | bool "Dummy Virtual Machine" |
694 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 695 | select ARM_AMBA |
05e2a3de | 696 | select ARM_GIC |
3ee80364 | 697 | select ARM_GIC_V2M if PCI |
0b28f1db | 698 | select ARM_GIC_V3 |
bb29cecb | 699 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 700 | select ARM_PSCI |
4b8b5f25 | 701 | select HAVE_ARM_ARCH_TIMER |
8e2649d0 | 702 | select ARCH_SUPPORTS_BIG_ENDIAN |
05e2a3de | 703 | |
ccf50e23 RK |
704 | # |
705 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
706 | # Kconfigs may be included either alphabetically (according to the | |
707 | # plat- suffix) or along side the corresponding mach-* source. | |
708 | # | |
6bb8536c AF |
709 | source "arch/arm/mach-actions/Kconfig" |
710 | ||
445d9b30 TZ |
711 | source "arch/arm/mach-alpine/Kconfig" |
712 | ||
590b460c LP |
713 | source "arch/arm/mach-artpec/Kconfig" |
714 | ||
d9bfc86d OR |
715 | source "arch/arm/mach-asm9260/Kconfig" |
716 | ||
a66c51f9 AB |
717 | source "arch/arm/mach-aspeed/Kconfig" |
718 | ||
95b8f20f RK |
719 | source "arch/arm/mach-at91/Kconfig" |
720 | ||
1d22924e AB |
721 | source "arch/arm/mach-axxia/Kconfig" |
722 | ||
8ac49e04 CD |
723 | source "arch/arm/mach-bcm/Kconfig" |
724 | ||
1c37fa10 SH |
725 | source "arch/arm/mach-berlin/Kconfig" |
726 | ||
1da177e4 LT |
727 | source "arch/arm/mach-clps711x/Kconfig" |
728 | ||
d94f944e AV |
729 | source "arch/arm/mach-cns3xxx/Kconfig" |
730 | ||
95b8f20f RK |
731 | source "arch/arm/mach-davinci/Kconfig" |
732 | ||
df8d742e BS |
733 | source "arch/arm/mach-digicolor/Kconfig" |
734 | ||
95b8f20f RK |
735 | source "arch/arm/mach-dove/Kconfig" |
736 | ||
e7736d47 LB |
737 | source "arch/arm/mach-ep93xx/Kconfig" |
738 | ||
a66c51f9 AB |
739 | source "arch/arm/mach-exynos/Kconfig" |
740 | source "arch/arm/plat-samsung/Kconfig" | |
741 | ||
1da177e4 LT |
742 | source "arch/arm/mach-footbridge/Kconfig" |
743 | ||
59d3a193 PZ |
744 | source "arch/arm/mach-gemini/Kconfig" |
745 | ||
387798b3 RH |
746 | source "arch/arm/mach-highbank/Kconfig" |
747 | ||
389ee0c2 HZ |
748 | source "arch/arm/mach-hisi/Kconfig" |
749 | ||
a66c51f9 AB |
750 | source "arch/arm/mach-imx/Kconfig" |
751 | ||
1da177e4 LT |
752 | source "arch/arm/mach-integrator/Kconfig" |
753 | ||
a66c51f9 AB |
754 | source "arch/arm/mach-iop13xx/Kconfig" |
755 | ||
3f7e5815 LB |
756 | source "arch/arm/mach-iop32x/Kconfig" |
757 | ||
758 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 LT |
759 | |
760 | source "arch/arm/mach-ixp4xx/Kconfig" | |
761 | ||
828989ad SS |
762 | source "arch/arm/mach-keystone/Kconfig" |
763 | ||
95b8f20f RK |
764 | source "arch/arm/mach-ks8695/Kconfig" |
765 | ||
a66c51f9 AB |
766 | source "arch/arm/mach-mediatek/Kconfig" |
767 | ||
3b8f5030 CC |
768 | source "arch/arm/mach-meson/Kconfig" |
769 | ||
a66c51f9 | 770 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 771 | |
a66c51f9 | 772 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 773 | |
794d15b2 SS |
774 | source "arch/arm/mach-mv78xx0/Kconfig" |
775 | ||
a66c51f9 | 776 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 777 | |
1d3f33d5 SG |
778 | source "arch/arm/mach-mxs/Kconfig" |
779 | ||
95b8f20f | 780 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 781 | |
95b8f20f | 782 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 783 | |
7bffa14c BH |
784 | source "arch/arm/mach-npcm/Kconfig" |
785 | ||
9851ca57 DT |
786 | source "arch/arm/mach-nspire/Kconfig" |
787 | ||
d48af15e TL |
788 | source "arch/arm/plat-omap/Kconfig" |
789 | ||
790 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 791 | |
1dbae815 TL |
792 | source "arch/arm/mach-omap2/Kconfig" |
793 | ||
9dd0b194 | 794 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 795 | |
a66c51f9 AB |
796 | source "arch/arm/mach-oxnas/Kconfig" |
797 | ||
387798b3 RH |
798 | source "arch/arm/mach-picoxcell/Kconfig" |
799 | ||
a66c51f9 AB |
800 | source "arch/arm/mach-prima2/Kconfig" |
801 | ||
95b8f20f RK |
802 | source "arch/arm/mach-pxa/Kconfig" |
803 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 804 | |
8fc1b0f8 KG |
805 | source "arch/arm/mach-qcom/Kconfig" |
806 | ||
95b8f20f RK |
807 | source "arch/arm/mach-realview/Kconfig" |
808 | ||
d63dc051 HS |
809 | source "arch/arm/mach-rockchip/Kconfig" |
810 | ||
a66c51f9 AB |
811 | source "arch/arm/mach-s3c24xx/Kconfig" |
812 | ||
813 | source "arch/arm/mach-s3c64xx/Kconfig" | |
814 | ||
815 | source "arch/arm/mach-s5pv210/Kconfig" | |
816 | ||
95b8f20f | 817 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 818 | |
a66c51f9 AB |
819 | source "arch/arm/mach-shmobile/Kconfig" |
820 | ||
387798b3 RH |
821 | source "arch/arm/mach-socfpga/Kconfig" |
822 | ||
a7ed099f | 823 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 824 | |
65ebcc11 SK |
825 | source "arch/arm/mach-sti/Kconfig" |
826 | ||
bcb84fb4 AT |
827 | source "arch/arm/mach-stm32/Kconfig" |
828 | ||
3b52634f MR |
829 | source "arch/arm/mach-sunxi/Kconfig" |
830 | ||
d6de5b02 MG |
831 | source "arch/arm/mach-tango/Kconfig" |
832 | ||
c5f80065 EG |
833 | source "arch/arm/mach-tegra/Kconfig" |
834 | ||
95b8f20f | 835 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 836 | |
ba56a987 MY |
837 | source "arch/arm/mach-uniphier/Kconfig" |
838 | ||
95b8f20f | 839 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
840 | |
841 | source "arch/arm/mach-versatile/Kconfig" | |
842 | ||
ceade897 | 843 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 844 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 845 | |
6f35f9a9 TP |
846 | source "arch/arm/mach-vt8500/Kconfig" |
847 | ||
7ec80ddf | 848 | source "arch/arm/mach-w90x900/Kconfig" |
849 | ||
acede515 JN |
850 | source "arch/arm/mach-zx/Kconfig" |
851 | ||
9a45eb69 JC |
852 | source "arch/arm/mach-zynq/Kconfig" |
853 | ||
499f1640 SA |
854 | # ARMv7-M architecture |
855 | config ARCH_EFM32 | |
856 | bool "Energy Micro efm32" | |
857 | depends on ARM_SINGLE_ARMV7M | |
5c34a4e8 | 858 | select GPIOLIB |
499f1640 SA |
859 | help |
860 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
861 | processors. | |
862 | ||
863 | config ARCH_LPC18XX | |
864 | bool "NXP LPC18xx/LPC43xx" | |
865 | depends on ARM_SINGLE_ARMV7M | |
866 | select ARCH_HAS_RESET_CONTROLLER | |
867 | select ARM_AMBA | |
868 | select CLKSRC_LPC32XX | |
869 | select PINCTRL | |
870 | help | |
871 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
872 | high performance microcontrollers. | |
873 | ||
1847119d | 874 | config ARCH_MPS2 |
17bd274e | 875 | bool "ARM MPS2 platform" |
1847119d VM |
876 | depends on ARM_SINGLE_ARMV7M |
877 | select ARM_AMBA | |
878 | select CLKSRC_MPS2 | |
879 | help | |
880 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
881 | with a range of available cores like Cortex-M3/M4/M7. | |
882 | ||
883 | Please, note that depends which Application Note is used memory map | |
884 | for the platform may vary, so adjustment of RAM base might be needed. | |
885 | ||
1da177e4 LT |
886 | # Definitions to make life easier |
887 | config ARCH_ACORN | |
888 | bool | |
889 | ||
7ae1f7ec LB |
890 | config PLAT_IOP |
891 | bool | |
469d3044 | 892 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 893 | |
69b02f6a LB |
894 | config PLAT_ORION |
895 | bool | |
bfe45e0b | 896 | select CLKSRC_MMIO |
b1b3f49c | 897 | select COMMON_CLK |
dc7ad3b3 | 898 | select GENERIC_IRQ_CHIP |
278b45b0 | 899 | select IRQ_DOMAIN |
69b02f6a | 900 | |
abcda1dc TP |
901 | config PLAT_ORION_LEGACY |
902 | bool | |
903 | select PLAT_ORION | |
904 | ||
bd5ce433 EM |
905 | config PLAT_PXA |
906 | bool | |
907 | ||
f4b8b319 RK |
908 | config PLAT_VERSATILE |
909 | bool | |
910 | ||
d9a1beaa AC |
911 | source "arch/arm/firmware/Kconfig" |
912 | ||
1da177e4 LT |
913 | source arch/arm/mm/Kconfig |
914 | ||
afe4b25e | 915 | config IWMMXT |
d93003e8 SH |
916 | bool "Enable iWMMXt support" |
917 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
918 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
919 | help |
920 | Enable support for iWMMXt context switching at run time if | |
921 | running on a CPU that supports it. | |
922 | ||
3b93e7b0 HC |
923 | if !MMU |
924 | source "arch/arm/Kconfig-nommu" | |
925 | endif | |
926 | ||
3e0a07f8 GC |
927 | config PJ4B_ERRATA_4742 |
928 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
929 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
930 | default y | |
931 | help | |
932 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
933 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
934 | the retiring WFI/WFE instructions and the newly issued subsequent | |
935 | instructions. This sensitivity can result in a CPU hang scenario. | |
936 | Workaround: | |
937 | The software must insert either a Data Synchronization Barrier (DSB) | |
938 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
939 | instruction | |
940 | ||
f0c4b8d6 WD |
941 | config ARM_ERRATA_326103 |
942 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
943 | depends on CPU_V6 | |
944 | help | |
945 | Executing a SWP instruction to read-only memory does not set bit 11 | |
946 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
947 | treat the access as a read, preventing a COW from occurring and | |
948 | causing the faulting task to livelock. | |
949 | ||
9cba3ccc CM |
950 | config ARM_ERRATA_411920 |
951 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 952 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
953 | help |
954 | Invalidation of the Instruction Cache operation can | |
955 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
956 | It does not affect the MPCore. This option enables the ARM Ltd. | |
957 | recommended workaround. | |
958 | ||
7ce236fc CM |
959 | config ARM_ERRATA_430973 |
960 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
961 | depends on CPU_V7 | |
962 | help | |
963 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 964 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
965 | interworking branch is replaced with another code sequence at the |
966 | same virtual address, whether due to self-modifying code or virtual | |
967 | to physical address re-mapping, Cortex-A8 does not recover from the | |
968 | stale interworking branch prediction. This results in Cortex-A8 | |
969 | executing the new code sequence in the incorrect ARM or Thumb state. | |
970 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
971 | and also flushes the branch target cache at every context switch. | |
972 | Note that setting specific bits in the ACTLR register may not be | |
973 | available in non-secure mode. | |
974 | ||
855c551f CM |
975 | config ARM_ERRATA_458693 |
976 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
977 | depends on CPU_V7 | |
62e4d357 | 978 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
979 | help |
980 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
981 | erratum. For very specific sequences of memory operations, it is | |
982 | possible for a hazard condition intended for a cache line to instead | |
983 | be incorrectly associated with a different cache line. This false | |
984 | hazard might then cause a processor deadlock. The workaround enables | |
985 | the L1 caching of the NEON accesses and disables the PLD instruction | |
986 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
987 | register may not be available in non-secure mode. | |
988 | ||
0516e464 CM |
989 | config ARM_ERRATA_460075 |
990 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
991 | depends on CPU_V7 | |
62e4d357 | 992 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
993 | help |
994 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
995 | erratum. Any asynchronous access to the L2 cache may encounter a | |
996 | situation in which recent store transactions to the L2 cache are lost | |
997 | and overwritten with stale memory contents from external memory. The | |
998 | workaround disables the write-allocate mode for the L2 cache via the | |
999 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1000 | may not be available in non-secure mode. | |
1001 | ||
9f05027c WD |
1002 | config ARM_ERRATA_742230 |
1003 | bool "ARM errata: DMB operation may be faulty" | |
1004 | depends on CPU_V7 && SMP | |
62e4d357 | 1005 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1006 | help |
1007 | This option enables the workaround for the 742230 Cortex-A9 | |
1008 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1009 | between two write operations may not ensure the correct visibility | |
1010 | ordering of the two writes. This workaround sets a specific bit in | |
1011 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1012 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1013 | the two writes. | |
1014 | ||
a672e99b WD |
1015 | config ARM_ERRATA_742231 |
1016 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1017 | depends on CPU_V7 && SMP | |
62e4d357 | 1018 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1019 | help |
1020 | This option enables the workaround for the 742231 Cortex-A9 | |
1021 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1022 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1023 | accessing some data located in the same cache line, may get corrupted | |
1024 | data due to bad handling of the address hazard when the line gets | |
1025 | replaced from one of the CPUs at the same time as another CPU is | |
1026 | accessing it. This workaround sets specific bits in the diagnostic | |
1027 | register of the Cortex-A9 which reduces the linefill issuing | |
1028 | capabilities of the processor. | |
1029 | ||
69155794 JM |
1030 | config ARM_ERRATA_643719 |
1031 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1032 | depends on CPU_V7 && SMP | |
e5a5de44 | 1033 | default y |
69155794 JM |
1034 | help |
1035 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1036 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1037 | register returns zero when it should return one. The workaround | |
1038 | corrects this value, ensuring cache maintenance operations which use | |
1039 | it behave as intended and avoiding data corruption. | |
1040 | ||
cdf357f1 WD |
1041 | config ARM_ERRATA_720789 |
1042 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1043 | depends on CPU_V7 |
cdf357f1 WD |
1044 | help |
1045 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1046 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1047 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1048 | As a consequence of this erratum, some TLB entries which should be | |
1049 | invalidated are not, resulting in an incoherency in the system page | |
1050 | tables. The workaround changes the TLB flushing routines to invalidate | |
1051 | entries regardless of the ASID. | |
475d92fc WD |
1052 | |
1053 | config ARM_ERRATA_743622 | |
1054 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1055 | depends on CPU_V7 | |
62e4d357 | 1056 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1057 | help |
1058 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1059 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1060 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1061 | corruption. This workaround sets a specific bit in the diagnostic | |
1062 | register of the Cortex-A9 which disables the Store Buffer | |
1063 | optimisation, preventing the defect from occurring. This has no | |
1064 | visible impact on the overall performance or power consumption of the | |
1065 | processor. | |
1066 | ||
9a27c27c WD |
1067 | config ARM_ERRATA_751472 |
1068 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1069 | depends on CPU_V7 |
62e4d357 | 1070 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1071 | help |
1072 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1073 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1074 | completion of a following broadcasted operation if the second | |
1075 | operation is received by a CPU before the ICIALLUIS has completed, | |
1076 | potentially leading to corrupted entries in the cache or TLB. | |
1077 | ||
fcbdc5fe WD |
1078 | config ARM_ERRATA_754322 |
1079 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1080 | depends on CPU_V7 | |
1081 | help | |
1082 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1083 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1084 | which starts prior to an ASID switch but completes afterwards. This | |
1085 | can populate the micro-TLB with a stale entry which may be hit with | |
1086 | the new ASID. This workaround places two dsb instructions in the mm | |
1087 | switching code so that no page table walks can cross the ASID switch. | |
1088 | ||
5dab26af WD |
1089 | config ARM_ERRATA_754327 |
1090 | bool "ARM errata: no automatic Store Buffer drain" | |
1091 | depends on CPU_V7 && SMP | |
1092 | help | |
1093 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1094 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1095 | mechanism and therefore a livelock may occur if an external agent | |
1096 | continuously polls a memory location waiting to observe an update. | |
1097 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1098 | written polling loops from denying visibility of updates to memory. | |
1099 | ||
145e10e1 CM |
1100 | config ARM_ERRATA_364296 |
1101 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1102 | depends on CPU_V6 |
145e10e1 CM |
1103 | help |
1104 | This options enables the workaround for the 364296 ARM1136 | |
1105 | r0p2 erratum (possible cache data corruption with | |
1106 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1107 | the auxiliary control register and the FI bit in the control | |
1108 | register, thus disabling hit-under-miss without putting the | |
1109 | processor into full low interrupt latency mode. ARM11MPCore | |
1110 | is not affected. | |
1111 | ||
f630c1bd WD |
1112 | config ARM_ERRATA_764369 |
1113 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1114 | depends on CPU_V7 && SMP | |
1115 | help | |
1116 | This option enables the workaround for erratum 764369 | |
1117 | affecting Cortex-A9 MPCore with two or more processors (all | |
1118 | current revisions). Under certain timing circumstances, a data | |
1119 | cache line maintenance operation by MVA targeting an Inner | |
1120 | Shareable memory region may fail to proceed up to either the | |
1121 | Point of Coherency or to the Point of Unification of the | |
1122 | system. This workaround adds a DSB instruction before the | |
1123 | relevant cache maintenance functions and sets a specific bit | |
1124 | in the diagnostic control register of the SCU. | |
1125 | ||
7253b85c SH |
1126 | config ARM_ERRATA_775420 |
1127 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1128 | depends on CPU_V7 | |
1129 | help | |
1130 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1131 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1132 | operation aborts with MMU exception, it might cause the processor | |
1133 | to deadlock. This workaround puts DSB before executing ISB if | |
1134 | an abort may occur on cache maintenance. | |
1135 | ||
93dc6887 CM |
1136 | config ARM_ERRATA_798181 |
1137 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1138 | depends on CPU_V7 && SMP | |
1139 | help | |
1140 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1141 | adequately shooting down all use of the old entries. This | |
1142 | option enables the Linux kernel workaround for this erratum | |
1143 | which sends an IPI to the CPUs that are running the same ASID | |
1144 | as the one being invalidated. | |
1145 | ||
84b6504f WD |
1146 | config ARM_ERRATA_773022 |
1147 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1148 | depends on CPU_V7 | |
1149 | help | |
1150 | This option enables the workaround for the 773022 Cortex-A15 | |
1151 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1152 | loop buffer may deliver incorrect instructions. This | |
1153 | workaround disables the loop buffer to avoid the erratum. | |
1154 | ||
62c0f4a5 DA |
1155 | config ARM_ERRATA_818325_852422 |
1156 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1157 | depends on CPU_V7 | |
1158 | help | |
1159 | This option enables the workaround for: | |
1160 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1161 | instruction might deadlock. Fixed in r0p1. | |
1162 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1163 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1164 | any Cortex-A12 cores yet. | |
1165 | This workaround for all both errata involves setting bit[12] of the | |
1166 | Feature Register. This bit disables an optimisation applied to a | |
1167 | sequence of 2 instructions that use opposing condition codes. | |
1168 | ||
416bcf21 DA |
1169 | config ARM_ERRATA_821420 |
1170 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1171 | depends on CPU_V7 | |
1172 | help | |
1173 | This option enables the workaround for the 821420 Cortex-A12 | |
1174 | (all revs) erratum. In very rare timing conditions, a sequence | |
1175 | of VMOV to Core registers instructions, for which the second | |
1176 | one is in the shadow of a branch or abort, can lead to a | |
1177 | deadlock when the VMOV instructions are issued out-of-order. | |
1178 | ||
9f6f9354 DA |
1179 | config ARM_ERRATA_825619 |
1180 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1181 | depends on CPU_V7 | |
1182 | help | |
1183 | This option enables the workaround for the 825619 Cortex-A12 | |
1184 | (all revs) erratum. Within rare timing constraints, executing a | |
1185 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1186 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1187 | ||
1188 | config ARM_ERRATA_852421 | |
1189 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1190 | depends on CPU_V7 | |
1191 | help | |
1192 | This option enables the workaround for the 852421 Cortex-A17 | |
1193 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1194 | execution of a DMB ST instruction might fail to properly order | |
1195 | stores from GroupA and stores from GroupB. | |
1196 | ||
62c0f4a5 DA |
1197 | config ARM_ERRATA_852423 |
1198 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1199 | depends on CPU_V7 | |
1200 | help | |
1201 | This option enables the workaround for: | |
1202 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1203 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1204 | any Cortex-A17 cores yet. | |
1205 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1206 | config option from the A12 erratum due to the way errata are checked | |
1207 | for and handled. | |
1208 | ||
1da177e4 LT |
1209 | endmenu |
1210 | ||
1211 | source "arch/arm/common/Kconfig" | |
1212 | ||
1da177e4 LT |
1213 | menu "Bus support" |
1214 | ||
1da177e4 LT |
1215 | config ISA |
1216 | bool | |
1da177e4 LT |
1217 | help |
1218 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1219 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1220 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1221 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1222 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1223 | ||
065909b9 | 1224 | # Select ISA DMA controller support |
1da177e4 LT |
1225 | config ISA_DMA |
1226 | bool | |
065909b9 | 1227 | select ISA_DMA_API |
1da177e4 | 1228 | |
065909b9 | 1229 | # Select ISA DMA interface |
5cae841b AV |
1230 | config ISA_DMA_API |
1231 | bool | |
5cae841b | 1232 | |
1da177e4 | 1233 | config PCI |
0b05da72 | 1234 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1235 | help |
1236 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1237 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1238 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1239 | VESA. If you have PCI, say Y, otherwise N. | |
1240 | ||
52882173 | 1241 | config PCI_DOMAINS |
925d3166 | 1242 | bool "Support for multiple PCI domains" |
52882173 | 1243 | depends on PCI |
925d3166 LP |
1244 | help |
1245 | Enable PCI domains kernel management. Say Y if your machine | |
1246 | has a PCI bus hierarchy that requires more than one PCI | |
1247 | domain (aka segment) to be correctly managed. Say N otherwise. | |
1248 | ||
1249 | If you don't know what to do here, say N. | |
52882173 | 1250 | |
8c7d1474 LP |
1251 | config PCI_DOMAINS_GENERIC |
1252 | def_bool PCI_DOMAINS | |
1253 | ||
b080ac8a MRJ |
1254 | config PCI_NANOENGINE |
1255 | bool "BSE nanoEngine PCI support" | |
1256 | depends on SA1100_NANOENGINE | |
1257 | help | |
1258 | Enable PCI on the BSE nanoEngine board. | |
1259 | ||
36e23590 MW |
1260 | config PCI_SYSCALL |
1261 | def_bool PCI | |
1262 | ||
a0113a99 MR |
1263 | config PCI_HOST_ITE8152 |
1264 | bool | |
1265 | depends on PCI && MACH_ARMCORE | |
1266 | default y | |
1267 | select DMABOUNCE | |
1268 | ||
1da177e4 LT |
1269 | source "drivers/pci/Kconfig" |
1270 | ||
1271 | source "drivers/pcmcia/Kconfig" | |
1272 | ||
1273 | endmenu | |
1274 | ||
1275 | menu "Kernel Features" | |
1276 | ||
3b55658a DM |
1277 | config HAVE_SMP |
1278 | bool | |
1279 | help | |
1280 | This option should be selected by machines which have an SMP- | |
1281 | capable CPU. | |
1282 | ||
1283 | The only effect of this option is to make the SMP-related | |
1284 | options available to the user for configuration. | |
1285 | ||
1da177e4 | 1286 | config SMP |
bb2d8130 | 1287 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1288 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1289 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1290 | depends on HAVE_SMP |
801bb21c | 1291 | depends on MMU || ARM_MPU |
0361748f | 1292 | select IRQ_WORK |
1da177e4 LT |
1293 | help |
1294 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1295 | a system with only one CPU, say N. If you have a system with more |
1296 | than one CPU, say Y. | |
1da177e4 | 1297 | |
4a474157 | 1298 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1299 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1300 | you say Y here, the kernel will run on many, but not all, |
1301 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1302 | will run faster if you say N here. | |
1da177e4 | 1303 | |
395cf969 | 1304 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
ecf38679 | 1305 | <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at |
50a23e6e | 1306 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1307 | |
1308 | If you don't know what to do here, say N. | |
1309 | ||
f00ec48f | 1310 | config SMP_ON_UP |
5744ff43 | 1311 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1312 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1313 | default y |
1314 | help | |
1315 | SMP kernels contain instructions which fail on non-SMP processors. | |
1316 | Enabling this option allows the kernel to modify itself to make | |
1317 | these instructions safe. Disabling it allows about 1K of space | |
1318 | savings. | |
1319 | ||
1320 | If you don't know what to do here, say Y. | |
1321 | ||
c9018aab VG |
1322 | config ARM_CPU_TOPOLOGY |
1323 | bool "Support cpu topology definition" | |
1324 | depends on SMP && CPU_V7 | |
1325 | default y | |
1326 | help | |
1327 | Support ARM cpu topology definition. The MPIDR register defines | |
1328 | affinity between processors which is then used to describe the cpu | |
1329 | topology of an ARM System. | |
1330 | ||
1331 | config SCHED_MC | |
1332 | bool "Multi-core scheduler support" | |
1333 | depends on ARM_CPU_TOPOLOGY | |
1334 | help | |
1335 | Multi-core scheduler support improves the CPU scheduler's decision | |
1336 | making when dealing with multi-core CPU chips at a cost of slightly | |
1337 | increased overhead in some places. If unsure say N here. | |
1338 | ||
1339 | config SCHED_SMT | |
1340 | bool "SMT scheduler support" | |
1341 | depends on ARM_CPU_TOPOLOGY | |
1342 | help | |
1343 | Improves the CPU scheduler's decision making when dealing with | |
1344 | MultiThreading at a cost of slightly increased overhead in some | |
1345 | places. If unsure say N here. | |
1346 | ||
a8cbcd92 RK |
1347 | config HAVE_ARM_SCU |
1348 | bool | |
a8cbcd92 RK |
1349 | help |
1350 | This option enables support for the ARM system coherency unit | |
1351 | ||
8a4da6e3 | 1352 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1353 | bool "Architected timer support" |
1354 | depends on CPU_V7 | |
8a4da6e3 | 1355 | select ARM_ARCH_TIMER |
0c403462 | 1356 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1357 | help |
1358 | This option enables support for the ARM architected timer | |
1359 | ||
f32f4ce2 RK |
1360 | config HAVE_ARM_TWD |
1361 | bool | |
bb0eb050 | 1362 | select TIMER_OF if OF |
f32f4ce2 RK |
1363 | help |
1364 | This options enables support for the ARM timer and watchdog unit | |
1365 | ||
e8db288e NP |
1366 | config MCPM |
1367 | bool "Multi-Cluster Power Management" | |
1368 | depends on CPU_V7 && SMP | |
1369 | help | |
1370 | This option provides the common power management infrastructure | |
1371 | for (multi-)cluster based systems, such as big.LITTLE based | |
1372 | systems. | |
1373 | ||
ebf4a5c5 HZ |
1374 | config MCPM_QUAD_CLUSTER |
1375 | bool | |
1376 | depends on MCPM | |
1377 | help | |
1378 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1379 | to 2 clusters by default. | |
1380 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1381 | option to allow the additional clusters to be managed. | |
1382 | ||
1c33be57 NP |
1383 | config BIG_LITTLE |
1384 | bool "big.LITTLE support (Experimental)" | |
1385 | depends on CPU_V7 && SMP | |
1386 | select MCPM | |
1387 | help | |
1388 | This option enables support selections for the big.LITTLE | |
1389 | system architecture. | |
1390 | ||
1391 | config BL_SWITCHER | |
1392 | bool "big.LITTLE switcher support" | |
6c044fec | 1393 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1394 | select CPU_PM |
1c33be57 NP |
1395 | help |
1396 | The big.LITTLE "switcher" provides the core functionality to | |
1397 | transparently handle transition between a cluster of A15's | |
1398 | and a cluster of A7's in a big.LITTLE system. | |
1399 | ||
b22537c6 NP |
1400 | config BL_SWITCHER_DUMMY_IF |
1401 | tristate "Simple big.LITTLE switcher user interface" | |
1402 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1403 | help | |
1404 | This is a simple and dummy char dev interface to control | |
1405 | the big.LITTLE switcher core code. It is meant for | |
1406 | debugging purposes only. | |
1407 | ||
8d5796d2 LB |
1408 | choice |
1409 | prompt "Memory split" | |
006fa259 | 1410 | depends on MMU |
8d5796d2 LB |
1411 | default VMSPLIT_3G |
1412 | help | |
1413 | Select the desired split between kernel and user memory. | |
1414 | ||
1415 | If you are not absolutely sure what you are doing, leave this | |
1416 | option alone! | |
1417 | ||
1418 | config VMSPLIT_3G | |
1419 | bool "3G/1G user/kernel split" | |
63ce446c | 1420 | config VMSPLIT_3G_OPT |
bbeedfda | 1421 | depends on !ARM_LPAE |
63ce446c | 1422 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1423 | config VMSPLIT_2G |
1424 | bool "2G/2G user/kernel split" | |
1425 | config VMSPLIT_1G | |
1426 | bool "1G/3G user/kernel split" | |
1427 | endchoice | |
1428 | ||
1429 | config PAGE_OFFSET | |
1430 | hex | |
006fa259 | 1431 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1432 | default 0x40000000 if VMSPLIT_1G |
1433 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1434 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1435 | default 0xC0000000 |
1436 | ||
1da177e4 LT |
1437 | config NR_CPUS |
1438 | int "Maximum number of CPUs (2-32)" | |
1439 | range 2 32 | |
1440 | depends on SMP | |
1441 | default "4" | |
1442 | ||
a054a811 | 1443 | config HOTPLUG_CPU |
00b7dede | 1444 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1445 | depends on SMP |
a054a811 RK |
1446 | help |
1447 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1448 | can be controlled through /sys/devices/system/cpu. | |
1449 | ||
2bdd424f WD |
1450 | config ARM_PSCI |
1451 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1452 | depends on HAVE_ARM_SMCCC |
be120397 | 1453 | select ARM_PSCI_FW |
2bdd424f WD |
1454 | help |
1455 | Say Y here if you want Linux to communicate with system firmware | |
1456 | implementing the PSCI specification for CPU-centric power | |
1457 | management operations described in ARM document number ARM DEN | |
1458 | 0022A ("Power State Coordination Interface System Software on | |
1459 | ARM processors"). | |
1460 | ||
2a6ad871 MR |
1461 | # The GPIO number here must be sorted by descending number. In case of |
1462 | # a multiplatform kernel, we just want the highest value required by the | |
1463 | # selected platforms. | |
44986ab0 PDSN |
1464 | config ARCH_NR_GPIO |
1465 | int | |
139358be | 1466 | default 2048 if ARCH_SOCFPGA |
d9be9ceb | 1467 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
b35d2e56 | 1468 | ARCH_ZYNQ |
aa42587a TF |
1469 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1470 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1471 | default 416 if ARCH_SUNXI |
06b851e5 | 1472 | default 392 if ARCH_U8500 |
01bb914c | 1473 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1474 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1475 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1476 | default 0 |
1477 | help | |
1478 | Maximum number of GPIOs in the system. | |
1479 | ||
1480 | If unsure, leave the default value. | |
1481 | ||
c9218b16 | 1482 | config HZ_FIXED |
f8065813 | 1483 | int |
da6b21e9 | 1484 | default 200 if ARCH_EBSA110 |
1164f672 | 1485 | default 128 if SOC_AT91RM9200 |
47d84682 | 1486 | default 0 |
c9218b16 RK |
1487 | |
1488 | choice | |
47d84682 | 1489 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1490 | prompt "Timer frequency" |
1491 | ||
1492 | config HZ_100 | |
1493 | bool "100 Hz" | |
1494 | ||
1495 | config HZ_200 | |
1496 | bool "200 Hz" | |
1497 | ||
1498 | config HZ_250 | |
1499 | bool "250 Hz" | |
1500 | ||
1501 | config HZ_300 | |
1502 | bool "300 Hz" | |
1503 | ||
1504 | config HZ_500 | |
1505 | bool "500 Hz" | |
1506 | ||
1507 | config HZ_1000 | |
1508 | bool "1000 Hz" | |
1509 | ||
1510 | endchoice | |
1511 | ||
1512 | config HZ | |
1513 | int | |
47d84682 | 1514 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1515 | default 100 if HZ_100 |
1516 | default 200 if HZ_200 | |
1517 | default 250 if HZ_250 | |
1518 | default 300 if HZ_300 | |
1519 | default 500 if HZ_500 | |
1520 | default 1000 | |
1521 | ||
1522 | config SCHED_HRTICK | |
1523 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1524 | |
16c79651 | 1525 | config THUMB2_KERNEL |
bc7dea00 | 1526 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1527 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1528 | default y if CPU_THUMBONLY |
89bace65 | 1529 | select ARM_UNWIND |
16c79651 CM |
1530 | help |
1531 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1532 | Thumb-2 mode. |
16c79651 CM |
1533 | |
1534 | If unsure, say N. | |
1535 | ||
6f685c5c DM |
1536 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1537 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1538 | depends on THUMB2_KERNEL && MODULES | |
1539 | default y | |
1540 | help | |
1541 | Various binutils versions can resolve Thumb-2 branches to | |
1542 | locally-defined, preemptible global symbols as short-range "b.n" | |
1543 | branch instructions. | |
1544 | ||
1545 | This is a problem, because there's no guarantee the final | |
1546 | destination of the symbol, or any candidate locations for a | |
1547 | trampoline, are within range of the branch. For this reason, the | |
1548 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1549 | relocation in modules at all, and it makes little sense to add | |
1550 | support. | |
1551 | ||
1552 | The symptom is that the kernel fails with an "unsupported | |
1553 | relocation" error when loading some modules. | |
1554 | ||
1555 | Until fixed tools are available, passing | |
1556 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1557 | code which hits this problem, at the cost of a bit of extra runtime | |
1558 | stack usage in some cases. | |
1559 | ||
1560 | The problem is described in more detail at: | |
1561 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1562 | ||
1563 | Only Thumb-2 kernels are affected. | |
1564 | ||
1565 | Unless you are sure your tools don't have this problem, say Y. | |
1566 | ||
42f25bdd NP |
1567 | config ARM_PATCH_IDIV |
1568 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1569 | depends on CPU_32v7 && !XIP_KERNEL | |
1570 | default y | |
1571 | help | |
1572 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1573 | __aeabi_uidiv() when it needs to perform division on signed | |
1574 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1575 | and udiv instructions that can be used to implement those | |
1576 | functions. | |
1577 | ||
1578 | Enabling this option allows the kernel to modify itself to | |
1579 | replace the first two instructions of these library functions | |
1580 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1581 | it is running on supports them. Typically this will be faster | |
1582 | and less power intensive than running the original library | |
1583 | code to do integer division. | |
1584 | ||
704bdda0 | 1585 | config AEABI |
49460970 RK |
1586 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K |
1587 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K | |
704bdda0 NP |
1588 | help |
1589 | This option allows for the kernel to be compiled using the latest | |
1590 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1591 | space environment that is also compiled with EABI. | |
1592 | ||
1593 | Since there are major incompatibilities between the legacy ABI and | |
1594 | EABI, especially with regard to structure member alignment, this | |
1595 | option also changes the kernel syscall calling convention to | |
1596 | disambiguate both ABIs and allow for backward compatibility support | |
1597 | (selected with CONFIG_OABI_COMPAT). | |
1598 | ||
1599 | To use this you need GCC version 4.0.0 or later. | |
1600 | ||
6c90c872 | 1601 | config OABI_COMPAT |
a73a3ff1 | 1602 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1603 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1604 | help |
1605 | This option preserves the old syscall interface along with the | |
1606 | new (ARM EABI) one. It also provides a compatibility layer to | |
1607 | intercept syscalls that have structure arguments which layout | |
1608 | in memory differs between the legacy ABI and the new ARM EABI | |
1609 | (only for non "thumb" binaries). This option adds a tiny | |
1610 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1611 | |
1612 | The seccomp filter system will not be available when this is | |
1613 | selected, since there is no way yet to sensibly distinguish | |
1614 | between calling conventions during filtering. | |
1615 | ||
6c90c872 NP |
1616 | If you know you'll be using only pure EABI user space then you |
1617 | can say N here. If this option is not selected and you attempt | |
1618 | to execute a legacy ABI binary then the result will be | |
1619 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1620 | at all). If in doubt say N. |
6c90c872 | 1621 | |
eb33575c | 1622 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1623 | bool |
e80d6a24 | 1624 | |
05944d74 RK |
1625 | config ARCH_SPARSEMEM_ENABLE |
1626 | bool | |
1627 | ||
07a2f737 RK |
1628 | config ARCH_SPARSEMEM_DEFAULT |
1629 | def_bool ARCH_SPARSEMEM_ENABLE | |
1630 | ||
05944d74 | 1631 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1632 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1633 | |
7b7bf499 WD |
1634 | config HAVE_ARCH_PFN_VALID |
1635 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1636 | ||
e585513b | 1637 | config HAVE_GENERIC_GUP |
b8cd51af SC |
1638 | def_bool y |
1639 | depends on ARM_LPAE | |
1640 | ||
053a96ca | 1641 | config HIGHMEM |
e8db89a2 RK |
1642 | bool "High Memory Support" |
1643 | depends on MMU | |
053a96ca NP |
1644 | help |
1645 | The address space of ARM processors is only 4 Gigabytes large | |
1646 | and it has to accommodate user address space, kernel address | |
1647 | space as well as some memory mapped IO. That means that, if you | |
1648 | have a large amount of physical memory and/or IO, not all of the | |
1649 | memory can be "permanently mapped" by the kernel. The physical | |
1650 | memory that is not permanently mapped is called "high memory". | |
1651 | ||
1652 | Depending on the selected kernel/user memory split, minimum | |
1653 | vmalloc space and actual amount of RAM, you may not need this | |
1654 | option which should result in a slightly faster kernel. | |
1655 | ||
1656 | If unsure, say n. | |
1657 | ||
65cec8e3 | 1658 | config HIGHPTE |
9a431bd5 | 1659 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1660 | depends on HIGHMEM |
9a431bd5 | 1661 | default y |
b4d103d1 RK |
1662 | help |
1663 | The VM uses one page of physical memory for each page table. | |
1664 | For systems with a lot of processes, this can use a lot of | |
1665 | precious low memory, eventually leading to low memory being | |
1666 | consumed by page tables. Setting this option will allow | |
1667 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1668 | |
a5e090ac RK |
1669 | config CPU_SW_DOMAIN_PAN |
1670 | bool "Enable use of CPU domains to implement privileged no-access" | |
1671 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1672 | default y |
1673 | help | |
a5e090ac RK |
1674 | Increase kernel security by ensuring that normal kernel accesses |
1675 | are unable to access userspace addresses. This can help prevent | |
1676 | use-after-free bugs becoming an exploitable privilege escalation | |
1677 | by ensuring that magic values (such as LIST_POISON) will always | |
1678 | fault when dereferenced. | |
1679 | ||
1680 | CPUs with low-vector mappings use a best-efforts implementation. | |
1681 | Their lower 1MB needs to remain accessible for the vectors, but | |
1682 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1683 | |
1b8873a0 | 1684 | config HW_PERF_EVENTS |
fa8ad788 MR |
1685 | def_bool y |
1686 | depends on ARM_PMU | |
1b8873a0 | 1687 | |
1355e2a6 CM |
1688 | config SYS_SUPPORTS_HUGETLBFS |
1689 | def_bool y | |
1690 | depends on ARM_LPAE | |
1691 | ||
8d962507 CM |
1692 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1693 | def_bool y | |
1694 | depends on ARM_LPAE | |
1695 | ||
4bfab203 SC |
1696 | config ARCH_WANT_GENERAL_HUGETLB |
1697 | def_bool y | |
1698 | ||
7d485f64 AB |
1699 | config ARM_MODULE_PLTS |
1700 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1701 | depends on MODULES | |
e7229f7d | 1702 | default y |
7d485f64 AB |
1703 | help |
1704 | Allocate PLTs when loading modules so that jumps and calls whose | |
1705 | targets are too far away for their relative offsets to be encoded | |
1706 | in the instructions themselves can be bounced via veneers in the | |
1707 | module's PLT. This allows modules to be allocated in the generic | |
1708 | vmalloc area after the dedicated module memory area has been | |
1709 | exhausted. The modules will use slightly more memory, but after | |
1710 | rounding up to page size, the actual memory footprint is usually | |
1711 | the same. | |
1712 | ||
e7229f7d AR |
1713 | Disabling this is usually safe for small single-platform |
1714 | configurations. If unsure, say y. | |
7d485f64 | 1715 | |
c1b2d970 | 1716 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1717 | int "Maximum zone order" |
898f08e1 | 1718 | default "12" if SOC_AM33XX |
6d85e2b0 | 1719 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1720 | default "11" |
1721 | help | |
1722 | The kernel memory allocator divides physically contiguous memory | |
1723 | blocks into "zones", where each zone is a power of two number of | |
1724 | pages. This option selects the largest power of two that the kernel | |
1725 | keeps in the memory allocator. If you need to allocate very large | |
1726 | blocks of physically contiguous memory, then you may need to | |
1727 | increase this value. | |
1728 | ||
1729 | This config option is actually maximum order plus one. For example, | |
1730 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1731 | ||
1da177e4 LT |
1732 | config ALIGNMENT_TRAP |
1733 | bool | |
f12d0d7c | 1734 | depends on CPU_CP15_MMU |
1da177e4 | 1735 | default y if !ARCH_EBSA110 |
e119bfff | 1736 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1737 | help |
84eb8d06 | 1738 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1739 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1740 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1741 | fetch/store instructions will be emulated in software if you say | |
1742 | here, which has a severe performance impact. This is necessary for | |
1743 | correct operation of some network protocols. With an IP-only | |
1744 | configuration it is safe to say N, otherwise say Y. | |
1745 | ||
39ec58f3 | 1746 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1747 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1748 | depends on MMU | |
39ec58f3 LB |
1749 | default y if CPU_FEROCEON |
1750 | help | |
1751 | Implement faster copy_to_user and clear_user methods for CPU | |
1752 | cores where a 8-word STM instruction give significantly higher | |
1753 | memory write throughput than a sequence of individual 32bit stores. | |
1754 | ||
1755 | A possible side effect is a slight increase in scheduling latency | |
1756 | between threads sharing the same address space if they invoke | |
1757 | such copy operations with large buffers. | |
1758 | ||
1759 | However, if the CPU data cache is using a write-allocate mode, | |
1760 | this option is unlikely to provide any performance gain. | |
1761 | ||
70c70d97 NP |
1762 | config SECCOMP |
1763 | bool | |
1764 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1765 | ---help--- | |
1766 | This kernel feature is useful for number crunching applications | |
1767 | that may need to compute untrusted bytecode during their | |
1768 | execution. By using pipes or other transports made available to | |
1769 | the process as file descriptors supporting the read/write | |
1770 | syscalls, it's possible to isolate those applications in | |
1771 | their own address space using seccomp. Once seccomp is | |
1772 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1773 | and the task is only allowed to execute a few safe syscalls | |
1774 | defined by each seccomp mode. | |
1775 | ||
02c2433b SS |
1776 | config PARAVIRT |
1777 | bool "Enable paravirtualization code" | |
1778 | help | |
1779 | This changes the kernel so it can modify itself when it is run | |
1780 | under a hypervisor, potentially improving performance significantly | |
1781 | over full virtualization. | |
1782 | ||
1783 | config PARAVIRT_TIME_ACCOUNTING | |
1784 | bool "Paravirtual steal time accounting" | |
1785 | select PARAVIRT | |
1786 | default n | |
1787 | help | |
1788 | Select this option to enable fine granularity task steal time | |
1789 | accounting. Time spent executing other tasks in parallel with | |
1790 | the current vCPU is discounted from the vCPU power. To account for | |
1791 | that, there can be a small performance impact. | |
1792 | ||
1793 | If in doubt, say N here. | |
1794 | ||
eff8d644 SS |
1795 | config XEN_DOM0 |
1796 | def_bool y | |
1797 | depends on XEN | |
1798 | ||
1799 | config XEN | |
c2ba1f7d | 1800 | bool "Xen guest support on ARM" |
85323a99 | 1801 | depends on ARM && AEABI && OF |
f880b67d | 1802 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1803 | depends on !GENERIC_ATOMIC64 |
7693decc | 1804 | depends on MMU |
51aaf81f | 1805 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1806 | select ARM_PSCI |
f21254cd | 1807 | select SWIOTLB |
83862ccf | 1808 | select SWIOTLB_XEN |
02c2433b | 1809 | select PARAVIRT |
eff8d644 SS |
1810 | help |
1811 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1812 | ||
189af465 AB |
1813 | config STACKPROTECTOR_PER_TASK |
1814 | bool "Use a unique stack canary value for each task" | |
1815 | depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA | |
1816 | select GCC_PLUGIN_ARM_SSP_PER_TASK | |
1817 | default y | |
1818 | help | |
1819 | Due to the fact that GCC uses an ordinary symbol reference from | |
1820 | which to load the value of the stack canary, this value can only | |
1821 | change at reboot time on SMP systems, and all tasks running in the | |
1822 | kernel's address space are forced to use the same canary value for | |
1823 | the entire duration that the system is up. | |
1824 | ||
1825 | Enable this option to switch to a different method that uses a | |
1826 | different canary value for each task. | |
1827 | ||
1da177e4 LT |
1828 | endmenu |
1829 | ||
1830 | menu "Boot options" | |
1831 | ||
9eb8f674 GL |
1832 | config USE_OF |
1833 | bool "Flattened Device Tree support" | |
b1b3f49c | 1834 | select IRQ_DOMAIN |
9eb8f674 | 1835 | select OF |
9eb8f674 GL |
1836 | help |
1837 | Include support for flattened device tree machine descriptions. | |
1838 | ||
bd51e2f5 NP |
1839 | config ATAGS |
1840 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1841 | default y | |
1842 | help | |
1843 | This is the traditional way of passing data to the kernel at boot | |
1844 | time. If you are solely relying on the flattened device tree (or | |
1845 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1846 | to remove ATAGS support from your kernel binary. If unsure, | |
1847 | leave this to y. | |
1848 | ||
1849 | config DEPRECATED_PARAM_STRUCT | |
1850 | bool "Provide old way to pass kernel parameters" | |
1851 | depends on ATAGS | |
1852 | help | |
1853 | This was deprecated in 2001 and announced to live on for 5 years. | |
1854 | Some old boot loaders still use this way. | |
1855 | ||
1da177e4 LT |
1856 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1857 | # TEXT and BSS so we preserve their values in the config files. | |
1858 | config ZBOOT_ROM_TEXT | |
1859 | hex "Compressed ROM boot loader base address" | |
1860 | default "0" | |
1861 | help | |
1862 | The physical address at which the ROM-able zImage is to be | |
1863 | placed in the target. Platforms which normally make use of | |
1864 | ROM-able zImage formats normally set this to a suitable | |
1865 | value in their defconfig file. | |
1866 | ||
1867 | If ZBOOT_ROM is not enabled, this has no effect. | |
1868 | ||
1869 | config ZBOOT_ROM_BSS | |
1870 | hex "Compressed ROM boot loader BSS address" | |
1871 | default "0" | |
1872 | help | |
f8c440b2 DF |
1873 | The base address of an area of read/write memory in the target |
1874 | for the ROM-able zImage which must be available while the | |
1875 | decompressor is running. It must be large enough to hold the | |
1876 | entire decompressed kernel plus an additional 128 KiB. | |
1877 | Platforms which normally make use of ROM-able zImage formats | |
1878 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1879 | |
1880 | If ZBOOT_ROM is not enabled, this has no effect. | |
1881 | ||
1882 | config ZBOOT_ROM | |
1883 | bool "Compressed boot loader in ROM/flash" | |
1884 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1885 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1886 | help |
1887 | Say Y here if you intend to execute your compressed kernel image | |
1888 | (zImage) directly from ROM or flash. If unsure, say N. | |
1889 | ||
e2a6a3aa JB |
1890 | config ARM_APPENDED_DTB |
1891 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1892 | depends on OF |
e2a6a3aa JB |
1893 | help |
1894 | With this option, the boot code will look for a device tree binary | |
1895 | (DTB) appended to zImage | |
1896 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1897 | ||
1898 | This is meant as a backward compatibility convenience for those | |
1899 | systems with a bootloader that can't be upgraded to accommodate | |
1900 | the documented boot protocol using a device tree. | |
1901 | ||
1902 | Beware that there is very little in terms of protection against | |
1903 | this option being confused by leftover garbage in memory that might | |
1904 | look like a DTB header after a reboot if no actual DTB is appended | |
1905 | to zImage. Do not leave this option active in a production kernel | |
1906 | if you don't intend to always append a DTB. Proper passing of the | |
1907 | location into r2 of a bootloader provided DTB is always preferable | |
1908 | to this option. | |
1909 | ||
b90b9a38 NP |
1910 | config ARM_ATAG_DTB_COMPAT |
1911 | bool "Supplement the appended DTB with traditional ATAG information" | |
1912 | depends on ARM_APPENDED_DTB | |
1913 | help | |
1914 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1915 | they provide ATAGs with memory configuration, the ramdisk address, | |
1916 | the kernel cmdline string, etc. Such information is dynamically | |
1917 | provided by the bootloader and can't always be stored in a static | |
1918 | DTB. To allow a device tree enabled kernel to be used with such | |
1919 | bootloaders, this option allows zImage to extract the information | |
1920 | from the ATAG list and store it at run time into the appended DTB. | |
1921 | ||
d0f34a11 GR |
1922 | choice |
1923 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1924 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1925 | ||
1926 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1927 | bool "Use bootloader kernel arguments if available" | |
1928 | help | |
1929 | Uses the command-line options passed by the boot loader instead of | |
1930 | the device tree bootargs property. If the boot loader doesn't provide | |
1931 | any, the device tree bootargs property will be used. | |
1932 | ||
1933 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1934 | bool "Extend with bootloader kernel arguments" | |
1935 | help | |
1936 | The command-line arguments provided by the boot loader will be | |
1937 | appended to the the device tree bootargs property. | |
1938 | ||
1939 | endchoice | |
1940 | ||
1da177e4 LT |
1941 | config CMDLINE |
1942 | string "Default kernel command string" | |
1943 | default "" | |
1944 | help | |
1945 | On some architectures (EBSA110 and CATS), there is currently no way | |
1946 | for the boot loader to pass arguments to the kernel. For these | |
1947 | architectures, you should supply some command-line options at build | |
1948 | time by entering them here. As a minimum, you should specify the | |
1949 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1950 | ||
4394c124 VB |
1951 | choice |
1952 | prompt "Kernel command line type" if CMDLINE != "" | |
1953 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1954 | depends on ATAGS |
4394c124 VB |
1955 | |
1956 | config CMDLINE_FROM_BOOTLOADER | |
1957 | bool "Use bootloader kernel arguments if available" | |
1958 | help | |
1959 | Uses the command-line options passed by the boot loader. If | |
1960 | the boot loader doesn't provide any, the default kernel command | |
1961 | string provided in CMDLINE will be used. | |
1962 | ||
1963 | config CMDLINE_EXTEND | |
1964 | bool "Extend bootloader kernel arguments" | |
1965 | help | |
1966 | The command-line arguments provided by the boot loader will be | |
1967 | appended to the default kernel command string. | |
1968 | ||
92d2040d AH |
1969 | config CMDLINE_FORCE |
1970 | bool "Always use the default kernel command string" | |
92d2040d AH |
1971 | help |
1972 | Always use the default kernel command string, even if the boot | |
1973 | loader passes other arguments to the kernel. | |
1974 | This is useful if you cannot or don't want to change the | |
1975 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1976 | endchoice |
92d2040d | 1977 | |
1da177e4 LT |
1978 | config XIP_KERNEL |
1979 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1980 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1981 | help |
1982 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1983 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1984 | space since the text section of the kernel is not loaded from flash | |
1985 | to RAM. Read-write sections, such as the data section and stack, | |
1986 | are still copied to RAM. The XIP kernel is not compressed since | |
1987 | it has to run directly from flash, so it will take more space to | |
1988 | store it. The flash address used to link the kernel object files, | |
1989 | and for storing it, is configuration dependent. Therefore, if you | |
1990 | say Y here, you must know the proper physical address where to | |
1991 | store the kernel image depending on your own flash memory usage. | |
1992 | ||
1993 | Also note that the make target becomes "make xipImage" rather than | |
1994 | "make zImage" or "make Image". The final kernel binary to put in | |
1995 | ROM memory will be arch/arm/boot/xipImage. | |
1996 | ||
1997 | If unsure, say N. | |
1998 | ||
1999 | config XIP_PHYS_ADDR | |
2000 | hex "XIP Kernel Physical Location" | |
2001 | depends on XIP_KERNEL | |
2002 | default "0x00080000" | |
2003 | help | |
2004 | This is the physical address in your flash memory the kernel will | |
2005 | be linked for and stored to. This address is dependent on your | |
2006 | own flash usage. | |
2007 | ||
ca8b5d97 NP |
2008 | config XIP_DEFLATED_DATA |
2009 | bool "Store kernel .data section compressed in ROM" | |
2010 | depends on XIP_KERNEL | |
2011 | select ZLIB_INFLATE | |
2012 | help | |
2013 | Before the kernel is actually executed, its .data section has to be | |
2014 | copied to RAM from ROM. This option allows for storing that data | |
2015 | in compressed form and decompressed to RAM rather than merely being | |
2016 | copied, saving some precious ROM space. A possible drawback is a | |
2017 | slightly longer boot delay. | |
2018 | ||
c587e4a6 RP |
2019 | config KEXEC |
2020 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2021 | depends on (!SMP || PM_SLEEP_SMP) |
cb1293e2 | 2022 | depends on !CPU_V7M |
2965faa5 | 2023 | select KEXEC_CORE |
c587e4a6 RP |
2024 | help |
2025 | kexec is a system call that implements the ability to shutdown your | |
2026 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2027 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2028 | you can start any kernel with it, not just Linux. |
2029 | ||
2030 | It is an ongoing process to be certain the hardware in a machine | |
2031 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 2032 | initially work for you. |
c587e4a6 | 2033 | |
4cd9d6f7 RP |
2034 | config ATAGS_PROC |
2035 | bool "Export atags in procfs" | |
bd51e2f5 | 2036 | depends on ATAGS && KEXEC |
b98d7291 | 2037 | default y |
4cd9d6f7 RP |
2038 | help |
2039 | Should the atags used to boot the kernel be exported in an "atags" | |
2040 | file in procfs. Useful with kexec. | |
2041 | ||
cb5d39b3 MW |
2042 | config CRASH_DUMP |
2043 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2044 | help |
2045 | Generate crash dump after being started by kexec. This should | |
2046 | be normally only set in special crash dump kernels which are | |
2047 | loaded in the main kernel with kexec-tools into a specially | |
2048 | reserved region and then later executed after a crash by | |
2049 | kdump/kexec. The crash dump kernel must be compiled to a | |
2050 | memory address not used by the main kernel | |
2051 | ||
2052 | For more details see Documentation/kdump/kdump.txt | |
2053 | ||
e69edc79 EM |
2054 | config AUTO_ZRELADDR |
2055 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2056 | help |
2057 | ZRELADDR is the physical address where the decompressed kernel | |
2058 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2059 | will be determined at run-time by masking the current IP with | |
2060 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2061 | from start of memory. | |
2062 | ||
81a0bc39 RF |
2063 | config EFI_STUB |
2064 | bool | |
2065 | ||
2066 | config EFI | |
2067 | bool "UEFI runtime support" | |
2068 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
2069 | select UCS2_STRING | |
2070 | select EFI_PARAMS_FROM_FDT | |
2071 | select EFI_STUB | |
2072 | select EFI_ARMSTUB | |
2073 | select EFI_RUNTIME_WRAPPERS | |
2074 | ---help--- | |
2075 | This option provides support for runtime services provided | |
2076 | by UEFI firmware (such as non-volatile variables, realtime | |
2077 | clock, and platform reset). A UEFI stub is also provided to | |
2078 | allow the kernel to be booted as an EFI application. This | |
2079 | is only useful for kernels that may run on systems that have | |
2080 | UEFI firmware. | |
2081 | ||
bb817bef AB |
2082 | config DMI |
2083 | bool "Enable support for SMBIOS (DMI) tables" | |
2084 | depends on EFI | |
2085 | default y | |
2086 | help | |
2087 | This enables SMBIOS/DMI feature for systems. | |
2088 | ||
2089 | This option is only useful on systems that have UEFI firmware. | |
2090 | However, even with this option, the resultant kernel should | |
2091 | continue to boot on existing non-UEFI platforms. | |
2092 | ||
2093 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
2094 | i.e., the the practice of identifying the platform via DMI to | |
2095 | decide whether certain workarounds for buggy hardware and/or | |
2096 | firmware need to be enabled. This would require the DMI subsystem | |
2097 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
2098 | ||
1da177e4 LT |
2099 | endmenu |
2100 | ||
ac9d7efc | 2101 | menu "CPU Power Management" |
1da177e4 | 2102 | |
1da177e4 | 2103 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2104 | |
ac9d7efc RK |
2105 | source "drivers/cpuidle/Kconfig" |
2106 | ||
2107 | endmenu | |
2108 | ||
1da177e4 LT |
2109 | menu "Floating point emulation" |
2110 | ||
2111 | comment "At least one emulation must be selected" | |
2112 | ||
2113 | config FPE_NWFPE | |
2114 | bool "NWFPE math emulation" | |
593c252a | 2115 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2116 | ---help--- |
2117 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2118 | This is necessary to run most binaries. Linux does not currently | |
2119 | support floating point hardware so you need to say Y here even if | |
2120 | your machine has an FPA or floating point co-processor podule. | |
2121 | ||
2122 | You may say N here if you are going to load the Acorn FPEmulator | |
2123 | early in the bootup. | |
2124 | ||
2125 | config FPE_NWFPE_XP | |
2126 | bool "Support extended precision" | |
bedf142b | 2127 | depends on FPE_NWFPE |
1da177e4 LT |
2128 | help |
2129 | Say Y to include 80-bit support in the kernel floating-point | |
2130 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2131 | Note that gcc does not generate 80-bit operations by default, | |
2132 | so in most cases this option only enlarges the size of the | |
2133 | floating point emulator without any good reason. | |
2134 | ||
2135 | You almost surely want to say N here. | |
2136 | ||
2137 | config FPE_FASTFPE | |
2138 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2139 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2140 | ---help--- |
2141 | Say Y here to include the FAST floating point emulator in the kernel. | |
2142 | This is an experimental much faster emulator which now also has full | |
2143 | precision for the mantissa. It does not support any exceptions. | |
2144 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2145 | ||
2146 | It should be sufficient for most programs. It may be not suitable | |
2147 | for scientific calculations, but you have to check this for yourself. | |
2148 | If you do not feel you need a faster FP emulation you should better | |
2149 | choose NWFPE. | |
2150 | ||
2151 | config VFP | |
2152 | bool "VFP-format floating point maths" | |
e399b1a4 | 2153 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2154 | help |
2155 | Say Y to include VFP support code in the kernel. This is needed | |
2156 | if your hardware includes a VFP unit. | |
2157 | ||
2158 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2159 | release notes and additional status information. | |
2160 | ||
2161 | Say N if your target does not have VFP hardware. | |
2162 | ||
25ebee02 CM |
2163 | config VFPv3 |
2164 | bool | |
2165 | depends on VFP | |
2166 | default y if CPU_V7 | |
2167 | ||
b5872db4 CM |
2168 | config NEON |
2169 | bool "Advanced SIMD (NEON) Extension support" | |
2170 | depends on VFPv3 && CPU_V7 | |
2171 | help | |
2172 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2173 | Extension. | |
2174 | ||
73c132c1 AB |
2175 | config KERNEL_MODE_NEON |
2176 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2177 | depends on NEON && AEABI |
73c132c1 AB |
2178 | help |
2179 | Say Y to include support for NEON in kernel mode. | |
2180 | ||
1da177e4 LT |
2181 | endmenu |
2182 | ||
1da177e4 LT |
2183 | menu "Power management options" |
2184 | ||
eceab4ac | 2185 | source "kernel/power/Kconfig" |
1da177e4 | 2186 | |
f4cb5700 | 2187 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2188 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2189 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2190 | def_bool y |
2191 | ||
15e0d9e3 | 2192 | config ARM_CPU_SUSPEND |
8b6f2499 | 2193 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 2194 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 2195 | |
603fb42a SC |
2196 | config ARCH_HIBERNATION_POSSIBLE |
2197 | bool | |
2198 | depends on MMU | |
2199 | default y if ARCH_SUSPEND_POSSIBLE | |
2200 | ||
1da177e4 LT |
2201 | endmenu |
2202 | ||
916f743d KG |
2203 | source "drivers/firmware/Kconfig" |
2204 | ||
652ccae5 AB |
2205 | if CRYPTO |
2206 | source "arch/arm/crypto/Kconfig" | |
2207 | endif | |
1da177e4 | 2208 | |
749cf76c | 2209 | source "arch/arm/kvm/Kconfig" |