Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
fed240d9 | 6 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND |
aef0f78e | 7 | select ARCH_HAS_BINFMT_FLAT |
8690bbcf | 8 | select ARCH_HAS_CPU_CACHE_ALIASING |
ee31bb05 | 9 | select ARCH_HAS_CPU_FINALIZE_INIT if MMU |
2792d84e | 10 | select ARCH_HAS_CURRENT_STACK_POINTER |
c7780ab5 | 11 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
2c8ed1b9 | 12 | select ARCH_HAS_DMA_ALLOC if MMU |
419e2f18 | 13 | select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE |
2b68f6ca | 14 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 15 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 16 | select ARCH_HAS_KEEPINITRD |
75851720 | 17 | select ARCH_HAS_KCOV |
e69244d2 | 18 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 19 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
3010a5ea | 20 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
347cb6af | 21 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 22 | select ARCH_HAS_SET_MEMORY |
9fbed16c | 23 | select ARCH_STACKWALK |
ad21fc4f LA |
24 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
25 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
ae626eb9 CH |
26 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
27 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
dc2acded | 28 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 29 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
9aaf9bb7 | 30 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K |
957e3fac | 31 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e545df3 | 32 | select ARCH_KEEP_MEMBLOCK |
918327e9 | 33 | select ARCH_HAS_UBSAN |
d7018848 | 34 | select ARCH_MIGHT_HAVE_PC_PARPORT |
ad21fc4f LA |
35 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
36 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 37 | select ARCH_SUPPORTS_ATOMIC_RMW |
855f9a8e | 38 | select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE |
c16af121 | 39 | select ARCH_SUPPORTS_PER_VMA_LOCK |
017f161a | 40 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 41 | select ARCH_USE_CMPXCHG_LOCKREF |
dce44566 | 42 | select ARCH_USE_MEMTEST |
dba79c3d | 43 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU |
07431506 | 44 | select ARCH_WANT_GENERAL_HUGETLB |
b1b3f49c | 45 | select ARCH_WANT_IPC_PARSE_VERSION |
59612b24 | 46 | select ARCH_WANT_LD_ORPHAN_WARN |
bdd15a28 | 47 | select BINFMT_FLAT_ARGVP_ENVP_ON_STACK |
10916706 | 48 | select BUILDTIME_TABLE_SORT if MMU |
6fd09c9a | 49 | select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) |
171b3f0d | 50 | select CLONE_BACKWARDS |
f00790aa | 51 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 52 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 53 | select DMA_DECLARE_COHERENT |
31b089bb | 54 | select DMA_GLOBAL_POOL if !MMU |
2f9237d4 | 55 | select DMA_OPS |
f5ff79fd | 56 | select DMA_NONCOHERENT_MMAP if MMU |
b01aec9b BP |
57 | select EDAC_SUPPORT |
58 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 59 | select GENERIC_ALLOCATOR |
2ef7a295 | 60 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 61 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 62 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
56afcd3d | 63 | select GENERIC_IRQ_IPI if SMP |
ea2d9a96 | 64 | select GENERIC_CPU_AUTOPROBE |
2937367b | 65 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 66 | select GENERIC_IDLE_POLL_SETUP |
234a0f20 | 67 | select GENERIC_IRQ_MULTI_HANDLER |
b1b3f49c RK |
68 | select GENERIC_IRQ_PROBE |
69 | select GENERIC_IRQ_SHOW | |
7c07005e | 70 | select GENERIC_IRQ_SHOW_LEVEL |
914ee966 | 71 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
b1b3f49c | 72 | select GENERIC_PCI_IOMAP |
38ff87f7 | 73 | select GENERIC_SCHED_CLOCK |
b1b3f49c | 74 | select GENERIC_SMP_IDLE_THREAD |
b1b3f49c | 75 | select HARDIRQS_SW_RESEND |
fcbfe812 | 76 | select HAS_IOPORT |
f00790aa | 77 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 78 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee | 79 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
75969686 | 80 | select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL |
437682ee | 81 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU |
42101571 | 82 | select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL |
565cbaad | 83 | select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN |
e0c25d95 | 84 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
4f5b0c17 | 85 | select HAVE_ARCH_PFN_VALID |
282a181b | 86 | select HAVE_ARCH_SECCOMP |
f00790aa | 87 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 88 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 89 | select HAVE_ARCH_TRACEHOOK |
e8003bf6 | 90 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE |
b329f95d | 91 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 92 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
24a9c541 | 93 | select HAVE_CONTEXT_TRACKING_USER |
b1b3f49c | 94 | select HAVE_C_RECORDMCOUNT |
4ed308c4 | 95 | select HAVE_BUILDTIME_MCOUNT_SORT |
bc420c6c | 96 | select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL |
b1b3f49c | 97 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 98 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 99 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 100 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 101 | select HAVE_EXIT_THREAD |
67a929e0 | 102 | select HAVE_FAST_GUP if ARM_LPAE |
f00790aa | 103 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
aaa4dd1b | 104 | select HAVE_FUNCTION_ERROR_INJECTION |
41918ec8 | 105 | select HAVE_FUNCTION_GRAPH_TRACER |
d6800ca7 | 106 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 107 | select HAVE_GCC_PLUGINS |
f00790aa | 108 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
87c46b6c | 109 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 110 | select HAVE_KERNEL_GZIP |
f9b493ac | 111 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 112 | select HAVE_KERNEL_LZMA |
b1b3f49c | 113 | select HAVE_KERNEL_LZO |
a7f464f3 | 114 | select HAVE_KERNEL_XZ |
cb1293e2 | 115 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 116 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 117 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 118 | select HAVE_NMI |
0dc016db | 119 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
5394f1e9 | 120 | select HAVE_PAGE_SIZE_4KB |
47723de8 | 121 | select HAVE_PCI if MMU |
7ada189f | 122 | select HAVE_PERF_EVENTS |
49863894 WD |
123 | select HAVE_PERF_REGS |
124 | select HAVE_PERF_USER_STACK_DUMP | |
ff2e6d72 | 125 | select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 126 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 127 | select HAVE_RSEQ |
d148eac0 | 128 | select HAVE_STACKPROTECTOR |
b1b3f49c | 129 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 130 | select HAVE_UID16 |
31c1fc81 | 131 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
5490e769 | 132 | select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU |
da0ec6f7 | 133 | select IRQ_FORCED_THREADING |
8b35ca3e | 134 | select LOCK_MM_AND_FIND_VMA |
171b3f0d | 135 | select MODULES_USE_ELF_REL |
f616ab59 | 136 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 137 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
138 | select OLD_SIGACTION |
139 | select OLD_SIGSUSPEND3 | |
6fd09c9a | 140 | select PCI_DOMAINS_GENERIC if PCI |
20f1b79d | 141 | select PCI_SYSCALL if PCI |
b1b3f49c RK |
142 | select PERF_USE_VMALLOC |
143 | select RTC_LIB | |
6fd09c9a | 144 | select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) |
b1b3f49c | 145 | select SYS_SUPPORTS_APM_EMULATION |
9c46929e | 146 | select THREAD_INFO_IN_TASK |
6fd09c9a | 147 | select TIMER_OF if OF |
d6905849 | 148 | select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS |
4aae683f | 149 | select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M |
6fd09c9a | 150 | select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) |
171b3f0d RK |
151 | # Above selects are sorted alphabetically; please add new ones |
152 | # according to that. Thanks. | |
1da177e4 LT |
153 | help |
154 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 155 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 156 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 157 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
158 | Europe. There is an ARM Linux project with a web page at |
159 | <http://www.arm.linux.org.uk/>. | |
160 | ||
d6905849 AB |
161 | config ARM_HAS_GROUP_RELOCS |
162 | def_bool y | |
163 | depends on !LD_IS_LLD || LLD_VERSION >= 140000 | |
164 | depends on !COMPILE_TEST | |
165 | help | |
166 | Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group | |
167 | relocations, which have been around for a long time, but were not | |
168 | supported in LLD until version 14. The combined range is -/+ 256 MiB, | |
169 | which is usually sufficient, but not for allyesconfig, so we disable | |
170 | this feature when doing compile testing. | |
171 | ||
4ce63fcd | 172 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 173 | bool |
b1b3f49c | 174 | select NEED_SG_DMA_LENGTH |
4ce63fcd | 175 | |
60460abf SWK |
176 | if ARM_DMA_USE_IOMMU |
177 | ||
178 | config ARM_DMA_IOMMU_ALIGNMENT | |
179 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
180 | range 4 9 | |
181 | default 8 | |
182 | help | |
183 | DMA mapping framework by default aligns all buffers to the smallest | |
184 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
185 | size. This works well for buffers up to a few hundreds kilobytes, but | |
186 | for larger buffers it just a waste of address space. Drivers which has | |
187 | relatively small addressing window (like 64Mib) might run out of | |
188 | virtual space with just a few allocations. | |
189 | ||
190 | With this parameter you can specify the maximum PAGE_SIZE order for | |
191 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
192 | specified order. The order is expressed as a power of two multiplied | |
193 | by the PAGE_SIZE. | |
194 | ||
195 | endif | |
196 | ||
75e7153a RB |
197 | config SYS_SUPPORTS_APM_EMULATION |
198 | bool | |
199 | ||
bc581770 LW |
200 | config HAVE_TCM |
201 | bool | |
202 | select GENERIC_ALLOCATOR | |
203 | ||
e119bfff RK |
204 | config HAVE_PROC_CPU |
205 | bool | |
206 | ||
ce816fa8 | 207 | config NO_IOPORT_MAP |
5ea81769 | 208 | bool |
5ea81769 | 209 | |
1da177e4 LT |
210 | config SBUS |
211 | bool | |
212 | ||
f16fb1ec RK |
213 | config STACKTRACE_SUPPORT |
214 | bool | |
215 | default y | |
216 | ||
217 | config LOCKDEP_SUPPORT | |
218 | bool | |
219 | default y | |
220 | ||
f0d1b0b3 DH |
221 | config ARCH_HAS_ILOG2_U32 |
222 | bool | |
f0d1b0b3 DH |
223 | |
224 | config ARCH_HAS_ILOG2_U64 | |
225 | bool | |
f0d1b0b3 | 226 | |
4a1b5733 EV |
227 | config ARCH_HAS_BANDGAP |
228 | bool | |
229 | ||
a5f4c561 SA |
230 | config FIX_EARLYCON_MEM |
231 | def_bool y if MMU | |
232 | ||
b89c3b16 AM |
233 | config GENERIC_HWEIGHT |
234 | bool | |
235 | default y | |
236 | ||
1da177e4 LT |
237 | config GENERIC_CALIBRATE_DELAY |
238 | bool | |
239 | default y | |
240 | ||
a08b6b79 Z |
241 | config ARCH_MAY_HAVE_PC_FDC |
242 | bool | |
243 | ||
c7edc9e3 DL |
244 | config ARCH_SUPPORTS_UPROBES |
245 | def_bool y | |
246 | ||
1da177e4 LT |
247 | config GENERIC_ISA_DMA |
248 | bool | |
249 | ||
1da177e4 LT |
250 | config FIQ |
251 | bool | |
252 | ||
034d2f5a AV |
253 | config ARCH_MTD_XIP |
254 | bool | |
255 | ||
dc21af99 | 256 | config ARM_PATCH_PHYS_VIRT |
ef815d2c | 257 | bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM |
c1becedc | 258 | default y |
5408445b | 259 | depends on MMU |
dc21af99 | 260 | help |
111e9a5c RK |
261 | Patch phys-to-virt and virt-to-phys translation functions at |
262 | boot and module load time according to the position of the | |
263 | kernel in system memory. | |
dc21af99 | 264 | |
111e9a5c | 265 | This can only be used with non-XIP MMU kernels where the base |
9443076e | 266 | of physical memory is at a 2 MiB boundary. |
dc21af99 | 267 | |
c1becedc RK |
268 | Only disable this option if you know that you do not require |
269 | this feature (eg, building a kernel for a single machine) and | |
270 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 271 | |
c334bc15 RH |
272 | config NEED_MACH_IO_H |
273 | bool | |
274 | help | |
275 | Select this when mach/io.h is required to provide special | |
276 | definitions for this platform. The need for mach/io.h should | |
277 | be avoided when possible. | |
278 | ||
0cdc8b92 | 279 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
280 | bool |
281 | help | |
0cdc8b92 NP |
282 | Select this when mach/memory.h is required to provide special |
283 | definitions for this platform. The need for mach/memory.h should | |
284 | be avoided when possible. | |
dc21af99 | 285 | |
1b9f95f8 | 286 | config PHYS_OFFSET |
974c0724 | 287 | hex "Physical address of main memory" if MMU |
92481c7d | 288 | depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR |
974c0724 | 289 | default DRAM_BASE if !MMU |
06954b6a | 290 | default 0x00000000 if ARCH_FOOTBRIDGE |
c6f54a9b | 291 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
b91a69d1 | 292 | default 0xa0000000 if ARCH_PXA |
c6e77bb6 AB |
293 | default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 |
294 | default 0 | |
111e9a5c | 295 | help |
1b9f95f8 NP |
296 | Please provide the physical address corresponding to the |
297 | location of main memory in your system. | |
cada3c08 | 298 | |
87e040b6 SG |
299 | config GENERIC_BUG |
300 | def_bool y | |
301 | depends on BUG | |
302 | ||
1bcad26e KS |
303 | config PGTABLE_LEVELS |
304 | int | |
305 | default 3 if ARM_LPAE | |
306 | default 2 | |
307 | ||
1da177e4 LT |
308 | menu "System Type" |
309 | ||
3c427975 HC |
310 | config MMU |
311 | bool "MMU-based Paged Memory Management Support" | |
312 | default y | |
313 | help | |
314 | Select if you want MMU-based virtualised addressing space | |
315 | support by paged memory management. If unsure, say 'Y'. | |
316 | ||
2f618d5e AB |
317 | config ARM_SINGLE_ARMV7M |
318 | def_bool !MMU | |
319 | select ARM_NVIC | |
2f618d5e AB |
320 | select CPU_V7M |
321 | select NO_IOPORT_MAP | |
2f618d5e | 322 | |
e0c25d95 DC |
323 | config ARCH_MMAP_RND_BITS_MIN |
324 | default 8 | |
325 | ||
326 | config ARCH_MMAP_RND_BITS_MAX | |
327 | default 14 if PAGE_OFFSET=0x40000000 | |
328 | default 15 if PAGE_OFFSET=0x80000000 | |
329 | default 16 | |
330 | ||
387798b3 | 331 | config ARCH_MULTIPLATFORM |
84fc8636 AB |
332 | bool "Require kernel to be portable to multiple machines" if EXPERT |
333 | depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) | |
334 | default y | |
1da177e4 | 335 | help |
84fc8636 AB |
336 | In general, all Arm machines can be supported in a single |
337 | kernel image, covering either Armv4/v5 or Armv6/v7. | |
1da177e4 | 338 | |
84fc8636 AB |
339 | However, some configuration options require hardcoding machine |
340 | specific physical addresses or enable errata workarounds that may | |
341 | break other machines. | |
1da177e4 | 342 | |
84fc8636 AB |
343 | Selecting N here allows using those options, including |
344 | DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. | |
1da177e4 | 345 | |
20e3ab9e | 346 | source "arch/arm/Kconfig.platforms" |
2cf1c348 | 347 | |
ccf50e23 RK |
348 | # |
349 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
350 | # Kconfigs may be included either alphabetically (according to the | |
351 | # plat- suffix) or along side the corresponding mach-* source. | |
352 | # | |
6bb8536c AF |
353 | source "arch/arm/mach-actions/Kconfig" |
354 | ||
445d9b30 TZ |
355 | source "arch/arm/mach-alpine/Kconfig" |
356 | ||
590b460c LP |
357 | source "arch/arm/mach-artpec/Kconfig" |
358 | ||
a66c51f9 AB |
359 | source "arch/arm/mach-aspeed/Kconfig" |
360 | ||
95b8f20f RK |
361 | source "arch/arm/mach-at91/Kconfig" |
362 | ||
1d22924e AB |
363 | source "arch/arm/mach-axxia/Kconfig" |
364 | ||
8ac49e04 CD |
365 | source "arch/arm/mach-bcm/Kconfig" |
366 | ||
1c37fa10 SH |
367 | source "arch/arm/mach-berlin/Kconfig" |
368 | ||
1da177e4 LT |
369 | source "arch/arm/mach-clps711x/Kconfig" |
370 | ||
95b8f20f RK |
371 | source "arch/arm/mach-davinci/Kconfig" |
372 | ||
df8d742e BS |
373 | source "arch/arm/mach-digicolor/Kconfig" |
374 | ||
95b8f20f RK |
375 | source "arch/arm/mach-dove/Kconfig" |
376 | ||
e7736d47 LB |
377 | source "arch/arm/mach-ep93xx/Kconfig" |
378 | ||
a66c51f9 | 379 | source "arch/arm/mach-exynos/Kconfig" |
a66c51f9 | 380 | |
1da177e4 LT |
381 | source "arch/arm/mach-footbridge/Kconfig" |
382 | ||
59d3a193 PZ |
383 | source "arch/arm/mach-gemini/Kconfig" |
384 | ||
387798b3 RH |
385 | source "arch/arm/mach-highbank/Kconfig" |
386 | ||
389ee0c2 HZ |
387 | source "arch/arm/mach-hisi/Kconfig" |
388 | ||
11d89440 NH |
389 | source "arch/arm/mach-hpe/Kconfig" |
390 | ||
a66c51f9 AB |
391 | source "arch/arm/mach-imx/Kconfig" |
392 | ||
1da177e4 LT |
393 | source "arch/arm/mach-ixp4xx/Kconfig" |
394 | ||
828989ad SS |
395 | source "arch/arm/mach-keystone/Kconfig" |
396 | ||
75bf1bd7 | 397 | source "arch/arm/mach-lpc32xx/Kconfig" |
95b8f20f | 398 | |
a66c51f9 AB |
399 | source "arch/arm/mach-mediatek/Kconfig" |
400 | ||
3b8f5030 CC |
401 | source "arch/arm/mach-meson/Kconfig" |
402 | ||
9fb29c73 ST |
403 | source "arch/arm/mach-milbeaut/Kconfig" |
404 | ||
a66c51f9 | 405 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 406 | |
312b62b6 DP |
407 | source "arch/arm/mach-mstar/Kconfig" |
408 | ||
794d15b2 SS |
409 | source "arch/arm/mach-mv78xx0/Kconfig" |
410 | ||
a66c51f9 | 411 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 412 | |
1d3f33d5 SG |
413 | source "arch/arm/mach-mxs/Kconfig" |
414 | ||
95b8f20f | 415 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 416 | |
7bffa14c BH |
417 | source "arch/arm/mach-npcm/Kconfig" |
418 | ||
d48af15e | 419 | source "arch/arm/mach-omap1/Kconfig" |
1da177e4 | 420 | |
1dbae815 TL |
421 | source "arch/arm/mach-omap2/Kconfig" |
422 | ||
9dd0b194 | 423 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 424 | |
95b8f20f | 425 | source "arch/arm/mach-pxa/Kconfig" |
585cf175 | 426 | |
8fc1b0f8 KG |
427 | source "arch/arm/mach-qcom/Kconfig" |
428 | ||
86aeee4d AF |
429 | source "arch/arm/mach-realtek/Kconfig" |
430 | ||
6fd09c9a AB |
431 | source "arch/arm/mach-rpc/Kconfig" |
432 | ||
d63dc051 HS |
433 | source "arch/arm/mach-rockchip/Kconfig" |
434 | ||
71b9114d | 435 | source "arch/arm/mach-s3c/Kconfig" |
a66c51f9 AB |
436 | |
437 | source "arch/arm/mach-s5pv210/Kconfig" | |
438 | ||
95b8f20f | 439 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 440 | |
a66c51f9 AB |
441 | source "arch/arm/mach-shmobile/Kconfig" |
442 | ||
387798b3 RH |
443 | source "arch/arm/mach-socfpga/Kconfig" |
444 | ||
a7ed099f | 445 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 446 | |
65ebcc11 SK |
447 | source "arch/arm/mach-sti/Kconfig" |
448 | ||
bcb84fb4 AT |
449 | source "arch/arm/mach-stm32/Kconfig" |
450 | ||
3b52634f MR |
451 | source "arch/arm/mach-sunxi/Kconfig" |
452 | ||
c5f80065 EG |
453 | source "arch/arm/mach-tegra/Kconfig" |
454 | ||
95b8f20f | 455 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
456 | |
457 | source "arch/arm/mach-versatile/Kconfig" | |
458 | ||
6f35f9a9 TP |
459 | source "arch/arm/mach-vt8500/Kconfig" |
460 | ||
9a45eb69 JC |
461 | source "arch/arm/mach-zynq/Kconfig" |
462 | ||
499f1640 | 463 | # ARMv7-M architecture |
499f1640 SA |
464 | config ARCH_LPC18XX |
465 | bool "NXP LPC18xx/LPC43xx" | |
466 | depends on ARM_SINGLE_ARMV7M | |
467 | select ARCH_HAS_RESET_CONTROLLER | |
468 | select ARM_AMBA | |
469 | select CLKSRC_LPC32XX | |
470 | select PINCTRL | |
471 | help | |
472 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
473 | high performance microcontrollers. | |
474 | ||
1847119d | 475 | config ARCH_MPS2 |
17bd274e | 476 | bool "ARM MPS2 platform" |
1847119d VM |
477 | depends on ARM_SINGLE_ARMV7M |
478 | select ARM_AMBA | |
479 | select CLKSRC_MPS2 | |
480 | help | |
481 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
482 | with a range of available cores like Cortex-M3/M4/M7. | |
483 | ||
484 | Please, note that depends which Application Note is used memory map | |
485 | for the platform may vary, so adjustment of RAM base might be needed. | |
486 | ||
1da177e4 LT |
487 | # Definitions to make life easier |
488 | config ARCH_ACORN | |
489 | bool | |
490 | ||
69b02f6a LB |
491 | config PLAT_ORION |
492 | bool | |
bfe45e0b | 493 | select CLKSRC_MMIO |
dc7ad3b3 | 494 | select GENERIC_IRQ_CHIP |
278b45b0 | 495 | select IRQ_DOMAIN |
69b02f6a | 496 | |
abcda1dc TP |
497 | config PLAT_ORION_LEGACY |
498 | bool | |
499 | select PLAT_ORION | |
500 | ||
f4b8b319 RK |
501 | config PLAT_VERSATILE |
502 | bool | |
503 | ||
8636a1f9 | 504 | source "arch/arm/mm/Kconfig" |
1da177e4 | 505 | |
afe4b25e | 506 | config IWMMXT |
d93003e8 | 507 | bool "Enable iWMMXt support" |
b9920fdd AB |
508 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK |
509 | default y if PXA27x || PXA3xx || ARCH_MMP | |
afe4b25e LB |
510 | help |
511 | Enable support for iWMMXt context switching at run time if | |
512 | running on a CPU that supports it. | |
513 | ||
3b93e7b0 HC |
514 | if !MMU |
515 | source "arch/arm/Kconfig-nommu" | |
516 | endif | |
517 | ||
3e0a07f8 GC |
518 | config PJ4B_ERRATA_4742 |
519 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
520 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
521 | default y | |
522 | help | |
523 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
524 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
525 | the retiring WFI/WFE instructions and the newly issued subsequent | |
526 | instructions. This sensitivity can result in a CPU hang scenario. | |
527 | Workaround: | |
528 | The software must insert either a Data Synchronization Barrier (DSB) | |
529 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
530 | instruction | |
531 | ||
f0c4b8d6 WD |
532 | config ARM_ERRATA_326103 |
533 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
534 | depends on CPU_V6 | |
535 | help | |
536 | Executing a SWP instruction to read-only memory does not set bit 11 | |
537 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
538 | treat the access as a read, preventing a COW from occurring and | |
539 | causing the faulting task to livelock. | |
540 | ||
9cba3ccc CM |
541 | config ARM_ERRATA_411920 |
542 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 543 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
544 | help |
545 | Invalidation of the Instruction Cache operation can | |
546 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
547 | It does not affect the MPCore. This option enables the ARM Ltd. | |
548 | recommended workaround. | |
549 | ||
7ce236fc CM |
550 | config ARM_ERRATA_430973 |
551 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
552 | depends on CPU_V7 | |
553 | help | |
554 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 555 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
556 | interworking branch is replaced with another code sequence at the |
557 | same virtual address, whether due to self-modifying code or virtual | |
558 | to physical address re-mapping, Cortex-A8 does not recover from the | |
559 | stale interworking branch prediction. This results in Cortex-A8 | |
560 | executing the new code sequence in the incorrect ARM or Thumb state. | |
561 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
562 | and also flushes the branch target cache at every context switch. | |
563 | Note that setting specific bits in the ACTLR register may not be | |
564 | available in non-secure mode. | |
565 | ||
855c551f CM |
566 | config ARM_ERRATA_458693 |
567 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
568 | depends on CPU_V7 | |
62e4d357 | 569 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
570 | help |
571 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
572 | erratum. For very specific sequences of memory operations, it is | |
573 | possible for a hazard condition intended for a cache line to instead | |
574 | be incorrectly associated with a different cache line. This false | |
575 | hazard might then cause a processor deadlock. The workaround enables | |
576 | the L1 caching of the NEON accesses and disables the PLD instruction | |
577 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
368ccecd SR |
578 | register may not be available in non-secure mode and thus is not |
579 | available on a multiplatform kernel. This should be applied by the | |
580 | bootloader instead. | |
855c551f | 581 | |
0516e464 CM |
582 | config ARM_ERRATA_460075 |
583 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
584 | depends on CPU_V7 | |
62e4d357 | 585 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
586 | help |
587 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
588 | erratum. Any asynchronous access to the L2 cache may encounter a | |
589 | situation in which recent store transactions to the L2 cache are lost | |
590 | and overwritten with stale memory contents from external memory. The | |
591 | workaround disables the write-allocate mode for the L2 cache via the | |
592 | ACTLR register. Note that setting specific bits in the ACTLR register | |
368ccecd SR |
593 | may not be available in non-secure mode and thus is not available on |
594 | a multiplatform kernel. This should be applied by the bootloader | |
595 | instead. | |
0516e464 | 596 | |
9f05027c WD |
597 | config ARM_ERRATA_742230 |
598 | bool "ARM errata: DMB operation may be faulty" | |
599 | depends on CPU_V7 && SMP | |
62e4d357 | 600 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
601 | help |
602 | This option enables the workaround for the 742230 Cortex-A9 | |
603 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
604 | between two write operations may not ensure the correct visibility | |
605 | ordering of the two writes. This workaround sets a specific bit in | |
606 | the diagnostic register of the Cortex-A9 which causes the DMB | |
607 | instruction to behave as a DSB, ensuring the correct behaviour of | |
368ccecd SR |
608 | the two writes. Note that setting specific bits in the diagnostics |
609 | register may not be available in non-secure mode and thus is not | |
610 | available on a multiplatform kernel. This should be applied by the | |
611 | bootloader instead. | |
9f05027c | 612 | |
a672e99b WD |
613 | config ARM_ERRATA_742231 |
614 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
615 | depends on CPU_V7 && SMP | |
62e4d357 | 616 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
617 | help |
618 | This option enables the workaround for the 742231 Cortex-A9 | |
619 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
620 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
621 | accessing some data located in the same cache line, may get corrupted | |
622 | data due to bad handling of the address hazard when the line gets | |
623 | replaced from one of the CPUs at the same time as another CPU is | |
624 | accessing it. This workaround sets specific bits in the diagnostic | |
625 | register of the Cortex-A9 which reduces the linefill issuing | |
368ccecd SR |
626 | capabilities of the processor. Note that setting specific bits in the |
627 | diagnostics register may not be available in non-secure mode and thus | |
628 | is not available on a multiplatform kernel. This should be applied by | |
629 | the bootloader instead. | |
a672e99b | 630 | |
69155794 JM |
631 | config ARM_ERRATA_643719 |
632 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
633 | depends on CPU_V7 && SMP | |
e5a5de44 | 634 | default y |
69155794 JM |
635 | help |
636 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
637 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
638 | register returns zero when it should return one. The workaround | |
639 | corrects this value, ensuring cache maintenance operations which use | |
640 | it behave as intended and avoiding data corruption. | |
641 | ||
cdf357f1 WD |
642 | config ARM_ERRATA_720789 |
643 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 644 | depends on CPU_V7 |
cdf357f1 WD |
645 | help |
646 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
647 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
648 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
649 | As a consequence of this erratum, some TLB entries which should be | |
650 | invalidated are not, resulting in an incoherency in the system page | |
651 | tables. The workaround changes the TLB flushing routines to invalidate | |
652 | entries regardless of the ASID. | |
475d92fc WD |
653 | |
654 | config ARM_ERRATA_743622 | |
655 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
656 | depends on CPU_V7 | |
62e4d357 | 657 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
658 | help |
659 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 660 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
661 | optimisation in the Cortex-A9 Store Buffer may lead to data |
662 | corruption. This workaround sets a specific bit in the diagnostic | |
663 | register of the Cortex-A9 which disables the Store Buffer | |
664 | optimisation, preventing the defect from occurring. This has no | |
665 | visible impact on the overall performance or power consumption of the | |
368ccecd SR |
666 | processor. Note that setting specific bits in the diagnostics register |
667 | may not be available in non-secure mode and thus is not available on a | |
668 | multiplatform kernel. This should be applied by the bootloader instead. | |
475d92fc | 669 | |
9a27c27c WD |
670 | config ARM_ERRATA_751472 |
671 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 672 | depends on CPU_V7 |
62e4d357 | 673 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
674 | help |
675 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
676 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
677 | completion of a following broadcasted operation if the second | |
678 | operation is received by a CPU before the ICIALLUIS has completed, | |
679 | potentially leading to corrupted entries in the cache or TLB. | |
368ccecd SR |
680 | Note that setting specific bits in the diagnostics register may |
681 | not be available in non-secure mode and thus is not available on | |
682 | a multiplatform kernel. This should be applied by the bootloader | |
683 | instead. | |
9a27c27c | 684 | |
fcbdc5fe WD |
685 | config ARM_ERRATA_754322 |
686 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
687 | depends on CPU_V7 | |
688 | help | |
689 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
690 | r3p*) erratum. A speculative memory access may cause a page table walk | |
691 | which starts prior to an ASID switch but completes afterwards. This | |
692 | can populate the micro-TLB with a stale entry which may be hit with | |
693 | the new ASID. This workaround places two dsb instructions in the mm | |
694 | switching code so that no page table walks can cross the ASID switch. | |
695 | ||
5dab26af WD |
696 | config ARM_ERRATA_754327 |
697 | bool "ARM errata: no automatic Store Buffer drain" | |
698 | depends on CPU_V7 && SMP | |
699 | help | |
700 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
701 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
702 | mechanism and therefore a livelock may occur if an external agent | |
703 | continuously polls a memory location waiting to observe an update. | |
704 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
705 | written polling loops from denying visibility of updates to memory. | |
706 | ||
145e10e1 CM |
707 | config ARM_ERRATA_364296 |
708 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 709 | depends on CPU_V6 |
145e10e1 CM |
710 | help |
711 | This options enables the workaround for the 364296 ARM1136 | |
712 | r0p2 erratum (possible cache data corruption with | |
713 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
714 | the auxiliary control register and the FI bit in the control | |
715 | register, thus disabling hit-under-miss without putting the | |
716 | processor into full low interrupt latency mode. ARM11MPCore | |
717 | is not affected. | |
718 | ||
f630c1bd WD |
719 | config ARM_ERRATA_764369 |
720 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
721 | depends on CPU_V7 && SMP | |
722 | help | |
723 | This option enables the workaround for erratum 764369 | |
724 | affecting Cortex-A9 MPCore with two or more processors (all | |
725 | current revisions). Under certain timing circumstances, a data | |
726 | cache line maintenance operation by MVA targeting an Inner | |
727 | Shareable memory region may fail to proceed up to either the | |
728 | Point of Coherency or to the Point of Unification of the | |
729 | system. This workaround adds a DSB instruction before the | |
730 | relevant cache maintenance functions and sets a specific bit | |
731 | in the diagnostic control register of the SCU. | |
732 | ||
8294fec1 NH |
733 | config ARM_ERRATA_764319 |
734 | bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" | |
735 | depends on CPU_V7 | |
736 | help | |
737 | This option enables the workaround for the 764319 Cortex A-9 erratum. | |
738 | CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an | |
739 | unexpected Undefined Instruction exception when the DBGSWENABLE | |
740 | external pin is set to 0, even when the CP14 accesses are performed | |
741 | from a privileged mode. This work around catches the exception in a | |
742 | way the kernel does not stop execution. | |
743 | ||
7253b85c SH |
744 | config ARM_ERRATA_775420 |
745 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
746 | depends on CPU_V7 | |
747 | help | |
748 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
cb73737e | 749 | r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance |
7253b85c SH |
750 | operation aborts with MMU exception, it might cause the processor |
751 | to deadlock. This workaround puts DSB before executing ISB if | |
752 | an abort may occur on cache maintenance. | |
753 | ||
93dc6887 CM |
754 | config ARM_ERRATA_798181 |
755 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
756 | depends on CPU_V7 && SMP | |
757 | help | |
758 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
759 | adequately shooting down all use of the old entries. This | |
760 | option enables the Linux kernel workaround for this erratum | |
761 | which sends an IPI to the CPUs that are running the same ASID | |
762 | as the one being invalidated. | |
763 | ||
84b6504f WD |
764 | config ARM_ERRATA_773022 |
765 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
766 | depends on CPU_V7 | |
767 | help | |
768 | This option enables the workaround for the 773022 Cortex-A15 | |
769 | (up to r0p4) erratum. In certain rare sequences of code, the | |
770 | loop buffer may deliver incorrect instructions. This | |
771 | workaround disables the loop buffer to avoid the erratum. | |
772 | ||
62c0f4a5 DA |
773 | config ARM_ERRATA_818325_852422 |
774 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
775 | depends on CPU_V7 | |
776 | help | |
777 | This option enables the workaround for: | |
778 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
779 | instruction might deadlock. Fixed in r0p1. | |
780 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
781 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
782 | any Cortex-A12 cores yet. | |
783 | This workaround for all both errata involves setting bit[12] of the | |
784 | Feature Register. This bit disables an optimisation applied to a | |
785 | sequence of 2 instructions that use opposing condition codes. | |
786 | ||
416bcf21 DA |
787 | config ARM_ERRATA_821420 |
788 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
789 | depends on CPU_V7 | |
790 | help | |
791 | This option enables the workaround for the 821420 Cortex-A12 | |
792 | (all revs) erratum. In very rare timing conditions, a sequence | |
793 | of VMOV to Core registers instructions, for which the second | |
794 | one is in the shadow of a branch or abort, can lead to a | |
795 | deadlock when the VMOV instructions are issued out-of-order. | |
796 | ||
9f6f9354 DA |
797 | config ARM_ERRATA_825619 |
798 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
799 | depends on CPU_V7 | |
800 | help | |
801 | This option enables the workaround for the 825619 Cortex-A12 | |
802 | (all revs) erratum. Within rare timing constraints, executing a | |
803 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
804 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
805 | ||
304009a1 DA |
806 | config ARM_ERRATA_857271 |
807 | bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" | |
808 | depends on CPU_V7 | |
809 | help | |
810 | This option enables the workaround for the 857271 Cortex-A12 | |
811 | (all revs) erratum. Under very rare timing conditions, the CPU might | |
812 | hang. The workaround is expected to have a < 1% performance impact. | |
813 | ||
9f6f9354 DA |
814 | config ARM_ERRATA_852421 |
815 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
816 | depends on CPU_V7 | |
817 | help | |
818 | This option enables the workaround for the 852421 Cortex-A17 | |
819 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
820 | execution of a DMB ST instruction might fail to properly order | |
821 | stores from GroupA and stores from GroupB. | |
822 | ||
62c0f4a5 DA |
823 | config ARM_ERRATA_852423 |
824 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
825 | depends on CPU_V7 | |
826 | help | |
827 | This option enables the workaround for: | |
828 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
829 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
830 | any Cortex-A17 cores yet. | |
831 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
832 | config option from the A12 erratum due to the way errata are checked | |
833 | for and handled. | |
834 | ||
304009a1 DA |
835 | config ARM_ERRATA_857272 |
836 | bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" | |
837 | depends on CPU_V7 | |
838 | help | |
839 | This option enables the workaround for the 857272 Cortex-A17 erratum. | |
840 | This erratum is not known to be fixed in any A17 revision. | |
841 | This is identical to Cortex-A12 erratum 857271. It is a separate | |
842 | config option from the A12 erratum due to the way errata are checked | |
843 | for and handled. | |
844 | ||
1da177e4 LT |
845 | endmenu |
846 | ||
847 | source "arch/arm/common/Kconfig" | |
848 | ||
1da177e4 LT |
849 | menu "Bus support" |
850 | ||
1da177e4 LT |
851 | config ISA |
852 | bool | |
1da177e4 LT |
853 | help |
854 | Find out whether you have ISA slots on your motherboard. ISA is the | |
855 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
856 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
857 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
858 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
859 | ||
065909b9 | 860 | # Select ISA DMA interface |
5cae841b AV |
861 | config ISA_DMA_API |
862 | bool | |
5cae841b | 863 | |
779eb41c BG |
864 | config ARM_ERRATA_814220 |
865 | bool "ARM errata: Cache maintenance by set/way operations can execute out of order" | |
866 | depends on CPU_V7 | |
867 | help | |
868 | The v7 ARM states that all cache and branch predictor maintenance | |
869 | operations that do not specify an address execute, relative to | |
870 | each other, in program order. | |
871 | However, because of this erratum, an L2 set/way cache maintenance | |
872 | operation can overtake an L1 set/way cache maintenance operation. | |
873 | This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, | |
874 | r0p4, r0p5. | |
875 | ||
1da177e4 LT |
876 | endmenu |
877 | ||
878 | menu "Kernel Features" | |
879 | ||
3b55658a DM |
880 | config HAVE_SMP |
881 | bool | |
882 | help | |
883 | This option should be selected by machines which have an SMP- | |
884 | capable CPU. | |
885 | ||
886 | The only effect of this option is to make the SMP-related | |
887 | options available to the user for configuration. | |
888 | ||
1da177e4 | 889 | config SMP |
bb2d8130 | 890 | bool "Symmetric Multi-Processing" |
fbb4ddac | 891 | depends on CPU_V6K || CPU_V7 |
3b55658a | 892 | depends on HAVE_SMP |
801bb21c | 893 | depends on MMU || ARM_MPU |
0361748f | 894 | select IRQ_WORK |
1da177e4 LT |
895 | help |
896 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
897 | a system with only one CPU, say N. If you have a system with more |
898 | than one CPU, say Y. | |
1da177e4 | 899 | |
4a474157 | 900 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 901 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
902 | you say Y here, the kernel will run on many, but not all, |
903 | uniprocessor machines. On a uniprocessor machine, the kernel | |
904 | will run faster if you say N here. | |
1da177e4 | 905 | |
ff61f079 | 906 | See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, |
4f4cfa6c | 907 | <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at |
50a23e6e | 908 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
909 | |
910 | If you don't know what to do here, say N. | |
911 | ||
f00ec48f | 912 | config SMP_ON_UP |
5744ff43 | 913 | bool "Allow booting SMP kernel on uniprocessor systems" |
5408445b | 914 | depends on SMP && MMU |
f00ec48f RK |
915 | default y |
916 | help | |
917 | SMP kernels contain instructions which fail on non-SMP processors. | |
918 | Enabling this option allows the kernel to modify itself to make | |
919 | these instructions safe. Disabling it allows about 1K of space | |
920 | savings. | |
921 | ||
922 | If you don't know what to do here, say Y. | |
923 | ||
50596b75 AB |
924 | |
925 | config CURRENT_POINTER_IN_TPIDRURO | |
926 | def_bool y | |
b87cf911 | 927 | depends on CPU_32v6K && !CPU_V6 |
50596b75 | 928 | |
d4664b6c AB |
929 | config IRQSTACKS |
930 | def_bool y | |
9974f857 AB |
931 | select HAVE_IRQ_EXIT_ON_IRQ_STACK |
932 | select HAVE_SOFTIRQ_ON_OWN_STACK | |
50596b75 | 933 | |
c9018aab VG |
934 | config ARM_CPU_TOPOLOGY |
935 | bool "Support cpu topology definition" | |
936 | depends on SMP && CPU_V7 | |
937 | default y | |
938 | help | |
939 | Support ARM cpu topology definition. The MPIDR register defines | |
940 | affinity between processors which is then used to describe the cpu | |
941 | topology of an ARM System. | |
942 | ||
943 | config SCHED_MC | |
944 | bool "Multi-core scheduler support" | |
945 | depends on ARM_CPU_TOPOLOGY | |
946 | help | |
947 | Multi-core scheduler support improves the CPU scheduler's decision | |
948 | making when dealing with multi-core CPU chips at a cost of slightly | |
949 | increased overhead in some places. If unsure say N here. | |
950 | ||
951 | config SCHED_SMT | |
952 | bool "SMT scheduler support" | |
953 | depends on ARM_CPU_TOPOLOGY | |
954 | help | |
955 | Improves the CPU scheduler's decision making when dealing with | |
956 | MultiThreading at a cost of slightly increased overhead in some | |
957 | places. If unsure say N here. | |
958 | ||
a8cbcd92 RK |
959 | config HAVE_ARM_SCU |
960 | bool | |
a8cbcd92 | 961 | help |
8f433ec4 | 962 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 963 | |
8a4da6e3 | 964 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
965 | bool "Architected timer support" |
966 | depends on CPU_V7 | |
8a4da6e3 | 967 | select ARM_ARCH_TIMER |
022c03a2 MZ |
968 | help |
969 | This option enables support for the ARM architected timer | |
970 | ||
f32f4ce2 RK |
971 | config HAVE_ARM_TWD |
972 | bool | |
f32f4ce2 RK |
973 | help |
974 | This options enables support for the ARM timer and watchdog unit | |
975 | ||
e8db288e NP |
976 | config MCPM |
977 | bool "Multi-Cluster Power Management" | |
978 | depends on CPU_V7 && SMP | |
979 | help | |
980 | This option provides the common power management infrastructure | |
981 | for (multi-)cluster based systems, such as big.LITTLE based | |
982 | systems. | |
983 | ||
ebf4a5c5 HZ |
984 | config MCPM_QUAD_CLUSTER |
985 | bool | |
986 | depends on MCPM | |
987 | help | |
988 | To avoid wasting resources unnecessarily, MCPM only supports up | |
989 | to 2 clusters by default. | |
990 | Platforms with 3 or 4 clusters that use MCPM must select this | |
991 | option to allow the additional clusters to be managed. | |
992 | ||
1c33be57 NP |
993 | config BIG_LITTLE |
994 | bool "big.LITTLE support (Experimental)" | |
995 | depends on CPU_V7 && SMP | |
996 | select MCPM | |
997 | help | |
998 | This option enables support selections for the big.LITTLE | |
999 | system architecture. | |
1000 | ||
1001 | config BL_SWITCHER | |
1002 | bool "big.LITTLE switcher support" | |
6c044fec | 1003 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1004 | select CPU_PM |
1c33be57 NP |
1005 | help |
1006 | The big.LITTLE "switcher" provides the core functionality to | |
1007 | transparently handle transition between a cluster of A15's | |
1008 | and a cluster of A7's in a big.LITTLE system. | |
1009 | ||
b22537c6 NP |
1010 | config BL_SWITCHER_DUMMY_IF |
1011 | tristate "Simple big.LITTLE switcher user interface" | |
1012 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1013 | help | |
1014 | This is a simple and dummy char dev interface to control | |
1015 | the big.LITTLE switcher core code. It is meant for | |
1016 | debugging purposes only. | |
1017 | ||
8d5796d2 LB |
1018 | choice |
1019 | prompt "Memory split" | |
006fa259 | 1020 | depends on MMU |
8d5796d2 LB |
1021 | default VMSPLIT_3G |
1022 | help | |
1023 | Select the desired split between kernel and user memory. | |
1024 | ||
1025 | If you are not absolutely sure what you are doing, leave this | |
1026 | option alone! | |
1027 | ||
1028 | config VMSPLIT_3G | |
1029 | bool "3G/1G user/kernel split" | |
63ce446c | 1030 | config VMSPLIT_3G_OPT |
bbeedfda | 1031 | depends on !ARM_LPAE |
63ce446c | 1032 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1033 | config VMSPLIT_2G |
1034 | bool "2G/2G user/kernel split" | |
1035 | config VMSPLIT_1G | |
1036 | bool "1G/3G user/kernel split" | |
1037 | endchoice | |
1038 | ||
1039 | config PAGE_OFFSET | |
1040 | hex | |
006fa259 | 1041 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1042 | default 0x40000000 if VMSPLIT_1G |
1043 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1044 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1045 | default 0xC0000000 |
1046 | ||
c12366ba LW |
1047 | config KASAN_SHADOW_OFFSET |
1048 | hex | |
1049 | depends on KASAN | |
1050 | default 0x1f000000 if PAGE_OFFSET=0x40000000 | |
1051 | default 0x5f000000 if PAGE_OFFSET=0x80000000 | |
1052 | default 0x9f000000 if PAGE_OFFSET=0xC0000000 | |
1053 | default 0x8f000000 if PAGE_OFFSET=0xB0000000 | |
1054 | default 0xffffffff | |
1055 | ||
1da177e4 LT |
1056 | config NR_CPUS |
1057 | int "Maximum number of CPUs (2-32)" | |
d624833f AB |
1058 | range 2 16 if DEBUG_KMAP_LOCAL |
1059 | range 2 32 if !DEBUG_KMAP_LOCAL | |
1da177e4 LT |
1060 | depends on SMP |
1061 | default "4" | |
d624833f AB |
1062 | help |
1063 | The maximum number of CPUs that the kernel can support. | |
1064 | Up to 32 CPUs can be supported, or up to 16 if kmap_local() | |
1065 | debugging is enabled, which uses half of the per-CPU fixmap | |
1066 | slots as guard regions. | |
1da177e4 | 1067 | |
a054a811 | 1068 | config HOTPLUG_CPU |
00b7dede | 1069 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1070 | depends on SMP |
1b5ba350 | 1071 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1072 | help |
1073 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1074 | can be controlled through /sys/devices/system/cpu. | |
1075 | ||
2bdd424f WD |
1076 | config ARM_PSCI |
1077 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1078 | depends on HAVE_ARM_SMCCC |
be120397 | 1079 | select ARM_PSCI_FW |
2bdd424f WD |
1080 | help |
1081 | Say Y here if you want Linux to communicate with system firmware | |
1082 | implementing the PSCI specification for CPU-centric power | |
1083 | management operations described in ARM document number ARM DEN | |
1084 | 0022A ("Power State Coordination Interface System Software on | |
1085 | ARM processors"). | |
1086 | ||
c9218b16 | 1087 | config HZ_FIXED |
f8065813 | 1088 | int |
1164f672 | 1089 | default 128 if SOC_AT91RM9200 |
47d84682 | 1090 | default 0 |
c9218b16 RK |
1091 | |
1092 | choice | |
47d84682 | 1093 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1094 | prompt "Timer frequency" |
1095 | ||
1096 | config HZ_100 | |
1097 | bool "100 Hz" | |
1098 | ||
1099 | config HZ_200 | |
1100 | bool "200 Hz" | |
1101 | ||
1102 | config HZ_250 | |
1103 | bool "250 Hz" | |
1104 | ||
1105 | config HZ_300 | |
1106 | bool "300 Hz" | |
1107 | ||
1108 | config HZ_500 | |
1109 | bool "500 Hz" | |
1110 | ||
1111 | config HZ_1000 | |
1112 | bool "1000 Hz" | |
1113 | ||
1114 | endchoice | |
1115 | ||
1116 | config HZ | |
1117 | int | |
47d84682 | 1118 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1119 | default 100 if HZ_100 |
1120 | default 200 if HZ_200 | |
1121 | default 250 if HZ_250 | |
1122 | default 300 if HZ_300 | |
1123 | default 500 if HZ_500 | |
1124 | default 1000 | |
1125 | ||
1126 | config SCHED_HRTICK | |
1127 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1128 | |
16c79651 | 1129 | config THUMB2_KERNEL |
bc7dea00 | 1130 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1131 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1132 | default y if CPU_THUMBONLY |
89bace65 | 1133 | select ARM_UNWIND |
16c79651 CM |
1134 | help |
1135 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1136 | Thumb-2 mode. |
16c79651 CM |
1137 | |
1138 | If unsure, say N. | |
1139 | ||
42f25bdd NP |
1140 | config ARM_PATCH_IDIV |
1141 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
5408445b | 1142 | depends on CPU_32v7 |
42f25bdd NP |
1143 | default y |
1144 | help | |
1145 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1146 | __aeabi_uidiv() when it needs to perform division on signed | |
1147 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1148 | and udiv instructions that can be used to implement those | |
1149 | functions. | |
1150 | ||
1151 | Enabling this option allows the kernel to modify itself to | |
1152 | replace the first two instructions of these library functions | |
1153 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1154 | it is running on supports them. Typically this will be faster | |
1155 | and less power intensive than running the original library | |
1156 | code to do integer division. | |
1157 | ||
704bdda0 | 1158 | config AEABI |
a05b9608 ND |
1159 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ |
1160 | !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG | |
1161 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG | |
704bdda0 NP |
1162 | help |
1163 | This option allows for the kernel to be compiled using the latest | |
1164 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1165 | space environment that is also compiled with EABI. | |
1166 | ||
1167 | Since there are major incompatibilities between the legacy ABI and | |
1168 | EABI, especially with regard to structure member alignment, this | |
1169 | option also changes the kernel syscall calling convention to | |
1170 | disambiguate both ABIs and allow for backward compatibility support | |
1171 | (selected with CONFIG_OABI_COMPAT). | |
1172 | ||
1173 | To use this you need GCC version 4.0.0 or later. | |
1174 | ||
6c90c872 | 1175 | config OABI_COMPAT |
a73a3ff1 | 1176 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1177 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1178 | help |
1179 | This option preserves the old syscall interface along with the | |
1180 | new (ARM EABI) one. It also provides a compatibility layer to | |
1181 | intercept syscalls that have structure arguments which layout | |
1182 | in memory differs between the legacy ABI and the new ARM EABI | |
1183 | (only for non "thumb" binaries). This option adds a tiny | |
1184 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1185 | |
1186 | The seccomp filter system will not be available when this is | |
1187 | selected, since there is no way yet to sensibly distinguish | |
1188 | between calling conventions during filtering. | |
1189 | ||
6c90c872 NP |
1190 | If you know you'll be using only pure EABI user space then you |
1191 | can say N here. If this option is not selected and you attempt | |
1192 | to execute a legacy ABI binary then the result will be | |
1193 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1194 | at all). If in doubt say N. |
6c90c872 | 1195 | |
fb597f2a | 1196 | config ARCH_SELECT_MEMORY_MODEL |
6fd09c9a | 1197 | def_bool y |
fb597f2a GF |
1198 | |
1199 | config ARCH_FLATMEM_ENABLE | |
6fd09c9a | 1200 | def_bool !(ARCH_RPC || ARCH_SA1100) |
05944d74 | 1201 | |
05944d74 | 1202 | config ARCH_SPARSEMEM_ENABLE |
6fd09c9a | 1203 | def_bool !ARCH_FOOTBRIDGE |
fb597f2a | 1204 | select SPARSEMEM_STATIC if SPARSEMEM |
07a2f737 | 1205 | |
053a96ca | 1206 | config HIGHMEM |
e8db89a2 RK |
1207 | bool "High Memory Support" |
1208 | depends on MMU | |
2a15ba82 | 1209 | select KMAP_LOCAL |
825c43f5 | 1210 | select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY |
053a96ca NP |
1211 | help |
1212 | The address space of ARM processors is only 4 Gigabytes large | |
1213 | and it has to accommodate user address space, kernel address | |
1214 | space as well as some memory mapped IO. That means that, if you | |
1215 | have a large amount of physical memory and/or IO, not all of the | |
1216 | memory can be "permanently mapped" by the kernel. The physical | |
1217 | memory that is not permanently mapped is called "high memory". | |
1218 | ||
1219 | Depending on the selected kernel/user memory split, minimum | |
1220 | vmalloc space and actual amount of RAM, you may not need this | |
1221 | option which should result in a slightly faster kernel. | |
1222 | ||
1223 | If unsure, say n. | |
1224 | ||
65cec8e3 | 1225 | config HIGHPTE |
9a431bd5 | 1226 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1227 | depends on HIGHMEM |
9a431bd5 | 1228 | default y |
b4d103d1 RK |
1229 | help |
1230 | The VM uses one page of physical memory for each page table. | |
1231 | For systems with a lot of processes, this can use a lot of | |
1232 | precious low memory, eventually leading to low memory being | |
1233 | consumed by page tables. Setting this option will allow | |
1234 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1235 | |
a5e090ac RK |
1236 | config CPU_SW_DOMAIN_PAN |
1237 | bool "Enable use of CPU domains to implement privileged no-access" | |
1238 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1239 | default y |
1240 | help | |
a5e090ac RK |
1241 | Increase kernel security by ensuring that normal kernel accesses |
1242 | are unable to access userspace addresses. This can help prevent | |
1243 | use-after-free bugs becoming an exploitable privilege escalation | |
1244 | by ensuring that magic values (such as LIST_POISON) will always | |
1245 | fault when dereferenced. | |
1246 | ||
1247 | CPUs with low-vector mappings use a best-efforts implementation. | |
1248 | Their lower 1MB needs to remain accessible for the vectors, but | |
1249 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1250 | |
1b8873a0 | 1251 | config HW_PERF_EVENTS |
fa8ad788 MR |
1252 | def_bool y |
1253 | depends on ARM_PMU | |
1b8873a0 | 1254 | |
7d485f64 AB |
1255 | config ARM_MODULE_PLTS |
1256 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1257 | depends on MODULES | |
8fa7ea40 | 1258 | select KASAN_VMALLOC if KASAN |
e7229f7d | 1259 | default y |
7d485f64 AB |
1260 | help |
1261 | Allocate PLTs when loading modules so that jumps and calls whose | |
1262 | targets are too far away for their relative offsets to be encoded | |
1263 | in the instructions themselves can be bounced via veneers in the | |
1264 | module's PLT. This allows modules to be allocated in the generic | |
1265 | vmalloc area after the dedicated module memory area has been | |
1266 | exhausted. The modules will use slightly more memory, but after | |
1267 | rounding up to page size, the actual memory footprint is usually | |
1268 | the same. | |
1269 | ||
e7229f7d AR |
1270 | Disabling this is usually safe for small single-platform |
1271 | configurations. If unsure, say y. | |
7d485f64 | 1272 | |
0192445c | 1273 | config ARCH_FORCE_MAX_ORDER |
8c907785 | 1274 | int "Order of maximal physically contiguous allocations" |
23baf831 KS |
1275 | default "11" if SOC_AM33XX |
1276 | default "8" if SA1111 | |
1277 | default "10" | |
c1b2d970 | 1278 | help |
8c907785 | 1279 | The kernel page allocator limits the size of maximal physically |
5e0a760b | 1280 | contiguous allocations. The limit is called MAX_PAGE_ORDER and it |
8c907785 MRI |
1281 | defines the maximal power of two of number of pages that can be |
1282 | allocated as a single contiguous block. This option allows | |
1283 | overriding the default setting when ability to allocate very | |
1284 | large blocks of physically contiguous memory is required. | |
1285 | ||
1286 | Don't change if unsure. | |
c1b2d970 | 1287 | |
1da177e4 | 1288 | config ALIGNMENT_TRAP |
3e3f354b | 1289 | def_bool CPU_CP15_MMU |
e119bfff | 1290 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1291 | help |
84eb8d06 | 1292 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1293 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1294 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1295 | fetch/store instructions will be emulated in software if you say | |
1296 | here, which has a severe performance impact. This is necessary for | |
1297 | correct operation of some network protocols. With an IP-only | |
1298 | configuration it is safe to say N, otherwise say Y. | |
1299 | ||
39ec58f3 | 1300 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1301 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1302 | depends on MMU | |
39ec58f3 LB |
1303 | default y if CPU_FEROCEON |
1304 | help | |
1305 | Implement faster copy_to_user and clear_user methods for CPU | |
1306 | cores where a 8-word STM instruction give significantly higher | |
1307 | memory write throughput than a sequence of individual 32bit stores. | |
1308 | ||
1309 | A possible side effect is a slight increase in scheduling latency | |
1310 | between threads sharing the same address space if they invoke | |
1311 | such copy operations with large buffers. | |
1312 | ||
1313 | However, if the CPU data cache is using a write-allocate mode, | |
1314 | this option is unlikely to provide any performance gain. | |
1315 | ||
02c2433b SS |
1316 | config PARAVIRT |
1317 | bool "Enable paravirtualization code" | |
1318 | help | |
1319 | This changes the kernel so it can modify itself when it is run | |
1320 | under a hypervisor, potentially improving performance significantly | |
1321 | over full virtualization. | |
1322 | ||
1323 | config PARAVIRT_TIME_ACCOUNTING | |
1324 | bool "Paravirtual steal time accounting" | |
1325 | select PARAVIRT | |
02c2433b SS |
1326 | help |
1327 | Select this option to enable fine granularity task steal time | |
1328 | accounting. Time spent executing other tasks in parallel with | |
1329 | the current vCPU is discounted from the vCPU power. To account for | |
1330 | that, there can be a small performance impact. | |
1331 | ||
1332 | If in doubt, say N here. | |
1333 | ||
eff8d644 SS |
1334 | config XEN_DOM0 |
1335 | def_bool y | |
1336 | depends on XEN | |
1337 | ||
1338 | config XEN | |
c2ba1f7d | 1339 | bool "Xen guest support on ARM" |
85323a99 | 1340 | depends on ARM && AEABI && OF |
f880b67d | 1341 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1342 | depends on !GENERIC_ATOMIC64 |
7693decc | 1343 | depends on MMU |
51aaf81f | 1344 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1345 | select ARM_PSCI |
f21254cd | 1346 | select SWIOTLB |
83862ccf | 1347 | select SWIOTLB_XEN |
02c2433b | 1348 | select PARAVIRT |
eff8d644 SS |
1349 | help |
1350 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1351 | ||
f05eb1d2 AB |
1352 | config CC_HAVE_STACKPROTECTOR_TLS |
1353 | def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) | |
1354 | ||
189af465 AB |
1355 | config STACKPROTECTOR_PER_TASK |
1356 | bool "Use a unique stack canary value for each task" | |
9c46929e | 1357 | depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA |
f05eb1d2 AB |
1358 | depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS |
1359 | select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS | |
189af465 AB |
1360 | default y |
1361 | help | |
1362 | Due to the fact that GCC uses an ordinary symbol reference from | |
1363 | which to load the value of the stack canary, this value can only | |
1364 | change at reboot time on SMP systems, and all tasks running in the | |
1365 | kernel's address space are forced to use the same canary value for | |
1366 | the entire duration that the system is up. | |
1367 | ||
1368 | Enable this option to switch to a different method that uses a | |
1369 | different canary value for each task. | |
1370 | ||
1da177e4 LT |
1371 | endmenu |
1372 | ||
1373 | menu "Boot options" | |
1374 | ||
9eb8f674 GL |
1375 | config USE_OF |
1376 | bool "Flattened Device Tree support" | |
b1b3f49c | 1377 | select IRQ_DOMAIN |
9eb8f674 | 1378 | select OF |
9eb8f674 GL |
1379 | help |
1380 | Include support for flattened device tree machine descriptions. | |
1381 | ||
6a1d798f RH |
1382 | config ARCH_WANT_FLAT_DTB_INSTALL |
1383 | def_bool y | |
1384 | ||
bd51e2f5 | 1385 | config ATAGS |
96a4ce30 | 1386 | bool "Support for the traditional ATAGS boot data passing" |
bd51e2f5 NP |
1387 | default y |
1388 | help | |
1389 | This is the traditional way of passing data to the kernel at boot | |
1390 | time. If you are solely relying on the flattened device tree (or | |
1391 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
acb926d6 AB |
1392 | to remove ATAGS support from your kernel binary. |
1393 | ||
bd51e2f5 NP |
1394 | config DEPRECATED_PARAM_STRUCT |
1395 | bool "Provide old way to pass kernel parameters" | |
1396 | depends on ATAGS | |
1397 | help | |
1398 | This was deprecated in 2001 and announced to live on for 5 years. | |
1399 | Some old boot loaders still use this way. | |
1400 | ||
1da177e4 LT |
1401 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1402 | # TEXT and BSS so we preserve their values in the config files. | |
1403 | config ZBOOT_ROM_TEXT | |
1404 | hex "Compressed ROM boot loader base address" | |
39c3e304 | 1405 | default 0x0 |
1da177e4 LT |
1406 | help |
1407 | The physical address at which the ROM-able zImage is to be | |
1408 | placed in the target. Platforms which normally make use of | |
1409 | ROM-able zImage formats normally set this to a suitable | |
1410 | value in their defconfig file. | |
1411 | ||
1412 | If ZBOOT_ROM is not enabled, this has no effect. | |
1413 | ||
1414 | config ZBOOT_ROM_BSS | |
1415 | hex "Compressed ROM boot loader BSS address" | |
39c3e304 | 1416 | default 0x0 |
1da177e4 | 1417 | help |
f8c440b2 DF |
1418 | The base address of an area of read/write memory in the target |
1419 | for the ROM-able zImage which must be available while the | |
1420 | decompressor is running. It must be large enough to hold the | |
1421 | entire decompressed kernel plus an additional 128 KiB. | |
1422 | Platforms which normally make use of ROM-able zImage formats | |
1423 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1424 | |
1425 | If ZBOOT_ROM is not enabled, this has no effect. | |
1426 | ||
1427 | config ZBOOT_ROM | |
1428 | bool "Compressed boot loader in ROM/flash" | |
1429 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1430 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1431 | help |
1432 | Say Y here if you intend to execute your compressed kernel image | |
1433 | (zImage) directly from ROM or flash. If unsure, say N. | |
1434 | ||
e2a6a3aa JB |
1435 | config ARM_APPENDED_DTB |
1436 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1437 | depends on OF |
e2a6a3aa JB |
1438 | help |
1439 | With this option, the boot code will look for a device tree binary | |
1440 | (DTB) appended to zImage | |
1441 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1442 | ||
1443 | This is meant as a backward compatibility convenience for those | |
1444 | systems with a bootloader that can't be upgraded to accommodate | |
1445 | the documented boot protocol using a device tree. | |
1446 | ||
1447 | Beware that there is very little in terms of protection against | |
1448 | this option being confused by leftover garbage in memory that might | |
1449 | look like a DTB header after a reboot if no actual DTB is appended | |
1450 | to zImage. Do not leave this option active in a production kernel | |
1451 | if you don't intend to always append a DTB. Proper passing of the | |
1452 | location into r2 of a bootloader provided DTB is always preferable | |
1453 | to this option. | |
1454 | ||
b90b9a38 NP |
1455 | config ARM_ATAG_DTB_COMPAT |
1456 | bool "Supplement the appended DTB with traditional ATAG information" | |
1457 | depends on ARM_APPENDED_DTB | |
1458 | help | |
1459 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1460 | they provide ATAGs with memory configuration, the ramdisk address, | |
1461 | the kernel cmdline string, etc. Such information is dynamically | |
1462 | provided by the bootloader and can't always be stored in a static | |
1463 | DTB. To allow a device tree enabled kernel to be used with such | |
1464 | bootloaders, this option allows zImage to extract the information | |
1465 | from the ATAG list and store it at run time into the appended DTB. | |
1466 | ||
d0f34a11 GR |
1467 | choice |
1468 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1469 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1470 | ||
1471 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1472 | bool "Use bootloader kernel arguments if available" | |
1473 | help | |
1474 | Uses the command-line options passed by the boot loader instead of | |
1475 | the device tree bootargs property. If the boot loader doesn't provide | |
1476 | any, the device tree bootargs property will be used. | |
1477 | ||
1478 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1479 | bool "Extend with bootloader kernel arguments" | |
1480 | help | |
1481 | The command-line arguments provided by the boot loader will be | |
1482 | appended to the the device tree bootargs property. | |
1483 | ||
1484 | endchoice | |
1485 | ||
1da177e4 LT |
1486 | config CMDLINE |
1487 | string "Default kernel command string" | |
1488 | default "" | |
1489 | help | |
3e3f354b | 1490 | On some architectures (e.g. CATS), there is currently no way |
1da177e4 LT |
1491 | for the boot loader to pass arguments to the kernel. For these |
1492 | architectures, you should supply some command-line options at build | |
1493 | time by entering them here. As a minimum, you should specify the | |
1494 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1495 | ||
4394c124 VB |
1496 | choice |
1497 | prompt "Kernel command line type" if CMDLINE != "" | |
1498 | default CMDLINE_FROM_BOOTLOADER | |
1499 | ||
1500 | config CMDLINE_FROM_BOOTLOADER | |
1501 | bool "Use bootloader kernel arguments if available" | |
1502 | help | |
1503 | Uses the command-line options passed by the boot loader. If | |
1504 | the boot loader doesn't provide any, the default kernel command | |
1505 | string provided in CMDLINE will be used. | |
1506 | ||
1507 | config CMDLINE_EXTEND | |
1508 | bool "Extend bootloader kernel arguments" | |
1509 | help | |
1510 | The command-line arguments provided by the boot loader will be | |
1511 | appended to the default kernel command string. | |
1512 | ||
92d2040d AH |
1513 | config CMDLINE_FORCE |
1514 | bool "Always use the default kernel command string" | |
92d2040d AH |
1515 | help |
1516 | Always use the default kernel command string, even if the boot | |
1517 | loader passes other arguments to the kernel. | |
1518 | This is useful if you cannot or don't want to change the | |
1519 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1520 | endchoice |
92d2040d | 1521 | |
1da177e4 LT |
1522 | config XIP_KERNEL |
1523 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1524 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
5408445b | 1525 | depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP |
1da177e4 LT |
1526 | help |
1527 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1528 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1529 | space since the text section of the kernel is not loaded from flash | |
1530 | to RAM. Read-write sections, such as the data section and stack, | |
1531 | are still copied to RAM. The XIP kernel is not compressed since | |
1532 | it has to run directly from flash, so it will take more space to | |
1533 | store it. The flash address used to link the kernel object files, | |
1534 | and for storing it, is configuration dependent. Therefore, if you | |
1535 | say Y here, you must know the proper physical address where to | |
1536 | store the kernel image depending on your own flash memory usage. | |
1537 | ||
1538 | Also note that the make target becomes "make xipImage" rather than | |
1539 | "make zImage" or "make Image". The final kernel binary to put in | |
1540 | ROM memory will be arch/arm/boot/xipImage. | |
1541 | ||
1542 | If unsure, say N. | |
1543 | ||
1544 | config XIP_PHYS_ADDR | |
1545 | hex "XIP Kernel Physical Location" | |
1546 | depends on XIP_KERNEL | |
1547 | default "0x00080000" | |
1548 | help | |
1549 | This is the physical address in your flash memory the kernel will | |
1550 | be linked for and stored to. This address is dependent on your | |
1551 | own flash usage. | |
1552 | ||
ca8b5d97 NP |
1553 | config XIP_DEFLATED_DATA |
1554 | bool "Store kernel .data section compressed in ROM" | |
1555 | depends on XIP_KERNEL | |
1556 | select ZLIB_INFLATE | |
1557 | help | |
1558 | Before the kernel is actually executed, its .data section has to be | |
1559 | copied to RAM from ROM. This option allows for storing that data | |
1560 | in compressed form and decompressed to RAM rather than merely being | |
1561 | copied, saving some precious ROM space. A possible drawback is a | |
1562 | slightly longer boot delay. | |
1563 | ||
4183635e ED |
1564 | config ARCH_SUPPORTS_KEXEC |
1565 | def_bool (!SMP || PM_SLEEP_SMP) && MMU | |
c587e4a6 | 1566 | |
4cd9d6f7 RP |
1567 | config ATAGS_PROC |
1568 | bool "Export atags in procfs" | |
bd51e2f5 | 1569 | depends on ATAGS && KEXEC |
b98d7291 | 1570 | default y |
4cd9d6f7 RP |
1571 | help |
1572 | Should the atags used to boot the kernel be exported in an "atags" | |
1573 | file in procfs. Useful with kexec. | |
1574 | ||
4183635e ED |
1575 | config ARCH_SUPPORTS_CRASH_DUMP |
1576 | def_bool y | |
cb5d39b3 | 1577 | |
e69edc79 | 1578 | config AUTO_ZRELADDR |
6fd09c9a AB |
1579 | bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM |
1580 | default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) | |
e69edc79 EM |
1581 | help |
1582 | ZRELADDR is the physical address where the decompressed kernel | |
1583 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
0673cb38 GU |
1584 | will be determined at run-time, either by masking the current IP |
1585 | with 0xf8000000, or, if invalid, from the DTB passed in r2. | |
1586 | This assumes the zImage being placed in the first 128MB from | |
1587 | start of memory. | |
e69edc79 | 1588 | |
81a0bc39 RF |
1589 | config EFI_STUB |
1590 | bool | |
1591 | ||
1592 | config EFI | |
1593 | bool "UEFI runtime support" | |
1594 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
1595 | select UCS2_STRING | |
1596 | select EFI_PARAMS_FROM_FDT | |
1597 | select EFI_STUB | |
2e0eb483 | 1598 | select EFI_GENERIC_STUB |
81a0bc39 | 1599 | select EFI_RUNTIME_WRAPPERS |
a7f7f624 | 1600 | help |
81a0bc39 RF |
1601 | This option provides support for runtime services provided |
1602 | by UEFI firmware (such as non-volatile variables, realtime | |
1603 | clock, and platform reset). A UEFI stub is also provided to | |
1604 | allow the kernel to be booted as an EFI application. This | |
1605 | is only useful for kernels that may run on systems that have | |
1606 | UEFI firmware. | |
1607 | ||
bb817bef AB |
1608 | config DMI |
1609 | bool "Enable support for SMBIOS (DMI) tables" | |
1610 | depends on EFI | |
1611 | default y | |
1612 | help | |
1613 | This enables SMBIOS/DMI feature for systems. | |
1614 | ||
1615 | This option is only useful on systems that have UEFI firmware. | |
1616 | However, even with this option, the resultant kernel should | |
1617 | continue to boot on existing non-UEFI platforms. | |
1618 | ||
1619 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
1620 | i.e., the the practice of identifying the platform via DMI to | |
1621 | decide whether certain workarounds for buggy hardware and/or | |
1622 | firmware need to be enabled. This would require the DMI subsystem | |
1623 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
1624 | ||
1da177e4 LT |
1625 | endmenu |
1626 | ||
ac9d7efc | 1627 | menu "CPU Power Management" |
1da177e4 | 1628 | |
1da177e4 | 1629 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 1630 | |
ac9d7efc RK |
1631 | source "drivers/cpuidle/Kconfig" |
1632 | ||
1633 | endmenu | |
1634 | ||
1da177e4 LT |
1635 | menu "Floating point emulation" |
1636 | ||
1637 | comment "At least one emulation must be selected" | |
1638 | ||
1639 | config FPE_NWFPE | |
1640 | bool "NWFPE math emulation" | |
593c252a | 1641 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
a7f7f624 | 1642 | help |
1da177e4 LT |
1643 | Say Y to include the NWFPE floating point emulator in the kernel. |
1644 | This is necessary to run most binaries. Linux does not currently | |
1645 | support floating point hardware so you need to say Y here even if | |
1646 | your machine has an FPA or floating point co-processor podule. | |
1647 | ||
1648 | You may say N here if you are going to load the Acorn FPEmulator | |
1649 | early in the bootup. | |
1650 | ||
1651 | config FPE_NWFPE_XP | |
1652 | bool "Support extended precision" | |
bedf142b | 1653 | depends on FPE_NWFPE |
1da177e4 LT |
1654 | help |
1655 | Say Y to include 80-bit support in the kernel floating-point | |
1656 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
1657 | Note that gcc does not generate 80-bit operations by default, | |
1658 | so in most cases this option only enlarges the size of the | |
1659 | floating point emulator without any good reason. | |
1660 | ||
1661 | You almost surely want to say N here. | |
1662 | ||
1663 | config FPE_FASTFPE | |
1664 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 1665 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
a7f7f624 | 1666 | help |
1da177e4 LT |
1667 | Say Y here to include the FAST floating point emulator in the kernel. |
1668 | This is an experimental much faster emulator which now also has full | |
1669 | precision for the mantissa. It does not support any exceptions. | |
1670 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
1671 | ||
1672 | It should be sufficient for most programs. It may be not suitable | |
1673 | for scientific calculations, but you have to check this for yourself. | |
1674 | If you do not feel you need a faster FP emulation you should better | |
1675 | choose NWFPE. | |
1676 | ||
1677 | config VFP | |
1678 | bool "VFP-format floating point maths" | |
e399b1a4 | 1679 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
1680 | help |
1681 | Say Y to include VFP support code in the kernel. This is needed | |
1682 | if your hardware includes a VFP unit. | |
1683 | ||
e318b36e | 1684 | Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for |
1da177e4 LT |
1685 | release notes and additional status information. |
1686 | ||
1687 | Say N if your target does not have VFP hardware. | |
1688 | ||
25ebee02 CM |
1689 | config VFPv3 |
1690 | bool | |
1691 | depends on VFP | |
1692 | default y if CPU_V7 | |
1693 | ||
b5872db4 CM |
1694 | config NEON |
1695 | bool "Advanced SIMD (NEON) Extension support" | |
1696 | depends on VFPv3 && CPU_V7 | |
1697 | help | |
1698 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
1699 | Extension. | |
1700 | ||
73c132c1 AB |
1701 | config KERNEL_MODE_NEON |
1702 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 1703 | depends on NEON && AEABI |
73c132c1 AB |
1704 | help |
1705 | Say Y to include support for NEON in kernel mode. | |
1706 | ||
1da177e4 LT |
1707 | endmenu |
1708 | ||
1da177e4 LT |
1709 | menu "Power management options" |
1710 | ||
eceab4ac | 1711 | source "kernel/power/Kconfig" |
1da177e4 | 1712 | |
f4cb5700 | 1713 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 1714 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 1715 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
1716 | def_bool y |
1717 | ||
15e0d9e3 | 1718 | config ARM_CPU_SUSPEND |
8b6f2499 | 1719 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 1720 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 1721 | |
603fb42a SC |
1722 | config ARCH_HIBERNATION_POSSIBLE |
1723 | bool | |
1724 | depends on MMU | |
1725 | default y if ARCH_SUSPEND_POSSIBLE | |
1726 | ||
1da177e4 LT |
1727 | endmenu |
1728 | ||
2cbd1cc3 | 1729 | source "arch/arm/Kconfig.assembler" |