Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | config ARM |
3 | bool | |
4 | default y | |
942fa985 | 5 | select ARCH_32BIT_OFF_T |
1d8f51d4 | 6 | select ARCH_CLOCKSOURCE_DATA |
c7780ab5 | 7 | select ARCH_HAS_DEBUG_VIRTUAL if MMU |
21266be9 | 8 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
2b68f6ca | 9 | select ARCH_HAS_ELF_RANDOMIZE |
ee333554 | 10 | select ARCH_HAS_FORTIFY_SOURCE |
d8ae8a37 | 11 | select ARCH_HAS_KEEPINITRD |
75851720 | 12 | select ARCH_HAS_KCOV |
e69244d2 | 13 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
3010a5ea | 14 | select ARCH_HAS_PTE_SPECIAL if ARM_LPAE |
ea8c64ac | 15 | select ARCH_HAS_PHYS_TO_DMA |
347cb6af | 16 | select ARCH_HAS_SETUP_DMA_OPS |
75851720 | 17 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
18 | select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL |
19 | select ARCH_HAS_STRICT_MODULE_RWX if MMU | |
dc2acded | 20 | select ARCH_HAS_TEARDOWN_DMA_OPS if MMU |
3d06770e | 21 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 22 | select ARCH_HAVE_CUSTOM_GPIO_H |
957e3fac | 23 | select ARCH_HAS_GCOV_PROFILE_ALL |
350e88ba | 24 | select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC |
d7018848 | 25 | select ARCH_MIGHT_HAVE_PC_PARPORT |
7c703e54 | 26 | select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN |
ad21fc4f LA |
27 | select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX |
28 | select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 | |
4badad35 | 29 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 30 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 31 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 32 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 33 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 34 | select CLONE_BACKWARDS |
f00790aa | 35 | select CPU_PM if SUSPEND || CPU_IDLE |
dce5c9e3 | 36 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
ff4c25f2 | 37 | select DMA_DECLARE_COHERENT |
f0edfea8 | 38 | select DMA_REMAP if MMU |
b01aec9b BP |
39 | select EDAC_SUPPORT |
40 | select EDAC_ATOMIC_SCRUB | |
36d0fd21 | 41 | select GENERIC_ALLOCATOR |
2ef7a295 | 42 | select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY |
f00790aa | 43 | select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI |
b1b3f49c | 44 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
ea2d9a96 | 45 | select GENERIC_CPU_AUTOPROBE |
2937367b | 46 | select GENERIC_EARLY_IOREMAP |
171b3f0d | 47 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
48 | select GENERIC_IRQ_PROBE |
49 | select GENERIC_IRQ_SHOW | |
7c07005e | 50 | select GENERIC_IRQ_SHOW_LEVEL |
b1b3f49c | 51 | select GENERIC_PCI_IOMAP |
38ff87f7 | 52 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
53 | select GENERIC_SMP_IDLE_THREAD |
54 | select GENERIC_STRNCPY_FROM_USER | |
55 | select GENERIC_STRNLEN_USER | |
a71b092a | 56 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 57 | select HARDIRQS_SW_RESEND |
f00790aa | 58 | select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT |
0b7857db | 59 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
437682ee AB |
60 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
61 | select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU | |
e0c25d95 | 62 | select HAVE_ARCH_MMAP_RND_BITS if MMU |
f00790aa | 63 | select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT |
08626a60 | 64 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
0693bf68 | 65 | select HAVE_ARCH_TRACEHOOK |
b329f95d | 66 | select HAVE_ARM_SMCCC if CPU_V7 |
39c13c20 | 67 | select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 |
171b3f0d | 68 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
69 | select HAVE_C_RECORDMCOUNT |
70 | select HAVE_DEBUG_KMEMLEAK | |
b1b3f49c | 71 | select HAVE_DMA_CONTIGUOUS if MMU |
f00790aa | 72 | select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU |
620176f3 | 73 | select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE |
dce5c9e3 | 74 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
5f56a5df | 75 | select HAVE_EXIT_THREAD |
f00790aa | 76 | select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL |
50362162 | 77 | select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG |
f00790aa | 78 | select HAVE_FUNCTION_TRACER if !XIP_KERNEL |
6b90bd4b | 79 | select HAVE_GCC_PLUGINS |
f00790aa | 80 | select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) |
b1b3f49c | 81 | select HAVE_IDE if PCI || ISA || PCMCIA |
87c46b6c | 82 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 83 | select HAVE_KERNEL_GZIP |
f9b493ac | 84 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 85 | select HAVE_KERNEL_LZMA |
b1b3f49c | 86 | select HAVE_KERNEL_LZO |
a7f464f3 | 87 | select HAVE_KERNEL_XZ |
cb1293e2 | 88 | select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M |
f00790aa | 89 | select HAVE_KRETPROBES if HAVE_KPROBES |
7d485f64 | 90 | select HAVE_MOD_ARCH_SPECIFIC |
42a0bb3f | 91 | select HAVE_NMI |
f00790aa | 92 | select HAVE_OPROFILE if HAVE_PERF_EVENTS |
0dc016db | 93 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 94 | select HAVE_PERF_EVENTS |
49863894 WD |
95 | select HAVE_PERF_REGS |
96 | select HAVE_PERF_USER_STACK_DUMP | |
f00790aa | 97 | select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE |
e513f8bf | 98 | select HAVE_REGS_AND_STACK_ACCESS_API |
9800b9dc | 99 | select HAVE_RSEQ |
d148eac0 | 100 | select HAVE_STACKPROTECTOR |
b1b3f49c | 101 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 102 | select HAVE_UID16 |
31c1fc81 | 103 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 104 | select IRQ_FORCED_THREADING |
171b3f0d | 105 | select MODULES_USE_ELF_REL |
f616ab59 | 106 | select NEED_DMA_MAP_STATE |
aa7d5f18 | 107 | select OF_EARLY_FLATTREE if OF |
171b3f0d RK |
108 | select OLD_SIGACTION |
109 | select OLD_SIGSUSPEND3 | |
20f1b79d | 110 | select PCI_SYSCALL if PCI |
b1b3f49c | 111 | select PERF_USE_VMALLOC |
b26d07a0 | 112 | select REFCOUNT_FULL |
b1b3f49c RK |
113 | select RTC_LIB |
114 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
115 | # Above selects are sorted alphabetically; please add new ones |
116 | # according to that. Thanks. | |
1da177e4 LT |
117 | help |
118 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 119 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 120 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 121 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
122 | Europe. There is an ARM Linux project with a web page at |
123 | <http://www.arm.linux.org.uk/>. | |
124 | ||
74facffe RK |
125 | config ARM_HAS_SG_CHAIN |
126 | bool | |
127 | ||
4ce63fcd | 128 | config ARM_DMA_USE_IOMMU |
4ce63fcd | 129 | bool |
b1b3f49c RK |
130 | select ARM_HAS_SG_CHAIN |
131 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 132 | |
60460abf SWK |
133 | if ARM_DMA_USE_IOMMU |
134 | ||
135 | config ARM_DMA_IOMMU_ALIGNMENT | |
136 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
137 | range 4 9 | |
138 | default 8 | |
139 | help | |
140 | DMA mapping framework by default aligns all buffers to the smallest | |
141 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
142 | size. This works well for buffers up to a few hundreds kilobytes, but | |
143 | for larger buffers it just a waste of address space. Drivers which has | |
144 | relatively small addressing window (like 64Mib) might run out of | |
145 | virtual space with just a few allocations. | |
146 | ||
147 | With this parameter you can specify the maximum PAGE_SIZE order for | |
148 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
149 | specified order. The order is expressed as a power of two multiplied | |
150 | by the PAGE_SIZE. | |
151 | ||
152 | endif | |
153 | ||
75e7153a RB |
154 | config SYS_SUPPORTS_APM_EMULATION |
155 | bool | |
156 | ||
bc581770 LW |
157 | config HAVE_TCM |
158 | bool | |
159 | select GENERIC_ALLOCATOR | |
160 | ||
e119bfff RK |
161 | config HAVE_PROC_CPU |
162 | bool | |
163 | ||
ce816fa8 | 164 | config NO_IOPORT_MAP |
5ea81769 | 165 | bool |
5ea81769 | 166 | |
1da177e4 LT |
167 | config SBUS |
168 | bool | |
169 | ||
f16fb1ec RK |
170 | config STACKTRACE_SUPPORT |
171 | bool | |
172 | default y | |
173 | ||
174 | config LOCKDEP_SUPPORT | |
175 | bool | |
176 | default y | |
177 | ||
7ad1bcb2 RK |
178 | config TRACE_IRQFLAGS_SUPPORT |
179 | bool | |
cb1293e2 | 180 | default !CPU_V7M |
7ad1bcb2 | 181 | |
f0d1b0b3 DH |
182 | config ARCH_HAS_ILOG2_U32 |
183 | bool | |
f0d1b0b3 DH |
184 | |
185 | config ARCH_HAS_ILOG2_U64 | |
186 | bool | |
f0d1b0b3 | 187 | |
4a1b5733 EV |
188 | config ARCH_HAS_BANDGAP |
189 | bool | |
190 | ||
a5f4c561 SA |
191 | config FIX_EARLYCON_MEM |
192 | def_bool y if MMU | |
193 | ||
b89c3b16 AM |
194 | config GENERIC_HWEIGHT |
195 | bool | |
196 | default y | |
197 | ||
1da177e4 LT |
198 | config GENERIC_CALIBRATE_DELAY |
199 | bool | |
200 | default y | |
201 | ||
a08b6b79 Z |
202 | config ARCH_MAY_HAVE_PC_FDC |
203 | bool | |
204 | ||
5ac6da66 CL |
205 | config ZONE_DMA |
206 | bool | |
5ac6da66 | 207 | |
c7edc9e3 DL |
208 | config ARCH_SUPPORTS_UPROBES |
209 | def_bool y | |
210 | ||
58af4a24 RH |
211 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
212 | bool | |
213 | ||
1da177e4 LT |
214 | config GENERIC_ISA_DMA |
215 | bool | |
216 | ||
1da177e4 LT |
217 | config FIQ |
218 | bool | |
219 | ||
13a5045d RH |
220 | config NEED_RET_TO_USER |
221 | bool | |
222 | ||
034d2f5a AV |
223 | config ARCH_MTD_XIP |
224 | bool | |
225 | ||
dc21af99 | 226 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
227 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
228 | default y | |
b511d75d | 229 | depends on !XIP_KERNEL && MMU |
dc21af99 | 230 | help |
111e9a5c RK |
231 | Patch phys-to-virt and virt-to-phys translation functions at |
232 | boot and module load time according to the position of the | |
233 | kernel in system memory. | |
dc21af99 | 234 | |
111e9a5c | 235 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 236 | of physical memory is at a 16MB boundary. |
dc21af99 | 237 | |
c1becedc RK |
238 | Only disable this option if you know that you do not require |
239 | this feature (eg, building a kernel for a single machine) and | |
240 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 241 | |
c334bc15 RH |
242 | config NEED_MACH_IO_H |
243 | bool | |
244 | help | |
245 | Select this when mach/io.h is required to provide special | |
246 | definitions for this platform. The need for mach/io.h should | |
247 | be avoided when possible. | |
248 | ||
0cdc8b92 | 249 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
250 | bool |
251 | help | |
0cdc8b92 NP |
252 | Select this when mach/memory.h is required to provide special |
253 | definitions for this platform. The need for mach/memory.h should | |
254 | be avoided when possible. | |
dc21af99 | 255 | |
1b9f95f8 | 256 | config PHYS_OFFSET |
974c0724 | 257 | hex "Physical address of main memory" if MMU |
c6f54a9b | 258 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 259 | default DRAM_BASE if !MMU |
c6f54a9b | 260 | default 0x00000000 if ARCH_EBSA110 || \ |
c6f54a9b UKK |
261 | ARCH_FOOTBRIDGE || \ |
262 | ARCH_INTEGRATOR || \ | |
263 | ARCH_IOP13XX || \ | |
264 | ARCH_KS8695 || \ | |
8f2c0062 | 265 | ARCH_REALVIEW |
c6f54a9b UKK |
266 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC |
267 | default 0x20000000 if ARCH_S5PV210 | |
b8824c9a | 268 | default 0xc0000000 if ARCH_SA1100 |
111e9a5c | 269 | help |
1b9f95f8 NP |
270 | Please provide the physical address corresponding to the |
271 | location of main memory in your system. | |
cada3c08 | 272 | |
87e040b6 SG |
273 | config GENERIC_BUG |
274 | def_bool y | |
275 | depends on BUG | |
276 | ||
1bcad26e KS |
277 | config PGTABLE_LEVELS |
278 | int | |
279 | default 3 if ARM_LPAE | |
280 | default 2 | |
281 | ||
1da177e4 LT |
282 | menu "System Type" |
283 | ||
3c427975 HC |
284 | config MMU |
285 | bool "MMU-based Paged Memory Management Support" | |
286 | default y | |
287 | help | |
288 | Select if you want MMU-based virtualised addressing space | |
289 | support by paged memory management. If unsure, say 'Y'. | |
290 | ||
e0c25d95 DC |
291 | config ARCH_MMAP_RND_BITS_MIN |
292 | default 8 | |
293 | ||
294 | config ARCH_MMAP_RND_BITS_MAX | |
295 | default 14 if PAGE_OFFSET=0x40000000 | |
296 | default 15 if PAGE_OFFSET=0x80000000 | |
297 | default 16 | |
298 | ||
ccf50e23 RK |
299 | # |
300 | # The "ARM system type" choice list is ordered alphabetically by option | |
301 | # text. Please add new entries in the option alphabetic order. | |
302 | # | |
1da177e4 LT |
303 | choice |
304 | prompt "ARM system type" | |
70722803 | 305 | default ARM_SINGLE_ARMV7M if !MMU |
1420b22b | 306 | default ARCH_MULTIPLATFORM if MMU |
1da177e4 | 307 | |
387798b3 RH |
308 | config ARCH_MULTIPLATFORM |
309 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 310 | depends on MMU |
42dc836d | 311 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
312 | select ARM_PATCH_PHYS_VIRT |
313 | select AUTO_ZRELADDR | |
bb0eb050 | 314 | select TIMER_OF |
66314223 | 315 | select COMMON_CLK |
ddb902cc | 316 | select GENERIC_CLOCKEVENTS |
4c301f9b | 317 | select GENERIC_IRQ_MULTI_HANDLER |
eb01d42a | 318 | select HAVE_PCI |
2eac9c2d | 319 | select PCI_DOMAINS_GENERIC if PCI |
66314223 DN |
320 | select SPARSE_IRQ |
321 | select USE_OF | |
66314223 | 322 | |
9c77bc43 SA |
323 | config ARM_SINGLE_ARMV7M |
324 | bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" | |
325 | depends on !MMU | |
9c77bc43 | 326 | select ARM_NVIC |
499f1640 | 327 | select AUTO_ZRELADDR |
bb0eb050 | 328 | select TIMER_OF |
9c77bc43 SA |
329 | select COMMON_CLK |
330 | select CPU_V7M | |
331 | select GENERIC_CLOCKEVENTS | |
332 | select NO_IOPORT_MAP | |
333 | select SPARSE_IRQ | |
334 | select USE_OF | |
335 | ||
1da177e4 LT |
336 | config ARCH_EBSA110 |
337 | bool "EBSA-110" | |
b1b3f49c | 338 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 339 | select CPU_SA110 |
f7e68bbf | 340 | select ISA |
c334bc15 | 341 | select NEED_MACH_IO_H |
0cdc8b92 | 342 | select NEED_MACH_MEMORY_H |
ce816fa8 | 343 | select NO_IOPORT_MAP |
1da177e4 LT |
344 | help |
345 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 346 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
347 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
348 | parallel port. | |
349 | ||
e7736d47 LB |
350 | config ARCH_EP93XX |
351 | bool "EP93xx-based" | |
80320927 | 352 | select ARCH_SPARSEMEM_ENABLE |
e7736d47 | 353 | select ARM_AMBA |
cd5bad41 | 354 | imply ARM_PATCH_PHYS_VIRT |
e7736d47 | 355 | select ARM_VIC |
b8824c9a | 356 | select AUTO_ZRELADDR |
6d803ba7 | 357 | select CLKDEV_LOOKUP |
000bc178 | 358 | select CLKSRC_MMIO |
b1b3f49c | 359 | select CPU_ARM920T |
000bc178 | 360 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 361 | select GPIOLIB |
e7736d47 LB |
362 | help |
363 | This enables support for the Cirrus EP93xx series of CPUs. | |
364 | ||
1da177e4 LT |
365 | config ARCH_FOOTBRIDGE |
366 | bool "FootBridge" | |
c750815e | 367 | select CPU_SA110 |
1da177e4 | 368 | select FOOTBRIDGE |
4e8d7637 | 369 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 370 | select HAVE_IDE |
8ef6e620 | 371 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 372 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
373 | help |
374 | Support for systems based on the DC21285 companion chip | |
375 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 376 | |
4af6fee1 DS |
377 | config ARCH_NETX |
378 | bool "Hilscher NetX based" | |
b1b3f49c | 379 | select ARM_VIC |
234b6ced | 380 | select CLKSRC_MMIO |
c750815e | 381 | select CPU_ARM926T |
2fcfe6b8 | 382 | select GENERIC_CLOCKEVENTS |
f999b8bd | 383 | help |
4af6fee1 DS |
384 | This enables support for systems based on the Hilscher NetX Soc |
385 | ||
3b938be6 RK |
386 | config ARCH_IOP13XX |
387 | bool "IOP13xx-based" | |
388 | depends on MMU | |
b1b3f49c | 389 | select CPU_XSC3 |
0cdc8b92 | 390 | select NEED_MACH_MEMORY_H |
13a5045d | 391 | select NEED_RET_TO_USER |
eb01d42a | 392 | select FORCE_PCI |
b1b3f49c RK |
393 | select PLAT_IOP |
394 | select VMSPLIT_1G | |
37ebbcff | 395 | select SPARSE_IRQ |
3b938be6 RK |
396 | help |
397 | Support for Intel's IOP13XX (XScale) family of processors. | |
398 | ||
3f7e5815 LB |
399 | config ARCH_IOP32X |
400 | bool "IOP32x-based" | |
a4f7e763 | 401 | depends on MMU |
c750815e | 402 | select CPU_XSCALE |
e9004f50 | 403 | select GPIO_IOP |
5c34a4e8 | 404 | select GPIOLIB |
13a5045d | 405 | select NEED_RET_TO_USER |
eb01d42a | 406 | select FORCE_PCI |
b1b3f49c | 407 | select PLAT_IOP |
f999b8bd | 408 | help |
3f7e5815 LB |
409 | Support for Intel's 80219 and IOP32X (XScale) family of |
410 | processors. | |
411 | ||
412 | config ARCH_IOP33X | |
413 | bool "IOP33x-based" | |
414 | depends on MMU | |
c750815e | 415 | select CPU_XSCALE |
e9004f50 | 416 | select GPIO_IOP |
5c34a4e8 | 417 | select GPIOLIB |
13a5045d | 418 | select NEED_RET_TO_USER |
eb01d42a | 419 | select FORCE_PCI |
b1b3f49c | 420 | select PLAT_IOP |
3f7e5815 LB |
421 | help |
422 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 423 | |
3b938be6 RK |
424 | config ARCH_IXP4XX |
425 | bool "IXP4xx-based" | |
a4f7e763 | 426 | depends on MMU |
58af4a24 | 427 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
51aaf81f | 428 | select ARCH_SUPPORTS_BIG_ENDIAN |
c750815e | 429 | select CPU_XSCALE |
b1b3f49c | 430 | select DMABOUNCE if PCI |
3b938be6 | 431 | select GENERIC_CLOCKEVENTS |
98ac0cc2 | 432 | select GENERIC_IRQ_MULTI_HANDLER |
55ec465e | 433 | select GPIO_IXP4XX |
5c34a4e8 | 434 | select GPIOLIB |
eb01d42a | 435 | select HAVE_PCI |
55ec465e | 436 | select IXP4XX_IRQ |
65af6667 | 437 | select IXP4XX_TIMER |
c334bc15 | 438 | select NEED_MACH_IO_H |
9296d94d | 439 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 440 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 441 | help |
3b938be6 | 442 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 443 | |
edabd38e SB |
444 | config ARCH_DOVE |
445 | bool "Marvell Dove" | |
756b2531 | 446 | select CPU_PJ4 |
edabd38e | 447 | select GENERIC_CLOCKEVENTS |
4c301f9b | 448 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 449 | select GPIOLIB |
eb01d42a | 450 | select HAVE_PCI |
171b3f0d | 451 | select MVEBU_MBUS |
9139acd1 SH |
452 | select PINCTRL |
453 | select PINCTRL_DOVE | |
abcda1dc | 454 | select PLAT_ORION_LEGACY |
0bd86961 | 455 | select SPARSE_IRQ |
c5d431e8 | 456 | select PM_GENERIC_DOMAINS if PM |
788c9700 | 457 | help |
edabd38e | 458 | Support for the Marvell Dove SoC 88AP510 |
788c9700 RK |
459 | |
460 | config ARCH_KS8695 | |
461 | bool "Micrel/Kendin KS8695" | |
c7e783d6 | 462 | select CLKSRC_MMIO |
b1b3f49c | 463 | select CPU_ARM922T |
c7e783d6 | 464 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 465 | select GPIOLIB |
b1b3f49c | 466 | select NEED_MACH_MEMORY_H |
788c9700 RK |
467 | help |
468 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
469 | System-on-Chip devices. | |
470 | ||
788c9700 RK |
471 | config ARCH_W90X900 |
472 | bool "Nuvoton W90X900 CPU" | |
6d803ba7 | 473 | select CLKDEV_LOOKUP |
6fa5d5f7 | 474 | select CLKSRC_MMIO |
b1b3f49c | 475 | select CPU_ARM926T |
58b5369e | 476 | select GENERIC_CLOCKEVENTS |
5c34a4e8 | 477 | select GPIOLIB |
788c9700 | 478 | help |
a8bc4ead | 479 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
480 | At present, the w90x900 has been renamed nuc900, regarding | |
481 | the ARM series product line, you can login the following | |
482 | link address to know more. | |
483 | ||
484 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
485 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 486 | |
93e22567 RK |
487 | config ARCH_LPC32XX |
488 | bool "NXP LPC32XX" | |
93e22567 RK |
489 | select ARM_AMBA |
490 | select CLKDEV_LOOKUP | |
c227f127 VZ |
491 | select CLKSRC_LPC32XX |
492 | select COMMON_CLK | |
93e22567 RK |
493 | select CPU_ARM926T |
494 | select GENERIC_CLOCKEVENTS | |
4c301f9b | 495 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 496 | select GPIOLIB |
8cb17b5e | 497 | select SPARSE_IRQ |
93e22567 RK |
498 | select USE_OF |
499 | help | |
500 | Support for the NXP LPC32XX family of processors | |
501 | ||
1da177e4 | 502 | config ARCH_PXA |
2c8086a5 | 503 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 504 | depends on MMU |
b1b3f49c | 505 | select ARCH_MTD_XIP |
b1b3f49c RK |
506 | select ARM_CPU_SUSPEND if PM |
507 | select AUTO_ZRELADDR | |
a1c0a6ad | 508 | select COMMON_CLK |
6d803ba7 | 509 | select CLKDEV_LOOKUP |
389d9b58 | 510 | select CLKSRC_PXA |
234b6ced | 511 | select CLKSRC_MMIO |
bb0eb050 | 512 | select TIMER_OF |
2f202861 | 513 | select CPU_XSCALE if !CPU_XSC3 |
981d0f39 | 514 | select GENERIC_CLOCKEVENTS |
4c301f9b | 515 | select GENERIC_IRQ_MULTI_HANDLER |
157d2644 | 516 | select GPIO_PXA |
5c34a4e8 | 517 | select GPIOLIB |
d0ee9f40 | 518 | select HAVE_IDE |
d6cf30ca | 519 | select IRQ_DOMAIN |
b1b3f49c RK |
520 | select PLAT_PXA |
521 | select SPARSE_IRQ | |
f999b8bd | 522 | help |
2c8086a5 | 523 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 LT |
524 | |
525 | config ARCH_RPC | |
526 | bool "RiscPC" | |
868e87cc | 527 | depends on MMU |
1da177e4 | 528 | select ARCH_ACORN |
a08b6b79 | 529 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 530 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 531 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 532 | select CPU_SA110 |
b1b3f49c | 533 | select FIQ |
d0ee9f40 | 534 | select HAVE_IDE |
b1b3f49c RK |
535 | select HAVE_PATA_PLATFORM |
536 | select ISA_DMA_API | |
c334bc15 | 537 | select NEED_MACH_IO_H |
0cdc8b92 | 538 | select NEED_MACH_MEMORY_H |
ce816fa8 | 539 | select NO_IOPORT_MAP |
1da177e4 LT |
540 | help |
541 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
542 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
543 | ||
544 | config ARCH_SA1100 | |
545 | bool "SA1100-based" | |
b1b3f49c | 546 | select ARCH_MTD_XIP |
b1b3f49c RK |
547 | select ARCH_SPARSEMEM_ENABLE |
548 | select CLKDEV_LOOKUP | |
549 | select CLKSRC_MMIO | |
389d9b58 | 550 | select CLKSRC_PXA |
bb0eb050 | 551 | select TIMER_OF if OF |
1937f5b9 | 552 | select CPU_FREQ |
b1b3f49c | 553 | select CPU_SA1100 |
3e238be2 | 554 | select GENERIC_CLOCKEVENTS |
4c301f9b | 555 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 556 | select GPIOLIB |
d0ee9f40 | 557 | select HAVE_IDE |
1eca42b4 | 558 | select IRQ_DOMAIN |
b1b3f49c | 559 | select ISA |
0cdc8b92 | 560 | select NEED_MACH_MEMORY_H |
375dec92 | 561 | select SPARSE_IRQ |
f999b8bd MM |
562 | help |
563 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 564 | |
b130d5c2 KK |
565 | config ARCH_S3C24XX |
566 | bool "Samsung S3C24XX SoCs" | |
335cce74 | 567 | select ATAGS |
b1b3f49c | 568 | select CLKDEV_LOOKUP |
4280506a | 569 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 570 | select GENERIC_CLOCKEVENTS |
880cf071 | 571 | select GPIO_SAMSUNG |
5c34a4e8 | 572 | select GPIOLIB |
4c301f9b | 573 | select GENERIC_IRQ_MULTI_HANDLER |
20676c15 | 574 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 575 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 576 | select HAVE_S3C_RTC if RTC_CLASS |
c334bc15 | 577 | select NEED_MACH_IO_H |
cd8dc7ae | 578 | select SAMSUNG_ATAGS |
ea04d6b4 | 579 | select USE_OF |
1da177e4 | 580 | help |
b130d5c2 KK |
581 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
582 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
583 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
584 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 585 | |
7c6337e2 KH |
586 | config ARCH_DAVINCI |
587 | bool "TI DaVinci" | |
b1b3f49c | 588 | select ARCH_HAS_HOLES_MEMORYMODEL |
27823278 | 589 | select COMMON_CLK |
ce32c5c5 | 590 | select CPU_ARM926T |
20e9969b | 591 | select GENERIC_ALLOCATOR |
b1b3f49c | 592 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 593 | select GENERIC_IRQ_CHIP |
d0064594 | 594 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 595 | select GPIOLIB |
b1b3f49c | 596 | select HAVE_IDE |
27823278 DL |
597 | select PM_GENERIC_DOMAINS if PM |
598 | select PM_GENERIC_DOMAINS_OF if PM && OF | |
2dbed152 | 599 | select REGMAP_MMIO |
27823278 | 600 | select RESET_CONTROLLER |
e87addec | 601 | select SPARSE_IRQ |
689e331f | 602 | select USE_OF |
b1b3f49c | 603 | select ZONE_DMA |
7c6337e2 KH |
604 | help |
605 | Support for TI's DaVinci platform. | |
606 | ||
a0694861 TL |
607 | config ARCH_OMAP1 |
608 | bool "TI OMAP1" | |
00a36698 | 609 | depends on MMU |
9af915da | 610 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 611 | select ARCH_OMAP |
b1b3f49c | 612 | select CLKDEV_LOOKUP |
d6e15d78 | 613 | select CLKSRC_MMIO |
b1b3f49c | 614 | select GENERIC_CLOCKEVENTS |
a0694861 | 615 | select GENERIC_IRQ_CHIP |
4c301f9b | 616 | select GENERIC_IRQ_MULTI_HANDLER |
5c34a4e8 | 617 | select GPIOLIB |
a0694861 TL |
618 | select HAVE_IDE |
619 | select IRQ_DOMAIN | |
620 | select NEED_MACH_IO_H if PCCARD | |
621 | select NEED_MACH_MEMORY_H | |
685e2d08 | 622 | select SPARSE_IRQ |
21f47fbc | 623 | help |
a0694861 | 624 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 625 | |
1da177e4 LT |
626 | endchoice |
627 | ||
387798b3 RH |
628 | menu "Multiple platform selection" |
629 | depends on ARCH_MULTIPLATFORM | |
630 | ||
631 | comment "CPU Core family selection" | |
632 | ||
f8afae40 AB |
633 | config ARCH_MULTI_V4 |
634 | bool "ARMv4 based platforms (FA526)" | |
635 | depends on !ARCH_MULTI_V6_V7 | |
636 | select ARCH_MULTI_V4_V5 | |
637 | select CPU_FA526 | |
638 | ||
387798b3 RH |
639 | config ARCH_MULTI_V4T |
640 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 641 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 642 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
643 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
644 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
645 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
646 | |
647 | config ARCH_MULTI_V5 | |
648 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 649 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 650 | select ARCH_MULTI_V4_V5 |
12567bbd | 651 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
652 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
653 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
654 | |
655 | config ARCH_MULTI_V4_V5 | |
656 | bool | |
657 | ||
658 | config ARCH_MULTI_V6 | |
8dda05cc | 659 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 660 | select ARCH_MULTI_V6_V7 |
42f4754a | 661 | select CPU_V6K |
387798b3 RH |
662 | |
663 | config ARCH_MULTI_V7 | |
8dda05cc | 664 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
665 | default y |
666 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 667 | select CPU_V7 |
90bc8ac7 | 668 | select HAVE_SMP |
387798b3 RH |
669 | |
670 | config ARCH_MULTI_V6_V7 | |
671 | bool | |
9352b05b | 672 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
673 | |
674 | config ARCH_MULTI_CPU_AUTO | |
675 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
676 | select ARCH_MULTI_V5 | |
677 | ||
678 | endmenu | |
679 | ||
05e2a3de | 680 | config ARCH_VIRT |
e3246542 MY |
681 | bool "Dummy Virtual Machine" |
682 | depends on ARCH_MULTI_V7 | |
4b8b5f25 | 683 | select ARM_AMBA |
05e2a3de | 684 | select ARM_GIC |
3ee80364 | 685 | select ARM_GIC_V2M if PCI |
0b28f1db | 686 | select ARM_GIC_V3 |
bb29cecb | 687 | select ARM_GIC_V3_ITS if PCI |
05e2a3de | 688 | select ARM_PSCI |
4b8b5f25 | 689 | select HAVE_ARM_ARCH_TIMER |
8e2649d0 | 690 | select ARCH_SUPPORTS_BIG_ENDIAN |
05e2a3de | 691 | |
ccf50e23 RK |
692 | # |
693 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
694 | # Kconfigs may be included either alphabetically (according to the | |
695 | # plat- suffix) or along side the corresponding mach-* source. | |
696 | # | |
6bb8536c AF |
697 | source "arch/arm/mach-actions/Kconfig" |
698 | ||
445d9b30 TZ |
699 | source "arch/arm/mach-alpine/Kconfig" |
700 | ||
590b460c LP |
701 | source "arch/arm/mach-artpec/Kconfig" |
702 | ||
d9bfc86d OR |
703 | source "arch/arm/mach-asm9260/Kconfig" |
704 | ||
a66c51f9 AB |
705 | source "arch/arm/mach-aspeed/Kconfig" |
706 | ||
95b8f20f RK |
707 | source "arch/arm/mach-at91/Kconfig" |
708 | ||
1d22924e AB |
709 | source "arch/arm/mach-axxia/Kconfig" |
710 | ||
8ac49e04 CD |
711 | source "arch/arm/mach-bcm/Kconfig" |
712 | ||
1c37fa10 SH |
713 | source "arch/arm/mach-berlin/Kconfig" |
714 | ||
1da177e4 LT |
715 | source "arch/arm/mach-clps711x/Kconfig" |
716 | ||
d94f944e AV |
717 | source "arch/arm/mach-cns3xxx/Kconfig" |
718 | ||
95b8f20f RK |
719 | source "arch/arm/mach-davinci/Kconfig" |
720 | ||
df8d742e BS |
721 | source "arch/arm/mach-digicolor/Kconfig" |
722 | ||
95b8f20f RK |
723 | source "arch/arm/mach-dove/Kconfig" |
724 | ||
e7736d47 LB |
725 | source "arch/arm/mach-ep93xx/Kconfig" |
726 | ||
a66c51f9 AB |
727 | source "arch/arm/mach-exynos/Kconfig" |
728 | source "arch/arm/plat-samsung/Kconfig" | |
729 | ||
1da177e4 LT |
730 | source "arch/arm/mach-footbridge/Kconfig" |
731 | ||
59d3a193 PZ |
732 | source "arch/arm/mach-gemini/Kconfig" |
733 | ||
387798b3 RH |
734 | source "arch/arm/mach-highbank/Kconfig" |
735 | ||
389ee0c2 HZ |
736 | source "arch/arm/mach-hisi/Kconfig" |
737 | ||
a66c51f9 AB |
738 | source "arch/arm/mach-imx/Kconfig" |
739 | ||
1da177e4 LT |
740 | source "arch/arm/mach-integrator/Kconfig" |
741 | ||
a66c51f9 AB |
742 | source "arch/arm/mach-iop13xx/Kconfig" |
743 | ||
3f7e5815 LB |
744 | source "arch/arm/mach-iop32x/Kconfig" |
745 | ||
746 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 LT |
747 | |
748 | source "arch/arm/mach-ixp4xx/Kconfig" | |
749 | ||
828989ad SS |
750 | source "arch/arm/mach-keystone/Kconfig" |
751 | ||
95b8f20f RK |
752 | source "arch/arm/mach-ks8695/Kconfig" |
753 | ||
a66c51f9 AB |
754 | source "arch/arm/mach-mediatek/Kconfig" |
755 | ||
3b8f5030 CC |
756 | source "arch/arm/mach-meson/Kconfig" |
757 | ||
9fb29c73 ST |
758 | source "arch/arm/mach-milbeaut/Kconfig" |
759 | ||
a66c51f9 | 760 | source "arch/arm/mach-mmp/Kconfig" |
17723fd3 | 761 | |
a66c51f9 | 762 | source "arch/arm/mach-moxart/Kconfig" |
8c2ed9bc | 763 | |
794d15b2 SS |
764 | source "arch/arm/mach-mv78xx0/Kconfig" |
765 | ||
a66c51f9 | 766 | source "arch/arm/mach-mvebu/Kconfig" |
f682a218 | 767 | |
1d3f33d5 SG |
768 | source "arch/arm/mach-mxs/Kconfig" |
769 | ||
95b8f20f | 770 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 771 | |
95b8f20f | 772 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 773 | |
7bffa14c BH |
774 | source "arch/arm/mach-npcm/Kconfig" |
775 | ||
9851ca57 DT |
776 | source "arch/arm/mach-nspire/Kconfig" |
777 | ||
d48af15e TL |
778 | source "arch/arm/plat-omap/Kconfig" |
779 | ||
780 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 781 | |
1dbae815 TL |
782 | source "arch/arm/mach-omap2/Kconfig" |
783 | ||
9dd0b194 | 784 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 785 | |
a66c51f9 AB |
786 | source "arch/arm/mach-oxnas/Kconfig" |
787 | ||
387798b3 RH |
788 | source "arch/arm/mach-picoxcell/Kconfig" |
789 | ||
a66c51f9 AB |
790 | source "arch/arm/mach-prima2/Kconfig" |
791 | ||
95b8f20f RK |
792 | source "arch/arm/mach-pxa/Kconfig" |
793 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 794 | |
8fc1b0f8 KG |
795 | source "arch/arm/mach-qcom/Kconfig" |
796 | ||
78e3dbc1 AF |
797 | source "arch/arm/mach-rda/Kconfig" |
798 | ||
95b8f20f RK |
799 | source "arch/arm/mach-realview/Kconfig" |
800 | ||
d63dc051 HS |
801 | source "arch/arm/mach-rockchip/Kconfig" |
802 | ||
a66c51f9 AB |
803 | source "arch/arm/mach-s3c24xx/Kconfig" |
804 | ||
805 | source "arch/arm/mach-s3c64xx/Kconfig" | |
806 | ||
807 | source "arch/arm/mach-s5pv210/Kconfig" | |
808 | ||
95b8f20f | 809 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 810 | |
a66c51f9 AB |
811 | source "arch/arm/mach-shmobile/Kconfig" |
812 | ||
387798b3 RH |
813 | source "arch/arm/mach-socfpga/Kconfig" |
814 | ||
a7ed099f | 815 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 816 | |
65ebcc11 SK |
817 | source "arch/arm/mach-sti/Kconfig" |
818 | ||
bcb84fb4 AT |
819 | source "arch/arm/mach-stm32/Kconfig" |
820 | ||
3b52634f MR |
821 | source "arch/arm/mach-sunxi/Kconfig" |
822 | ||
d6de5b02 MG |
823 | source "arch/arm/mach-tango/Kconfig" |
824 | ||
c5f80065 EG |
825 | source "arch/arm/mach-tegra/Kconfig" |
826 | ||
95b8f20f | 827 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 828 | |
ba56a987 MY |
829 | source "arch/arm/mach-uniphier/Kconfig" |
830 | ||
95b8f20f | 831 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
832 | |
833 | source "arch/arm/mach-versatile/Kconfig" | |
834 | ||
ceade897 | 835 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 836 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 837 | |
6f35f9a9 TP |
838 | source "arch/arm/mach-vt8500/Kconfig" |
839 | ||
7ec80ddf | 840 | source "arch/arm/mach-w90x900/Kconfig" |
841 | ||
acede515 JN |
842 | source "arch/arm/mach-zx/Kconfig" |
843 | ||
9a45eb69 JC |
844 | source "arch/arm/mach-zynq/Kconfig" |
845 | ||
499f1640 SA |
846 | # ARMv7-M architecture |
847 | config ARCH_EFM32 | |
848 | bool "Energy Micro efm32" | |
849 | depends on ARM_SINGLE_ARMV7M | |
5c34a4e8 | 850 | select GPIOLIB |
499f1640 SA |
851 | help |
852 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
853 | processors. | |
854 | ||
855 | config ARCH_LPC18XX | |
856 | bool "NXP LPC18xx/LPC43xx" | |
857 | depends on ARM_SINGLE_ARMV7M | |
858 | select ARCH_HAS_RESET_CONTROLLER | |
859 | select ARM_AMBA | |
860 | select CLKSRC_LPC32XX | |
861 | select PINCTRL | |
862 | help | |
863 | Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 | |
864 | high performance microcontrollers. | |
865 | ||
1847119d | 866 | config ARCH_MPS2 |
17bd274e | 867 | bool "ARM MPS2 platform" |
1847119d VM |
868 | depends on ARM_SINGLE_ARMV7M |
869 | select ARM_AMBA | |
870 | select CLKSRC_MPS2 | |
871 | help | |
872 | Support for Cortex-M Prototyping System (or V2M-MPS2) which comes | |
873 | with a range of available cores like Cortex-M3/M4/M7. | |
874 | ||
875 | Please, note that depends which Application Note is used memory map | |
876 | for the platform may vary, so adjustment of RAM base might be needed. | |
877 | ||
1da177e4 LT |
878 | # Definitions to make life easier |
879 | config ARCH_ACORN | |
880 | bool | |
881 | ||
7ae1f7ec LB |
882 | config PLAT_IOP |
883 | bool | |
469d3044 | 884 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 885 | |
69b02f6a LB |
886 | config PLAT_ORION |
887 | bool | |
bfe45e0b | 888 | select CLKSRC_MMIO |
b1b3f49c | 889 | select COMMON_CLK |
dc7ad3b3 | 890 | select GENERIC_IRQ_CHIP |
278b45b0 | 891 | select IRQ_DOMAIN |
69b02f6a | 892 | |
abcda1dc TP |
893 | config PLAT_ORION_LEGACY |
894 | bool | |
895 | select PLAT_ORION | |
896 | ||
bd5ce433 EM |
897 | config PLAT_PXA |
898 | bool | |
899 | ||
f4b8b319 RK |
900 | config PLAT_VERSATILE |
901 | bool | |
902 | ||
8636a1f9 | 903 | source "arch/arm/mm/Kconfig" |
1da177e4 | 904 | |
afe4b25e | 905 | config IWMMXT |
d93003e8 SH |
906 | bool "Enable iWMMXt support" |
907 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
908 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
909 | help |
910 | Enable support for iWMMXt context switching at run time if | |
911 | running on a CPU that supports it. | |
912 | ||
3b93e7b0 HC |
913 | if !MMU |
914 | source "arch/arm/Kconfig-nommu" | |
915 | endif | |
916 | ||
3e0a07f8 GC |
917 | config PJ4B_ERRATA_4742 |
918 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
919 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
920 | default y | |
921 | help | |
922 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
923 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
924 | the retiring WFI/WFE instructions and the newly issued subsequent | |
925 | instructions. This sensitivity can result in a CPU hang scenario. | |
926 | Workaround: | |
927 | The software must insert either a Data Synchronization Barrier (DSB) | |
928 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
929 | instruction | |
930 | ||
f0c4b8d6 WD |
931 | config ARM_ERRATA_326103 |
932 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
933 | depends on CPU_V6 | |
934 | help | |
935 | Executing a SWP instruction to read-only memory does not set bit 11 | |
936 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
937 | treat the access as a read, preventing a COW from occurring and | |
938 | causing the faulting task to livelock. | |
939 | ||
9cba3ccc CM |
940 | config ARM_ERRATA_411920 |
941 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 942 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
943 | help |
944 | Invalidation of the Instruction Cache operation can | |
945 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
946 | It does not affect the MPCore. This option enables the ARM Ltd. | |
947 | recommended workaround. | |
948 | ||
7ce236fc CM |
949 | config ARM_ERRATA_430973 |
950 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
951 | depends on CPU_V7 | |
952 | help | |
953 | This option enables the workaround for the 430973 Cortex-A8 | |
79403cda | 954 | r1p* erratum. If a code sequence containing an ARM/Thumb |
7ce236fc CM |
955 | interworking branch is replaced with another code sequence at the |
956 | same virtual address, whether due to self-modifying code or virtual | |
957 | to physical address re-mapping, Cortex-A8 does not recover from the | |
958 | stale interworking branch prediction. This results in Cortex-A8 | |
959 | executing the new code sequence in the incorrect ARM or Thumb state. | |
960 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
961 | and also flushes the branch target cache at every context switch. | |
962 | Note that setting specific bits in the ACTLR register may not be | |
963 | available in non-secure mode. | |
964 | ||
855c551f CM |
965 | config ARM_ERRATA_458693 |
966 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
967 | depends on CPU_V7 | |
62e4d357 | 968 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
969 | help |
970 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
971 | erratum. For very specific sequences of memory operations, it is | |
972 | possible for a hazard condition intended for a cache line to instead | |
973 | be incorrectly associated with a different cache line. This false | |
974 | hazard might then cause a processor deadlock. The workaround enables | |
975 | the L1 caching of the NEON accesses and disables the PLD instruction | |
976 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
977 | register may not be available in non-secure mode. | |
978 | ||
0516e464 CM |
979 | config ARM_ERRATA_460075 |
980 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
981 | depends on CPU_V7 | |
62e4d357 | 982 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
983 | help |
984 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
985 | erratum. Any asynchronous access to the L2 cache may encounter a | |
986 | situation in which recent store transactions to the L2 cache are lost | |
987 | and overwritten with stale memory contents from external memory. The | |
988 | workaround disables the write-allocate mode for the L2 cache via the | |
989 | ACTLR register. Note that setting specific bits in the ACTLR register | |
990 | may not be available in non-secure mode. | |
991 | ||
9f05027c WD |
992 | config ARM_ERRATA_742230 |
993 | bool "ARM errata: DMB operation may be faulty" | |
994 | depends on CPU_V7 && SMP | |
62e4d357 | 995 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
996 | help |
997 | This option enables the workaround for the 742230 Cortex-A9 | |
998 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
999 | between two write operations may not ensure the correct visibility | |
1000 | ordering of the two writes. This workaround sets a specific bit in | |
1001 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1002 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1003 | the two writes. | |
1004 | ||
a672e99b WD |
1005 | config ARM_ERRATA_742231 |
1006 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1007 | depends on CPU_V7 && SMP | |
62e4d357 | 1008 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1009 | help |
1010 | This option enables the workaround for the 742231 Cortex-A9 | |
1011 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1012 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1013 | accessing some data located in the same cache line, may get corrupted | |
1014 | data due to bad handling of the address hazard when the line gets | |
1015 | replaced from one of the CPUs at the same time as another CPU is | |
1016 | accessing it. This workaround sets specific bits in the diagnostic | |
1017 | register of the Cortex-A9 which reduces the linefill issuing | |
1018 | capabilities of the processor. | |
1019 | ||
69155794 JM |
1020 | config ARM_ERRATA_643719 |
1021 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1022 | depends on CPU_V7 && SMP | |
e5a5de44 | 1023 | default y |
69155794 JM |
1024 | help |
1025 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1026 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1027 | register returns zero when it should return one. The workaround | |
1028 | corrects this value, ensuring cache maintenance operations which use | |
1029 | it behave as intended and avoiding data corruption. | |
1030 | ||
cdf357f1 WD |
1031 | config ARM_ERRATA_720789 |
1032 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1033 | depends on CPU_V7 |
cdf357f1 WD |
1034 | help |
1035 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1036 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1037 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1038 | As a consequence of this erratum, some TLB entries which should be | |
1039 | invalidated are not, resulting in an incoherency in the system page | |
1040 | tables. The workaround changes the TLB flushing routines to invalidate | |
1041 | entries regardless of the ASID. | |
475d92fc WD |
1042 | |
1043 | config ARM_ERRATA_743622 | |
1044 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1045 | depends on CPU_V7 | |
62e4d357 | 1046 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1047 | help |
1048 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1049 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1050 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1051 | corruption. This workaround sets a specific bit in the diagnostic | |
1052 | register of the Cortex-A9 which disables the Store Buffer | |
1053 | optimisation, preventing the defect from occurring. This has no | |
1054 | visible impact on the overall performance or power consumption of the | |
1055 | processor. | |
1056 | ||
9a27c27c WD |
1057 | config ARM_ERRATA_751472 |
1058 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1059 | depends on CPU_V7 |
62e4d357 | 1060 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1061 | help |
1062 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1063 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1064 | completion of a following broadcasted operation if the second | |
1065 | operation is received by a CPU before the ICIALLUIS has completed, | |
1066 | potentially leading to corrupted entries in the cache or TLB. | |
1067 | ||
fcbdc5fe WD |
1068 | config ARM_ERRATA_754322 |
1069 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1070 | depends on CPU_V7 | |
1071 | help | |
1072 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1073 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1074 | which starts prior to an ASID switch but completes afterwards. This | |
1075 | can populate the micro-TLB with a stale entry which may be hit with | |
1076 | the new ASID. This workaround places two dsb instructions in the mm | |
1077 | switching code so that no page table walks can cross the ASID switch. | |
1078 | ||
5dab26af WD |
1079 | config ARM_ERRATA_754327 |
1080 | bool "ARM errata: no automatic Store Buffer drain" | |
1081 | depends on CPU_V7 && SMP | |
1082 | help | |
1083 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1084 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1085 | mechanism and therefore a livelock may occur if an external agent | |
1086 | continuously polls a memory location waiting to observe an update. | |
1087 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1088 | written polling loops from denying visibility of updates to memory. | |
1089 | ||
145e10e1 CM |
1090 | config ARM_ERRATA_364296 |
1091 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1092 | depends on CPU_V6 |
145e10e1 CM |
1093 | help |
1094 | This options enables the workaround for the 364296 ARM1136 | |
1095 | r0p2 erratum (possible cache data corruption with | |
1096 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1097 | the auxiliary control register and the FI bit in the control | |
1098 | register, thus disabling hit-under-miss without putting the | |
1099 | processor into full low interrupt latency mode. ARM11MPCore | |
1100 | is not affected. | |
1101 | ||
f630c1bd WD |
1102 | config ARM_ERRATA_764369 |
1103 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1104 | depends on CPU_V7 && SMP | |
1105 | help | |
1106 | This option enables the workaround for erratum 764369 | |
1107 | affecting Cortex-A9 MPCore with two or more processors (all | |
1108 | current revisions). Under certain timing circumstances, a data | |
1109 | cache line maintenance operation by MVA targeting an Inner | |
1110 | Shareable memory region may fail to proceed up to either the | |
1111 | Point of Coherency or to the Point of Unification of the | |
1112 | system. This workaround adds a DSB instruction before the | |
1113 | relevant cache maintenance functions and sets a specific bit | |
1114 | in the diagnostic control register of the SCU. | |
1115 | ||
7253b85c SH |
1116 | config ARM_ERRATA_775420 |
1117 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1118 | depends on CPU_V7 | |
1119 | help | |
1120 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1121 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1122 | operation aborts with MMU exception, it might cause the processor | |
1123 | to deadlock. This workaround puts DSB before executing ISB if | |
1124 | an abort may occur on cache maintenance. | |
1125 | ||
93dc6887 CM |
1126 | config ARM_ERRATA_798181 |
1127 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1128 | depends on CPU_V7 && SMP | |
1129 | help | |
1130 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1131 | adequately shooting down all use of the old entries. This | |
1132 | option enables the Linux kernel workaround for this erratum | |
1133 | which sends an IPI to the CPUs that are running the same ASID | |
1134 | as the one being invalidated. | |
1135 | ||
84b6504f WD |
1136 | config ARM_ERRATA_773022 |
1137 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1138 | depends on CPU_V7 | |
1139 | help | |
1140 | This option enables the workaround for the 773022 Cortex-A15 | |
1141 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1142 | loop buffer may deliver incorrect instructions. This | |
1143 | workaround disables the loop buffer to avoid the erratum. | |
1144 | ||
62c0f4a5 DA |
1145 | config ARM_ERRATA_818325_852422 |
1146 | bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" | |
1147 | depends on CPU_V7 | |
1148 | help | |
1149 | This option enables the workaround for: | |
1150 | - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM | |
1151 | instruction might deadlock. Fixed in r0p1. | |
1152 | - Cortex-A12 852422: Execution of a sequence of instructions might | |
1153 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1154 | any Cortex-A12 cores yet. | |
1155 | This workaround for all both errata involves setting bit[12] of the | |
1156 | Feature Register. This bit disables an optimisation applied to a | |
1157 | sequence of 2 instructions that use opposing condition codes. | |
1158 | ||
416bcf21 DA |
1159 | config ARM_ERRATA_821420 |
1160 | bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" | |
1161 | depends on CPU_V7 | |
1162 | help | |
1163 | This option enables the workaround for the 821420 Cortex-A12 | |
1164 | (all revs) erratum. In very rare timing conditions, a sequence | |
1165 | of VMOV to Core registers instructions, for which the second | |
1166 | one is in the shadow of a branch or abort, can lead to a | |
1167 | deadlock when the VMOV instructions are issued out-of-order. | |
1168 | ||
9f6f9354 DA |
1169 | config ARM_ERRATA_825619 |
1170 | bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" | |
1171 | depends on CPU_V7 | |
1172 | help | |
1173 | This option enables the workaround for the 825619 Cortex-A12 | |
1174 | (all revs) erratum. Within rare timing constraints, executing a | |
1175 | DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable | |
1176 | and Device/Strongly-Ordered loads and stores might cause deadlock | |
1177 | ||
1178 | config ARM_ERRATA_852421 | |
1179 | bool "ARM errata: A17: DMB ST might fail to create order between stores" | |
1180 | depends on CPU_V7 | |
1181 | help | |
1182 | This option enables the workaround for the 852421 Cortex-A17 | |
1183 | (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, | |
1184 | execution of a DMB ST instruction might fail to properly order | |
1185 | stores from GroupA and stores from GroupB. | |
1186 | ||
62c0f4a5 DA |
1187 | config ARM_ERRATA_852423 |
1188 | bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" | |
1189 | depends on CPU_V7 | |
1190 | help | |
1191 | This option enables the workaround for: | |
1192 | - Cortex-A17 852423: Execution of a sequence of instructions might | |
1193 | lead to either a data corruption or a CPU deadlock. Not fixed in | |
1194 | any Cortex-A17 cores yet. | |
1195 | This is identical to Cortex-A12 erratum 852422. It is a separate | |
1196 | config option from the A12 erratum due to the way errata are checked | |
1197 | for and handled. | |
1198 | ||
1da177e4 LT |
1199 | endmenu |
1200 | ||
1201 | source "arch/arm/common/Kconfig" | |
1202 | ||
1da177e4 LT |
1203 | menu "Bus support" |
1204 | ||
1da177e4 LT |
1205 | config ISA |
1206 | bool | |
1da177e4 LT |
1207 | help |
1208 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1209 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1210 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1211 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1212 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1213 | ||
065909b9 | 1214 | # Select ISA DMA controller support |
1da177e4 LT |
1215 | config ISA_DMA |
1216 | bool | |
065909b9 | 1217 | select ISA_DMA_API |
1da177e4 | 1218 | |
065909b9 | 1219 | # Select ISA DMA interface |
5cae841b AV |
1220 | config ISA_DMA_API |
1221 | bool | |
5cae841b | 1222 | |
b080ac8a MRJ |
1223 | config PCI_NANOENGINE |
1224 | bool "BSE nanoEngine PCI support" | |
1225 | depends on SA1100_NANOENGINE | |
1226 | help | |
1227 | Enable PCI on the BSE nanoEngine board. | |
1228 | ||
a0113a99 MR |
1229 | config PCI_HOST_ITE8152 |
1230 | bool | |
1231 | depends on PCI && MACH_ARMCORE | |
1232 | default y | |
1233 | select DMABOUNCE | |
1234 | ||
1da177e4 LT |
1235 | endmenu |
1236 | ||
1237 | menu "Kernel Features" | |
1238 | ||
3b55658a DM |
1239 | config HAVE_SMP |
1240 | bool | |
1241 | help | |
1242 | This option should be selected by machines which have an SMP- | |
1243 | capable CPU. | |
1244 | ||
1245 | The only effect of this option is to make the SMP-related | |
1246 | options available to the user for configuration. | |
1247 | ||
1da177e4 | 1248 | config SMP |
bb2d8130 | 1249 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1250 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1251 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1252 | depends on HAVE_SMP |
801bb21c | 1253 | depends on MMU || ARM_MPU |
0361748f | 1254 | select IRQ_WORK |
1da177e4 LT |
1255 | help |
1256 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1257 | a system with only one CPU, say N. If you have a system with more |
1258 | than one CPU, say Y. | |
1da177e4 | 1259 | |
4a474157 | 1260 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1261 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1262 | you say Y here, the kernel will run on many, but not all, |
1263 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1264 | will run faster if you say N here. | |
1da177e4 | 1265 | |
395cf969 | 1266 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
ecf38679 | 1267 | <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at |
50a23e6e | 1268 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1269 | |
1270 | If you don't know what to do here, say N. | |
1271 | ||
f00ec48f | 1272 | config SMP_ON_UP |
5744ff43 | 1273 | bool "Allow booting SMP kernel on uniprocessor systems" |
801bb21c | 1274 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1275 | default y |
1276 | help | |
1277 | SMP kernels contain instructions which fail on non-SMP processors. | |
1278 | Enabling this option allows the kernel to modify itself to make | |
1279 | these instructions safe. Disabling it allows about 1K of space | |
1280 | savings. | |
1281 | ||
1282 | If you don't know what to do here, say Y. | |
1283 | ||
c9018aab VG |
1284 | config ARM_CPU_TOPOLOGY |
1285 | bool "Support cpu topology definition" | |
1286 | depends on SMP && CPU_V7 | |
1287 | default y | |
1288 | help | |
1289 | Support ARM cpu topology definition. The MPIDR register defines | |
1290 | affinity between processors which is then used to describe the cpu | |
1291 | topology of an ARM System. | |
1292 | ||
1293 | config SCHED_MC | |
1294 | bool "Multi-core scheduler support" | |
1295 | depends on ARM_CPU_TOPOLOGY | |
1296 | help | |
1297 | Multi-core scheduler support improves the CPU scheduler's decision | |
1298 | making when dealing with multi-core CPU chips at a cost of slightly | |
1299 | increased overhead in some places. If unsure say N here. | |
1300 | ||
1301 | config SCHED_SMT | |
1302 | bool "SMT scheduler support" | |
1303 | depends on ARM_CPU_TOPOLOGY | |
1304 | help | |
1305 | Improves the CPU scheduler's decision making when dealing with | |
1306 | MultiThreading at a cost of slightly increased overhead in some | |
1307 | places. If unsure say N here. | |
1308 | ||
a8cbcd92 RK |
1309 | config HAVE_ARM_SCU |
1310 | bool | |
a8cbcd92 | 1311 | help |
8f433ec4 | 1312 | This option enables support for the ARM snoop control unit |
a8cbcd92 | 1313 | |
8a4da6e3 | 1314 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1315 | bool "Architected timer support" |
1316 | depends on CPU_V7 | |
8a4da6e3 | 1317 | select ARM_ARCH_TIMER |
0c403462 | 1318 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1319 | help |
1320 | This option enables support for the ARM architected timer | |
1321 | ||
f32f4ce2 RK |
1322 | config HAVE_ARM_TWD |
1323 | bool | |
f32f4ce2 RK |
1324 | help |
1325 | This options enables support for the ARM timer and watchdog unit | |
1326 | ||
e8db288e NP |
1327 | config MCPM |
1328 | bool "Multi-Cluster Power Management" | |
1329 | depends on CPU_V7 && SMP | |
1330 | help | |
1331 | This option provides the common power management infrastructure | |
1332 | for (multi-)cluster based systems, such as big.LITTLE based | |
1333 | systems. | |
1334 | ||
ebf4a5c5 HZ |
1335 | config MCPM_QUAD_CLUSTER |
1336 | bool | |
1337 | depends on MCPM | |
1338 | help | |
1339 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1340 | to 2 clusters by default. | |
1341 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1342 | option to allow the additional clusters to be managed. | |
1343 | ||
1c33be57 NP |
1344 | config BIG_LITTLE |
1345 | bool "big.LITTLE support (Experimental)" | |
1346 | depends on CPU_V7 && SMP | |
1347 | select MCPM | |
1348 | help | |
1349 | This option enables support selections for the big.LITTLE | |
1350 | system architecture. | |
1351 | ||
1352 | config BL_SWITCHER | |
1353 | bool "big.LITTLE switcher support" | |
6c044fec | 1354 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC |
51aaf81f | 1355 | select CPU_PM |
1c33be57 NP |
1356 | help |
1357 | The big.LITTLE "switcher" provides the core functionality to | |
1358 | transparently handle transition between a cluster of A15's | |
1359 | and a cluster of A7's in a big.LITTLE system. | |
1360 | ||
b22537c6 NP |
1361 | config BL_SWITCHER_DUMMY_IF |
1362 | tristate "Simple big.LITTLE switcher user interface" | |
1363 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1364 | help | |
1365 | This is a simple and dummy char dev interface to control | |
1366 | the big.LITTLE switcher core code. It is meant for | |
1367 | debugging purposes only. | |
1368 | ||
8d5796d2 LB |
1369 | choice |
1370 | prompt "Memory split" | |
006fa259 | 1371 | depends on MMU |
8d5796d2 LB |
1372 | default VMSPLIT_3G |
1373 | help | |
1374 | Select the desired split between kernel and user memory. | |
1375 | ||
1376 | If you are not absolutely sure what you are doing, leave this | |
1377 | option alone! | |
1378 | ||
1379 | config VMSPLIT_3G | |
1380 | bool "3G/1G user/kernel split" | |
63ce446c | 1381 | config VMSPLIT_3G_OPT |
bbeedfda | 1382 | depends on !ARM_LPAE |
63ce446c | 1383 | bool "3G/1G user/kernel split (for full 1G low memory)" |
8d5796d2 LB |
1384 | config VMSPLIT_2G |
1385 | bool "2G/2G user/kernel split" | |
1386 | config VMSPLIT_1G | |
1387 | bool "1G/3G user/kernel split" | |
1388 | endchoice | |
1389 | ||
1390 | config PAGE_OFFSET | |
1391 | hex | |
006fa259 | 1392 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1393 | default 0x40000000 if VMSPLIT_1G |
1394 | default 0x80000000 if VMSPLIT_2G | |
63ce446c | 1395 | default 0xB0000000 if VMSPLIT_3G_OPT |
8d5796d2 LB |
1396 | default 0xC0000000 |
1397 | ||
1da177e4 LT |
1398 | config NR_CPUS |
1399 | int "Maximum number of CPUs (2-32)" | |
1400 | range 2 32 | |
1401 | depends on SMP | |
1402 | default "4" | |
1403 | ||
a054a811 | 1404 | config HOTPLUG_CPU |
00b7dede | 1405 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1406 | depends on SMP |
1b5ba350 | 1407 | select GENERIC_IRQ_MIGRATION |
a054a811 RK |
1408 | help |
1409 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1410 | can be controlled through /sys/devices/system/cpu. | |
1411 | ||
2bdd424f WD |
1412 | config ARM_PSCI |
1413 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
e679660d | 1414 | depends on HAVE_ARM_SMCCC |
be120397 | 1415 | select ARM_PSCI_FW |
2bdd424f WD |
1416 | help |
1417 | Say Y here if you want Linux to communicate with system firmware | |
1418 | implementing the PSCI specification for CPU-centric power | |
1419 | management operations described in ARM document number ARM DEN | |
1420 | 0022A ("Power State Coordination Interface System Software on | |
1421 | ARM processors"). | |
1422 | ||
2a6ad871 MR |
1423 | # The GPIO number here must be sorted by descending number. In case of |
1424 | # a multiplatform kernel, we just want the highest value required by the | |
1425 | # selected platforms. | |
44986ab0 PDSN |
1426 | config ARCH_NR_GPIO |
1427 | int | |
139358be | 1428 | default 2048 if ARCH_SOCFPGA |
d9be9ceb | 1429 | default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ |
b35d2e56 | 1430 | ARCH_ZYNQ |
aa42587a TF |
1431 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1432 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1433 | default 416 if ARCH_SUNXI |
06b851e5 | 1434 | default 392 if ARCH_U8500 |
01bb914c | 1435 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1436 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1437 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1438 | default 0 |
1439 | help | |
1440 | Maximum number of GPIOs in the system. | |
1441 | ||
1442 | If unsure, leave the default value. | |
1443 | ||
c9218b16 | 1444 | config HZ_FIXED |
f8065813 | 1445 | int |
da6b21e9 | 1446 | default 200 if ARCH_EBSA110 |
1164f672 | 1447 | default 128 if SOC_AT91RM9200 |
47d84682 | 1448 | default 0 |
c9218b16 RK |
1449 | |
1450 | choice | |
47d84682 | 1451 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1452 | prompt "Timer frequency" |
1453 | ||
1454 | config HZ_100 | |
1455 | bool "100 Hz" | |
1456 | ||
1457 | config HZ_200 | |
1458 | bool "200 Hz" | |
1459 | ||
1460 | config HZ_250 | |
1461 | bool "250 Hz" | |
1462 | ||
1463 | config HZ_300 | |
1464 | bool "300 Hz" | |
1465 | ||
1466 | config HZ_500 | |
1467 | bool "500 Hz" | |
1468 | ||
1469 | config HZ_1000 | |
1470 | bool "1000 Hz" | |
1471 | ||
1472 | endchoice | |
1473 | ||
1474 | config HZ | |
1475 | int | |
47d84682 | 1476 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1477 | default 100 if HZ_100 |
1478 | default 200 if HZ_200 | |
1479 | default 250 if HZ_250 | |
1480 | default 300 if HZ_300 | |
1481 | default 500 if HZ_500 | |
1482 | default 1000 | |
1483 | ||
1484 | config SCHED_HRTICK | |
1485 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1486 | |
16c79651 | 1487 | config THUMB2_KERNEL |
bc7dea00 | 1488 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1489 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1490 | default y if CPU_THUMBONLY |
89bace65 | 1491 | select ARM_UNWIND |
16c79651 CM |
1492 | help |
1493 | By enabling this option, the kernel will be compiled in | |
75fea300 | 1494 | Thumb-2 mode. |
16c79651 CM |
1495 | |
1496 | If unsure, say N. | |
1497 | ||
6f685c5c DM |
1498 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1499 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1500 | depends on THUMB2_KERNEL && MODULES | |
1501 | default y | |
1502 | help | |
1503 | Various binutils versions can resolve Thumb-2 branches to | |
1504 | locally-defined, preemptible global symbols as short-range "b.n" | |
1505 | branch instructions. | |
1506 | ||
1507 | This is a problem, because there's no guarantee the final | |
1508 | destination of the symbol, or any candidate locations for a | |
1509 | trampoline, are within range of the branch. For this reason, the | |
1510 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1511 | relocation in modules at all, and it makes little sense to add | |
1512 | support. | |
1513 | ||
1514 | The symptom is that the kernel fails with an "unsupported | |
1515 | relocation" error when loading some modules. | |
1516 | ||
1517 | Until fixed tools are available, passing | |
1518 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1519 | code which hits this problem, at the cost of a bit of extra runtime | |
1520 | stack usage in some cases. | |
1521 | ||
1522 | The problem is described in more detail at: | |
1523 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1524 | ||
1525 | Only Thumb-2 kernels are affected. | |
1526 | ||
1527 | Unless you are sure your tools don't have this problem, say Y. | |
1528 | ||
42f25bdd NP |
1529 | config ARM_PATCH_IDIV |
1530 | bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" | |
1531 | depends on CPU_32v7 && !XIP_KERNEL | |
1532 | default y | |
1533 | help | |
1534 | The ARM compiler inserts calls to __aeabi_idiv() and | |
1535 | __aeabi_uidiv() when it needs to perform division on signed | |
1536 | and unsigned integers. Some v7 CPUs have support for the sdiv | |
1537 | and udiv instructions that can be used to implement those | |
1538 | functions. | |
1539 | ||
1540 | Enabling this option allows the kernel to modify itself to | |
1541 | replace the first two instructions of these library functions | |
1542 | with the sdiv or udiv plus "bx lr" instructions when the CPU | |
1543 | it is running on supports them. Typically this will be faster | |
1544 | and less power intensive than running the original library | |
1545 | code to do integer division. | |
1546 | ||
704bdda0 | 1547 | config AEABI |
49460970 RK |
1548 | bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K |
1549 | default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K | |
704bdda0 NP |
1550 | help |
1551 | This option allows for the kernel to be compiled using the latest | |
1552 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1553 | space environment that is also compiled with EABI. | |
1554 | ||
1555 | Since there are major incompatibilities between the legacy ABI and | |
1556 | EABI, especially with regard to structure member alignment, this | |
1557 | option also changes the kernel syscall calling convention to | |
1558 | disambiguate both ABIs and allow for backward compatibility support | |
1559 | (selected with CONFIG_OABI_COMPAT). | |
1560 | ||
1561 | To use this you need GCC version 4.0.0 or later. | |
1562 | ||
6c90c872 | 1563 | config OABI_COMPAT |
a73a3ff1 | 1564 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1565 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1566 | help |
1567 | This option preserves the old syscall interface along with the | |
1568 | new (ARM EABI) one. It also provides a compatibility layer to | |
1569 | intercept syscalls that have structure arguments which layout | |
1570 | in memory differs between the legacy ABI and the new ARM EABI | |
1571 | (only for non "thumb" binaries). This option adds a tiny | |
1572 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1573 | |
1574 | The seccomp filter system will not be available when this is | |
1575 | selected, since there is no way yet to sensibly distinguish | |
1576 | between calling conventions during filtering. | |
1577 | ||
6c90c872 NP |
1578 | If you know you'll be using only pure EABI user space then you |
1579 | can say N here. If this option is not selected and you attempt | |
1580 | to execute a legacy ABI binary then the result will be | |
1581 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1582 | at all). If in doubt say N. |
6c90c872 | 1583 | |
eb33575c | 1584 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1585 | bool |
e80d6a24 | 1586 | |
05944d74 RK |
1587 | config ARCH_SPARSEMEM_ENABLE |
1588 | bool | |
1589 | ||
07a2f737 RK |
1590 | config ARCH_SPARSEMEM_DEFAULT |
1591 | def_bool ARCH_SPARSEMEM_ENABLE | |
1592 | ||
05944d74 | 1593 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1594 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1595 | |
7b7bf499 WD |
1596 | config HAVE_ARCH_PFN_VALID |
1597 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1598 | ||
e585513b | 1599 | config HAVE_GENERIC_GUP |
b8cd51af SC |
1600 | def_bool y |
1601 | depends on ARM_LPAE | |
1602 | ||
053a96ca | 1603 | config HIGHMEM |
e8db89a2 RK |
1604 | bool "High Memory Support" |
1605 | depends on MMU | |
053a96ca NP |
1606 | help |
1607 | The address space of ARM processors is only 4 Gigabytes large | |
1608 | and it has to accommodate user address space, kernel address | |
1609 | space as well as some memory mapped IO. That means that, if you | |
1610 | have a large amount of physical memory and/or IO, not all of the | |
1611 | memory can be "permanently mapped" by the kernel. The physical | |
1612 | memory that is not permanently mapped is called "high memory". | |
1613 | ||
1614 | Depending on the selected kernel/user memory split, minimum | |
1615 | vmalloc space and actual amount of RAM, you may not need this | |
1616 | option which should result in a slightly faster kernel. | |
1617 | ||
1618 | If unsure, say n. | |
1619 | ||
65cec8e3 | 1620 | config HIGHPTE |
9a431bd5 | 1621 | bool "Allocate 2nd-level pagetables from highmem" if EXPERT |
65cec8e3 | 1622 | depends on HIGHMEM |
9a431bd5 | 1623 | default y |
b4d103d1 RK |
1624 | help |
1625 | The VM uses one page of physical memory for each page table. | |
1626 | For systems with a lot of processes, this can use a lot of | |
1627 | precious low memory, eventually leading to low memory being | |
1628 | consumed by page tables. Setting this option will allow | |
1629 | user-space 2nd level page tables to reside in high memory. | |
65cec8e3 | 1630 | |
a5e090ac RK |
1631 | config CPU_SW_DOMAIN_PAN |
1632 | bool "Enable use of CPU domains to implement privileged no-access" | |
1633 | depends on MMU && !ARM_LPAE | |
1b8873a0 JI |
1634 | default y |
1635 | help | |
a5e090ac RK |
1636 | Increase kernel security by ensuring that normal kernel accesses |
1637 | are unable to access userspace addresses. This can help prevent | |
1638 | use-after-free bugs becoming an exploitable privilege escalation | |
1639 | by ensuring that magic values (such as LIST_POISON) will always | |
1640 | fault when dereferenced. | |
1641 | ||
1642 | CPUs with low-vector mappings use a best-efforts implementation. | |
1643 | Their lower 1MB needs to remain accessible for the vectors, but | |
1644 | the remainder of userspace will become appropriately inaccessible. | |
65cec8e3 | 1645 | |
1b8873a0 | 1646 | config HW_PERF_EVENTS |
fa8ad788 MR |
1647 | def_bool y |
1648 | depends on ARM_PMU | |
1b8873a0 | 1649 | |
1355e2a6 CM |
1650 | config SYS_SUPPORTS_HUGETLBFS |
1651 | def_bool y | |
1652 | depends on ARM_LPAE | |
1653 | ||
8d962507 CM |
1654 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1655 | def_bool y | |
1656 | depends on ARM_LPAE | |
1657 | ||
4bfab203 SC |
1658 | config ARCH_WANT_GENERAL_HUGETLB |
1659 | def_bool y | |
1660 | ||
7d485f64 AB |
1661 | config ARM_MODULE_PLTS |
1662 | bool "Use PLTs to allow module memory to spill over into vmalloc area" | |
1663 | depends on MODULES | |
e7229f7d | 1664 | default y |
7d485f64 AB |
1665 | help |
1666 | Allocate PLTs when loading modules so that jumps and calls whose | |
1667 | targets are too far away for their relative offsets to be encoded | |
1668 | in the instructions themselves can be bounced via veneers in the | |
1669 | module's PLT. This allows modules to be allocated in the generic | |
1670 | vmalloc area after the dedicated module memory area has been | |
1671 | exhausted. The modules will use slightly more memory, but after | |
1672 | rounding up to page size, the actual memory footprint is usually | |
1673 | the same. | |
1674 | ||
e7229f7d AR |
1675 | Disabling this is usually safe for small single-platform |
1676 | configurations. If unsure, say y. | |
7d485f64 | 1677 | |
c1b2d970 | 1678 | config FORCE_MAX_ZONEORDER |
36d6c928 | 1679 | int "Maximum zone order" |
898f08e1 | 1680 | default "12" if SOC_AM33XX |
6d85e2b0 | 1681 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1682 | default "11" |
1683 | help | |
1684 | The kernel memory allocator divides physically contiguous memory | |
1685 | blocks into "zones", where each zone is a power of two number of | |
1686 | pages. This option selects the largest power of two that the kernel | |
1687 | keeps in the memory allocator. If you need to allocate very large | |
1688 | blocks of physically contiguous memory, then you may need to | |
1689 | increase this value. | |
1690 | ||
1691 | This config option is actually maximum order plus one. For example, | |
1692 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1693 | ||
1da177e4 LT |
1694 | config ALIGNMENT_TRAP |
1695 | bool | |
f12d0d7c | 1696 | depends on CPU_CP15_MMU |
1da177e4 | 1697 | default y if !ARCH_EBSA110 |
e119bfff | 1698 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1699 | help |
84eb8d06 | 1700 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1701 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1702 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1703 | fetch/store instructions will be emulated in software if you say | |
1704 | here, which has a severe performance impact. This is necessary for | |
1705 | correct operation of some network protocols. With an IP-only | |
1706 | configuration it is safe to say N, otherwise say Y. | |
1707 | ||
39ec58f3 | 1708 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1709 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1710 | depends on MMU | |
39ec58f3 LB |
1711 | default y if CPU_FEROCEON |
1712 | help | |
1713 | Implement faster copy_to_user and clear_user methods for CPU | |
1714 | cores where a 8-word STM instruction give significantly higher | |
1715 | memory write throughput than a sequence of individual 32bit stores. | |
1716 | ||
1717 | A possible side effect is a slight increase in scheduling latency | |
1718 | between threads sharing the same address space if they invoke | |
1719 | such copy operations with large buffers. | |
1720 | ||
1721 | However, if the CPU data cache is using a write-allocate mode, | |
1722 | this option is unlikely to provide any performance gain. | |
1723 | ||
70c70d97 NP |
1724 | config SECCOMP |
1725 | bool | |
1726 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1727 | ---help--- | |
1728 | This kernel feature is useful for number crunching applications | |
1729 | that may need to compute untrusted bytecode during their | |
1730 | execution. By using pipes or other transports made available to | |
1731 | the process as file descriptors supporting the read/write | |
1732 | syscalls, it's possible to isolate those applications in | |
1733 | their own address space using seccomp. Once seccomp is | |
1734 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1735 | and the task is only allowed to execute a few safe syscalls | |
1736 | defined by each seccomp mode. | |
1737 | ||
02c2433b SS |
1738 | config PARAVIRT |
1739 | bool "Enable paravirtualization code" | |
1740 | help | |
1741 | This changes the kernel so it can modify itself when it is run | |
1742 | under a hypervisor, potentially improving performance significantly | |
1743 | over full virtualization. | |
1744 | ||
1745 | config PARAVIRT_TIME_ACCOUNTING | |
1746 | bool "Paravirtual steal time accounting" | |
1747 | select PARAVIRT | |
02c2433b SS |
1748 | help |
1749 | Select this option to enable fine granularity task steal time | |
1750 | accounting. Time spent executing other tasks in parallel with | |
1751 | the current vCPU is discounted from the vCPU power. To account for | |
1752 | that, there can be a small performance impact. | |
1753 | ||
1754 | If in doubt, say N here. | |
1755 | ||
eff8d644 SS |
1756 | config XEN_DOM0 |
1757 | def_bool y | |
1758 | depends on XEN | |
1759 | ||
1760 | config XEN | |
c2ba1f7d | 1761 | bool "Xen guest support on ARM" |
85323a99 | 1762 | depends on ARM && AEABI && OF |
f880b67d | 1763 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1764 | depends on !GENERIC_ATOMIC64 |
7693decc | 1765 | depends on MMU |
51aaf81f | 1766 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1767 | select ARM_PSCI |
f21254cd | 1768 | select SWIOTLB |
83862ccf | 1769 | select SWIOTLB_XEN |
02c2433b | 1770 | select PARAVIRT |
eff8d644 SS |
1771 | help |
1772 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1773 | ||
189af465 AB |
1774 | config STACKPROTECTOR_PER_TASK |
1775 | bool "Use a unique stack canary value for each task" | |
1776 | depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA | |
1777 | select GCC_PLUGIN_ARM_SSP_PER_TASK | |
1778 | default y | |
1779 | help | |
1780 | Due to the fact that GCC uses an ordinary symbol reference from | |
1781 | which to load the value of the stack canary, this value can only | |
1782 | change at reboot time on SMP systems, and all tasks running in the | |
1783 | kernel's address space are forced to use the same canary value for | |
1784 | the entire duration that the system is up. | |
1785 | ||
1786 | Enable this option to switch to a different method that uses a | |
1787 | different canary value for each task. | |
1788 | ||
1da177e4 LT |
1789 | endmenu |
1790 | ||
1791 | menu "Boot options" | |
1792 | ||
9eb8f674 GL |
1793 | config USE_OF |
1794 | bool "Flattened Device Tree support" | |
b1b3f49c | 1795 | select IRQ_DOMAIN |
9eb8f674 | 1796 | select OF |
9eb8f674 GL |
1797 | help |
1798 | Include support for flattened device tree machine descriptions. | |
1799 | ||
bd51e2f5 NP |
1800 | config ATAGS |
1801 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1802 | default y | |
1803 | help | |
1804 | This is the traditional way of passing data to the kernel at boot | |
1805 | time. If you are solely relying on the flattened device tree (or | |
1806 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1807 | to remove ATAGS support from your kernel binary. If unsure, | |
1808 | leave this to y. | |
1809 | ||
1810 | config DEPRECATED_PARAM_STRUCT | |
1811 | bool "Provide old way to pass kernel parameters" | |
1812 | depends on ATAGS | |
1813 | help | |
1814 | This was deprecated in 2001 and announced to live on for 5 years. | |
1815 | Some old boot loaders still use this way. | |
1816 | ||
1da177e4 LT |
1817 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1818 | # TEXT and BSS so we preserve their values in the config files. | |
1819 | config ZBOOT_ROM_TEXT | |
1820 | hex "Compressed ROM boot loader base address" | |
1821 | default "0" | |
1822 | help | |
1823 | The physical address at which the ROM-able zImage is to be | |
1824 | placed in the target. Platforms which normally make use of | |
1825 | ROM-able zImage formats normally set this to a suitable | |
1826 | value in their defconfig file. | |
1827 | ||
1828 | If ZBOOT_ROM is not enabled, this has no effect. | |
1829 | ||
1830 | config ZBOOT_ROM_BSS | |
1831 | hex "Compressed ROM boot loader BSS address" | |
1832 | default "0" | |
1833 | help | |
f8c440b2 DF |
1834 | The base address of an area of read/write memory in the target |
1835 | for the ROM-able zImage which must be available while the | |
1836 | decompressor is running. It must be large enough to hold the | |
1837 | entire decompressed kernel plus an additional 128 KiB. | |
1838 | Platforms which normally make use of ROM-able zImage formats | |
1839 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1840 | |
1841 | If ZBOOT_ROM is not enabled, this has no effect. | |
1842 | ||
1843 | config ZBOOT_ROM | |
1844 | bool "Compressed boot loader in ROM/flash" | |
1845 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1846 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1847 | help |
1848 | Say Y here if you intend to execute your compressed kernel image | |
1849 | (zImage) directly from ROM or flash. If unsure, say N. | |
1850 | ||
e2a6a3aa JB |
1851 | config ARM_APPENDED_DTB |
1852 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1853 | depends on OF |
e2a6a3aa JB |
1854 | help |
1855 | With this option, the boot code will look for a device tree binary | |
1856 | (DTB) appended to zImage | |
1857 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1858 | ||
1859 | This is meant as a backward compatibility convenience for those | |
1860 | systems with a bootloader that can't be upgraded to accommodate | |
1861 | the documented boot protocol using a device tree. | |
1862 | ||
1863 | Beware that there is very little in terms of protection against | |
1864 | this option being confused by leftover garbage in memory that might | |
1865 | look like a DTB header after a reboot if no actual DTB is appended | |
1866 | to zImage. Do not leave this option active in a production kernel | |
1867 | if you don't intend to always append a DTB. Proper passing of the | |
1868 | location into r2 of a bootloader provided DTB is always preferable | |
1869 | to this option. | |
1870 | ||
b90b9a38 NP |
1871 | config ARM_ATAG_DTB_COMPAT |
1872 | bool "Supplement the appended DTB with traditional ATAG information" | |
1873 | depends on ARM_APPENDED_DTB | |
1874 | help | |
1875 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1876 | they provide ATAGs with memory configuration, the ramdisk address, | |
1877 | the kernel cmdline string, etc. Such information is dynamically | |
1878 | provided by the bootloader and can't always be stored in a static | |
1879 | DTB. To allow a device tree enabled kernel to be used with such | |
1880 | bootloaders, this option allows zImage to extract the information | |
1881 | from the ATAG list and store it at run time into the appended DTB. | |
1882 | ||
d0f34a11 GR |
1883 | choice |
1884 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1885 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1886 | ||
1887 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1888 | bool "Use bootloader kernel arguments if available" | |
1889 | help | |
1890 | Uses the command-line options passed by the boot loader instead of | |
1891 | the device tree bootargs property. If the boot loader doesn't provide | |
1892 | any, the device tree bootargs property will be used. | |
1893 | ||
1894 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1895 | bool "Extend with bootloader kernel arguments" | |
1896 | help | |
1897 | The command-line arguments provided by the boot loader will be | |
1898 | appended to the the device tree bootargs property. | |
1899 | ||
1900 | endchoice | |
1901 | ||
1da177e4 LT |
1902 | config CMDLINE |
1903 | string "Default kernel command string" | |
1904 | default "" | |
1905 | help | |
1906 | On some architectures (EBSA110 and CATS), there is currently no way | |
1907 | for the boot loader to pass arguments to the kernel. For these | |
1908 | architectures, you should supply some command-line options at build | |
1909 | time by entering them here. As a minimum, you should specify the | |
1910 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1911 | ||
4394c124 VB |
1912 | choice |
1913 | prompt "Kernel command line type" if CMDLINE != "" | |
1914 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1915 | depends on ATAGS |
4394c124 VB |
1916 | |
1917 | config CMDLINE_FROM_BOOTLOADER | |
1918 | bool "Use bootloader kernel arguments if available" | |
1919 | help | |
1920 | Uses the command-line options passed by the boot loader. If | |
1921 | the boot loader doesn't provide any, the default kernel command | |
1922 | string provided in CMDLINE will be used. | |
1923 | ||
1924 | config CMDLINE_EXTEND | |
1925 | bool "Extend bootloader kernel arguments" | |
1926 | help | |
1927 | The command-line arguments provided by the boot loader will be | |
1928 | appended to the default kernel command string. | |
1929 | ||
92d2040d AH |
1930 | config CMDLINE_FORCE |
1931 | bool "Always use the default kernel command string" | |
92d2040d AH |
1932 | help |
1933 | Always use the default kernel command string, even if the boot | |
1934 | loader passes other arguments to the kernel. | |
1935 | This is useful if you cannot or don't want to change the | |
1936 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1937 | endchoice |
92d2040d | 1938 | |
1da177e4 LT |
1939 | config XIP_KERNEL |
1940 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1941 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1942 | help |
1943 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1944 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1945 | space since the text section of the kernel is not loaded from flash | |
1946 | to RAM. Read-write sections, such as the data section and stack, | |
1947 | are still copied to RAM. The XIP kernel is not compressed since | |
1948 | it has to run directly from flash, so it will take more space to | |
1949 | store it. The flash address used to link the kernel object files, | |
1950 | and for storing it, is configuration dependent. Therefore, if you | |
1951 | say Y here, you must know the proper physical address where to | |
1952 | store the kernel image depending on your own flash memory usage. | |
1953 | ||
1954 | Also note that the make target becomes "make xipImage" rather than | |
1955 | "make zImage" or "make Image". The final kernel binary to put in | |
1956 | ROM memory will be arch/arm/boot/xipImage. | |
1957 | ||
1958 | If unsure, say N. | |
1959 | ||
1960 | config XIP_PHYS_ADDR | |
1961 | hex "XIP Kernel Physical Location" | |
1962 | depends on XIP_KERNEL | |
1963 | default "0x00080000" | |
1964 | help | |
1965 | This is the physical address in your flash memory the kernel will | |
1966 | be linked for and stored to. This address is dependent on your | |
1967 | own flash usage. | |
1968 | ||
ca8b5d97 NP |
1969 | config XIP_DEFLATED_DATA |
1970 | bool "Store kernel .data section compressed in ROM" | |
1971 | depends on XIP_KERNEL | |
1972 | select ZLIB_INFLATE | |
1973 | help | |
1974 | Before the kernel is actually executed, its .data section has to be | |
1975 | copied to RAM from ROM. This option allows for storing that data | |
1976 | in compressed form and decompressed to RAM rather than merely being | |
1977 | copied, saving some precious ROM space. A possible drawback is a | |
1978 | slightly longer boot delay. | |
1979 | ||
c587e4a6 RP |
1980 | config KEXEC |
1981 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1982 | depends on (!SMP || PM_SLEEP_SMP) |
cb1293e2 | 1983 | depends on !CPU_V7M |
2965faa5 | 1984 | select KEXEC_CORE |
c587e4a6 RP |
1985 | help |
1986 | kexec is a system call that implements the ability to shutdown your | |
1987 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1988 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1989 | you can start any kernel with it, not just Linux. |
1990 | ||
1991 | It is an ongoing process to be certain the hardware in a machine | |
1992 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1993 | initially work for you. |
c587e4a6 | 1994 | |
4cd9d6f7 RP |
1995 | config ATAGS_PROC |
1996 | bool "Export atags in procfs" | |
bd51e2f5 | 1997 | depends on ATAGS && KEXEC |
b98d7291 | 1998 | default y |
4cd9d6f7 RP |
1999 | help |
2000 | Should the atags used to boot the kernel be exported in an "atags" | |
2001 | file in procfs. Useful with kexec. | |
2002 | ||
cb5d39b3 MW |
2003 | config CRASH_DUMP |
2004 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2005 | help |
2006 | Generate crash dump after being started by kexec. This should | |
2007 | be normally only set in special crash dump kernels which are | |
2008 | loaded in the main kernel with kexec-tools into a specially | |
2009 | reserved region and then later executed after a crash by | |
2010 | kdump/kexec. The crash dump kernel must be compiled to a | |
2011 | memory address not used by the main kernel | |
2012 | ||
2013 | For more details see Documentation/kdump/kdump.txt | |
2014 | ||
e69edc79 EM |
2015 | config AUTO_ZRELADDR |
2016 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2017 | help |
2018 | ZRELADDR is the physical address where the decompressed kernel | |
2019 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2020 | will be determined at run-time by masking the current IP with | |
2021 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2022 | from start of memory. | |
2023 | ||
81a0bc39 RF |
2024 | config EFI_STUB |
2025 | bool | |
2026 | ||
2027 | config EFI | |
2028 | bool "UEFI runtime support" | |
2029 | depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL | |
2030 | select UCS2_STRING | |
2031 | select EFI_PARAMS_FROM_FDT | |
2032 | select EFI_STUB | |
2033 | select EFI_ARMSTUB | |
2034 | select EFI_RUNTIME_WRAPPERS | |
2035 | ---help--- | |
2036 | This option provides support for runtime services provided | |
2037 | by UEFI firmware (such as non-volatile variables, realtime | |
2038 | clock, and platform reset). A UEFI stub is also provided to | |
2039 | allow the kernel to be booted as an EFI application. This | |
2040 | is only useful for kernels that may run on systems that have | |
2041 | UEFI firmware. | |
2042 | ||
bb817bef AB |
2043 | config DMI |
2044 | bool "Enable support for SMBIOS (DMI) tables" | |
2045 | depends on EFI | |
2046 | default y | |
2047 | help | |
2048 | This enables SMBIOS/DMI feature for systems. | |
2049 | ||
2050 | This option is only useful on systems that have UEFI firmware. | |
2051 | However, even with this option, the resultant kernel should | |
2052 | continue to boot on existing non-UEFI platforms. | |
2053 | ||
2054 | NOTE: This does *NOT* enable or encourage the use of DMI quirks, | |
2055 | i.e., the the practice of identifying the platform via DMI to | |
2056 | decide whether certain workarounds for buggy hardware and/or | |
2057 | firmware need to be enabled. This would require the DMI subsystem | |
2058 | to be enabled much earlier than we do on ARM, which is non-trivial. | |
2059 | ||
1da177e4 LT |
2060 | endmenu |
2061 | ||
ac9d7efc | 2062 | menu "CPU Power Management" |
1da177e4 | 2063 | |
1da177e4 | 2064 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2065 | |
ac9d7efc RK |
2066 | source "drivers/cpuidle/Kconfig" |
2067 | ||
2068 | endmenu | |
2069 | ||
1da177e4 LT |
2070 | menu "Floating point emulation" |
2071 | ||
2072 | comment "At least one emulation must be selected" | |
2073 | ||
2074 | config FPE_NWFPE | |
2075 | bool "NWFPE math emulation" | |
593c252a | 2076 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2077 | ---help--- |
2078 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2079 | This is necessary to run most binaries. Linux does not currently | |
2080 | support floating point hardware so you need to say Y here even if | |
2081 | your machine has an FPA or floating point co-processor podule. | |
2082 | ||
2083 | You may say N here if you are going to load the Acorn FPEmulator | |
2084 | early in the bootup. | |
2085 | ||
2086 | config FPE_NWFPE_XP | |
2087 | bool "Support extended precision" | |
bedf142b | 2088 | depends on FPE_NWFPE |
1da177e4 LT |
2089 | help |
2090 | Say Y to include 80-bit support in the kernel floating-point | |
2091 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2092 | Note that gcc does not generate 80-bit operations by default, | |
2093 | so in most cases this option only enlarges the size of the | |
2094 | floating point emulator without any good reason. | |
2095 | ||
2096 | You almost surely want to say N here. | |
2097 | ||
2098 | config FPE_FASTFPE | |
2099 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2100 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2101 | ---help--- |
2102 | Say Y here to include the FAST floating point emulator in the kernel. | |
2103 | This is an experimental much faster emulator which now also has full | |
2104 | precision for the mantissa. It does not support any exceptions. | |
2105 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2106 | ||
2107 | It should be sufficient for most programs. It may be not suitable | |
2108 | for scientific calculations, but you have to check this for yourself. | |
2109 | If you do not feel you need a faster FP emulation you should better | |
2110 | choose NWFPE. | |
2111 | ||
2112 | config VFP | |
2113 | bool "VFP-format floating point maths" | |
e399b1a4 | 2114 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2115 | help |
2116 | Say Y to include VFP support code in the kernel. This is needed | |
2117 | if your hardware includes a VFP unit. | |
2118 | ||
2119 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2120 | release notes and additional status information. | |
2121 | ||
2122 | Say N if your target does not have VFP hardware. | |
2123 | ||
25ebee02 CM |
2124 | config VFPv3 |
2125 | bool | |
2126 | depends on VFP | |
2127 | default y if CPU_V7 | |
2128 | ||
b5872db4 CM |
2129 | config NEON |
2130 | bool "Advanced SIMD (NEON) Extension support" | |
2131 | depends on VFPv3 && CPU_V7 | |
2132 | help | |
2133 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2134 | Extension. | |
2135 | ||
73c132c1 AB |
2136 | config KERNEL_MODE_NEON |
2137 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2138 | depends on NEON && AEABI |
73c132c1 AB |
2139 | help |
2140 | Say Y to include support for NEON in kernel mode. | |
2141 | ||
1da177e4 LT |
2142 | endmenu |
2143 | ||
1da177e4 LT |
2144 | menu "Power management options" |
2145 | ||
eceab4ac | 2146 | source "kernel/power/Kconfig" |
1da177e4 | 2147 | |
f4cb5700 | 2148 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2149 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2150 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2151 | def_bool y |
2152 | ||
15e0d9e3 | 2153 | config ARM_CPU_SUSPEND |
8b6f2499 | 2154 | def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW |
1b9bdf5c | 2155 | depends on ARCH_SUSPEND_POSSIBLE |
15e0d9e3 | 2156 | |
603fb42a SC |
2157 | config ARCH_HIBERNATION_POSSIBLE |
2158 | bool | |
2159 | depends on MMU | |
2160 | default y if ARCH_SUSPEND_POSSIBLE | |
2161 | ||
1da177e4 LT |
2162 | endmenu |
2163 | ||
916f743d KG |
2164 | source "drivers/firmware/Kconfig" |
2165 | ||
652ccae5 AB |
2166 | if CRYPTO |
2167 | source "arch/arm/crypto/Kconfig" | |
2168 | endif | |
1da177e4 | 2169 | |
749cf76c | 2170 | source "arch/arm/kvm/Kconfig" |