Commit | Line | Data |
---|---|---|
4a66d3fe NC |
1 | /* |
2 | * Copyright(c) 2015 EZchip Technologies. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/io.h> | |
19 | #include <asm/mach_desc.h> | |
20 | #include <plat/mtm.h> | |
21 | ||
22 | static void __init eznps_configure_msu(void) | |
23 | { | |
24 | int cpu; | |
25 | struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0}; | |
26 | ||
27 | msu_en_cfg.msu_en = 1; | |
28 | msu_en_cfg.ipi_en = 1; | |
29 | msu_en_cfg.gim_0_en = 1; | |
30 | msu_en_cfg.gim_1_en = 1; | |
31 | ||
32 | /* enable IPI and GIM messages on all clusters */ | |
33 | for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster) | |
34 | iowrite32be(msu_en_cfg.value, | |
35 | nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG)); | |
36 | } | |
37 | ||
38 | static void __init eznps_configure_gim(void) | |
39 | { | |
40 | u32 reg_value; | |
41 | u32 gim_int_lines; | |
42 | struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0}; | |
43 | ||
44 | gim_int_lines = NPS_GIM_UART_LINE; | |
45 | gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; | |
46 | gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE; | |
47 | gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; | |
48 | gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE; | |
49 | ||
50 | /* | |
51 | * IRQ polarity | |
52 | * low or high level | |
53 | * negative or positive edge | |
54 | */ | |
55 | reg_value = ioread32be(REG_GIM_P_INT_POL_0); | |
56 | reg_value &= ~gim_int_lines; | |
57 | iowrite32be(reg_value, REG_GIM_P_INT_POL_0); | |
58 | ||
59 | /* IRQ type level or edge */ | |
60 | reg_value = ioread32be(REG_GIM_P_INT_SENS_0); | |
61 | reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; | |
62 | reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; | |
63 | iowrite32be(reg_value, REG_GIM_P_INT_SENS_0); | |
64 | ||
65 | /* | |
66 | * GIM interrupt select type for | |
67 | * dbg_lan TX and RX interrupts | |
68 | * should be type 1 | |
69 | * type 0 = IRQ line 6 | |
70 | * type 1 = IRQ line 7 | |
71 | */ | |
72 | gim_p_int_dst.is = 1; | |
73 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10); | |
74 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11); | |
75 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25); | |
76 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26); | |
77 | ||
78 | /* | |
79 | * CTOP IRQ lines should be defined | |
80 | * as blocking in GIM | |
81 | */ | |
82 | iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0); | |
83 | ||
84 | /* enable CTOP IRQ lines in GIM */ | |
85 | iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0); | |
86 | } | |
87 | ||
88 | static void __init eznps_early_init(void) | |
89 | { | |
90 | eznps_configure_msu(); | |
91 | eznps_configure_gim(); | |
92 | } | |
93 | ||
94 | static const char *eznps_compat[] __initconst = { | |
95 | "ezchip,arc-nps", | |
96 | NULL, | |
97 | }; | |
98 | ||
99 | MACHINE_START(NPS, "nps") | |
100 | .dt_compat = eznps_compat, | |
101 | .init_early = eznps_early_init, | |
102 | MACHINE_END |