projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 4a66d3fe NC |
2 | # |
| 3 | # For a description of the syntax of this configuration file, | |
| 4 | # see Documentation/kbuild/kconfig-language.txt. | |
| 5 | # | |
| 6 | ||
| 7 | menuconfig ARC_PLAT_EZNPS | |
| 8 | bool "\"EZchip\" ARC dev platform" | |
| 4a66d3fe NC |
9 | select CPU_BIG_ENDIAN |
| 10 | select CLKSRC_NPS | |
| 11 | select EZNPS_GIC | |
| 12 | select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET | |
| 13 | help | |
| 14 | Support for EZchip development platforms, | |
| 15 | based on ARC700 cores. | |
| 9e939552 NC |
16 | We handle few flavors: |
| 17 | - Hardware Emulator AKA HE which is FPGA based chassis | |
| 4a66d3fe NC |
18 | - Simulator based on MetaWare nSIM |
| 19 | - NPS400 chip based on ASIC | |
| 20 | ||
| 21 | config EZNPS_MTM_EXT | |
| 22 | bool "ARC-EZchip MTM Extensions" | |
| 23 | select CPUMASK_OFFSTACK | |
| 24 | depends on ARC_PLAT_EZNPS && SMP | |
| 25 | default y | |
| 26 | help | |
| 27 | Here we add new hierarchy for CPUs topology. | |
| 28 | We got: | |
| 29 | Core | |
| 30 | Thread | |
| 31 | At the new thread level each CPU represent one HW thread. | |
| 32 | At highest hierarchy each core contain 16 threads, | |
| 33 | any of them seem like CPU from Linux point of view. | |
| 34 | All threads within same core share the execution unit of the | |
| 35 | core and HW scheduler round robin between them. | |
| 98339495 NC |
36 | |
| 37 | config EZNPS_MEM_ERROR_ALIGN | |
| 38 | bool "ARC-EZchip Memory error as an exception" | |
| 39 | depends on EZNPS_MTM_EXT | |
| 40 | default n | |
| 41 | help | |
| 42 | On the real chip of the NPS, user memory errors are handled | |
| 43 | as a machine check exception, which is fatal, whereas on | |
| 44 | simulator platform for NPS, is handled as a Level 2 interrupt | |
| 45 | (just a stock ARC700) which is recoverable. This option makes | |
| 46 | simulator behave like hardware. | |
| abd8926b LR |
47 | |
| 48 | config EZNPS_SHARED_AUX_REGS | |
| 49 | bool "ARC-EZchip Shared Auxiliary Registers Per Core" | |
| 50 | depends on ARC_PLAT_EZNPS | |
| 51 | default y | |
| 52 | help | |
| 53 | On the real chip of the NPS, auxiliary registers are shared between | |
| 54 | all the cpus of the core, whereas on simulator platform for NPS, | |
| 55 | each cpu has a different set of auxiliary registers. Configuration | |
| 56 | should be unset if auxiliary registers are not shared between the cpus | |
| 57 | of the core, so there will be a need to initialize them per cpu. |