Commit | Line | Data |
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95d6976d VG |
1 | /* |
2 | * ARC700 VIPT Cache Management | |
3 | * | |
4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs | |
11 | * -flush_cache_dup_mm (fork) | |
12 | * -likewise for flush_cache_mm (exit/execve) | |
13 | * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break) | |
14 | * | |
15 | * vineetg: Apr 2011 | |
16 | * -Now that MMU can support larger pg sz (16K), the determiniation of | |
17 | * aliasing shd not be based on assumption of 8k pg | |
18 | * | |
19 | * vineetg: Mar 2011 | |
20 | * -optimised version of flush_icache_range( ) for making I/D coherent | |
21 | * when vaddr is available (agnostic of num of aliases) | |
22 | * | |
23 | * vineetg: Mar 2011 | |
24 | * -Added documentation about I-cache aliasing on ARC700 and the way it | |
25 | * was handled up until MMU V2. | |
26 | * -Spotted a three year old bug when killing the 4 aliases, which needs | |
27 | * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03} | |
28 | * instead of paddr | {0x00, 0x01, 0x10, 0x11} | |
29 | * (Rajesh you owe me one now) | |
30 | * | |
31 | * vineetg: Dec 2010 | |
32 | * -Off-by-one error when computing num_of_lines to flush | |
33 | * This broke signal handling with bionic which uses synthetic sigret stub | |
34 | * | |
35 | * vineetg: Mar 2010 | |
36 | * -GCC can't generate ZOL for core cache flush loops. | |
37 | * Conv them into iterations based as opposed to while (start < end) types | |
38 | * | |
39 | * Vineetg: July 2009 | |
40 | * -In I-cache flush routine we used to chk for aliasing for every line INV. | |
41 | * Instead now we setup routines per cache geometry and invoke them | |
42 | * via function pointers. | |
43 | * | |
44 | * Vineetg: Jan 2009 | |
45 | * -Cache Line flush routines used to flush an extra line beyond end addr | |
46 | * because check was while (end >= start) instead of (end > start) | |
47 | * =Some call sites had to work around by doing -1, -4 etc to end param | |
48 | * =Some callers didnt care. This was spec bad in case of INV routines | |
49 | * which would discard valid data (cause of the horrible ext2 bug | |
50 | * in ARC IDE driver) | |
51 | * | |
52 | * vineetg: June 11th 2008: Fixed flush_icache_range( ) | |
53 | * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need | |
54 | * to be flushed, which it was not doing. | |
55 | * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API, | |
56 | * however ARC cache maintenance OPs require PHY addr. Thus need to do | |
57 | * vmalloc_to_phy. | |
58 | * -Also added optimisation there, that for range > PAGE SIZE we flush the | |
59 | * entire cache in one shot rather than line by line. For e.g. a module | |
60 | * with Code sz 600k, old code flushed 600k worth of cache (line-by-line), | |
61 | * while cache is only 16 or 32k. | |
62 | */ | |
63 | ||
64 | #include <linux/module.h> | |
65 | #include <linux/mm.h> | |
66 | #include <linux/sched.h> | |
67 | #include <linux/cache.h> | |
68 | #include <linux/mmu_context.h> | |
69 | #include <linux/syscalls.h> | |
70 | #include <linux/uaccess.h> | |
4102b533 | 71 | #include <linux/pagemap.h> |
95d6976d VG |
72 | #include <asm/cacheflush.h> |
73 | #include <asm/cachectl.h> | |
74 | #include <asm/setup.h> | |
75 | ||
da1677b0 VG |
76 | /* Instruction cache related Auxiliary registers */ |
77 | #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ | |
78 | #define ARC_REG_IC_IVIC 0x10 | |
79 | #define ARC_REG_IC_CTRL 0x11 | |
80 | #define ARC_REG_IC_IVIL 0x19 | |
81 | #if (CONFIG_ARC_MMU_VER > 2) | |
82 | #define ARC_REG_IC_PTAG 0x1E | |
83 | #endif | |
84 | ||
85 | /* Bit val in IC_CTRL */ | |
86 | #define IC_CTRL_CACHE_DISABLE 0x1 | |
87 | ||
88 | /* Data cache related Auxiliary registers */ | |
89 | #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ | |
90 | #define ARC_REG_DC_IVDC 0x47 | |
91 | #define ARC_REG_DC_CTRL 0x48 | |
92 | #define ARC_REG_DC_IVDL 0x4A | |
93 | #define ARC_REG_DC_FLSH 0x4B | |
94 | #define ARC_REG_DC_FLDL 0x4C | |
95 | #if (CONFIG_ARC_MMU_VER > 2) | |
96 | #define ARC_REG_DC_PTAG 0x5C | |
97 | #endif | |
98 | ||
99 | /* Bit val in DC_CTRL */ | |
100 | #define DC_CTRL_INV_MODE_FLUSH 0x40 | |
101 | #define DC_CTRL_FLUSH_STATUS 0x100 | |
102 | ||
af617428 VG |
103 | char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) |
104 | { | |
105 | int n = 0; | |
106 | unsigned int c = smp_processor_id(); | |
107 | ||
108 | #define PR_CACHE(p, enb, str) \ | |
109 | { \ | |
110 | if (!(p)->ver) \ | |
111 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ | |
112 | else \ | |
113 | n += scnprintf(buf + n, len - n, \ | |
114 | str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \ | |
115 | TO_KB((p)->sz), (p)->assoc, (p)->line_len, \ | |
116 | enb ? "" : "DISABLED (kernel-build)"); \ | |
117 | } | |
118 | ||
8235703e VG |
119 | PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE), |
120 | "I-Cache"); | |
121 | PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE), | |
122 | "D-Cache"); | |
af617428 VG |
123 | |
124 | return buf; | |
125 | } | |
126 | ||
95d6976d VG |
127 | /* |
128 | * Read the Cache Build Confuration Registers, Decode them and save into | |
129 | * the cpuinfo structure for later use. | |
130 | * No Validation done here, simply read/convert the BCRs | |
131 | */ | |
30ecee8c | 132 | void __cpuinit read_decode_cache_bcr(void) |
95d6976d | 133 | { |
95d6976d VG |
134 | struct cpuinfo_arc_cache *p_ic, *p_dc; |
135 | unsigned int cpu = smp_processor_id(); | |
da1677b0 VG |
136 | struct bcr_cache { |
137 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
138 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
139 | #else | |
140 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
141 | #endif | |
142 | } ibcr, dbcr; | |
95d6976d VG |
143 | |
144 | p_ic = &cpuinfo_arc700[cpu].icache; | |
145 | READ_BCR(ARC_REG_IC_BCR, ibcr); | |
146 | ||
30499186 VG |
147 | BUG_ON(ibcr.config != 3); |
148 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ | |
95d6976d VG |
149 | p_ic->line_len = 8 << ibcr.line_len; |
150 | p_ic->sz = 0x200 << ibcr.sz; | |
151 | p_ic->ver = ibcr.ver; | |
152 | ||
153 | p_dc = &cpuinfo_arc700[cpu].dcache; | |
154 | READ_BCR(ARC_REG_DC_BCR, dbcr); | |
155 | ||
30499186 VG |
156 | BUG_ON(dbcr.config != 2); |
157 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ | |
95d6976d VG |
158 | p_dc->line_len = 16 << dbcr.line_len; |
159 | p_dc->sz = 0x200 << dbcr.sz; | |
160 | p_dc->ver = dbcr.ver; | |
161 | } | |
162 | ||
163 | /* | |
164 | * 1. Validate the Cache Geomtery (compile time config matches hardware) | |
165 | * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) | |
166 | * (aliasing D-cache configurations are not supported YET) | |
167 | * 3. Enable the Caches, setup default flush mode for D-Cache | |
168 | * 3. Calculate the SHMLBA used by user space | |
169 | */ | |
30ecee8c | 170 | void __cpuinit arc_cache_init(void) |
95d6976d | 171 | { |
95d6976d | 172 | unsigned int cpu = smp_processor_id(); |
d626f547 VG |
173 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; |
174 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
da1677b0 | 175 | unsigned int dcache_does_alias, temp; |
af617428 VG |
176 | char str[256]; |
177 | ||
178 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | |
95d6976d | 179 | |
d626f547 VG |
180 | if (!ic->ver) |
181 | goto chk_dc; | |
95d6976d | 182 | |
d626f547 | 183 | #ifdef CONFIG_ARC_HAS_ICACHE |
af617428 | 184 | /* 1. Confirm some of I-cache params which Linux assumes */ |
30499186 | 185 | if (ic->line_len != ARC_ICACHE_LINE_LEN) |
af617428 | 186 | panic("Cache H/W doesn't match kernel Config"); |
af617428 | 187 | |
30499186 VG |
188 | if (ic->ver != CONFIG_ARC_MMU_VER) |
189 | panic("Cache ver doesn't match MMU ver\n"); | |
95d6976d VG |
190 | #endif |
191 | ||
192 | /* Enable/disable I-Cache */ | |
193 | temp = read_aux_reg(ARC_REG_IC_CTRL); | |
194 | ||
195 | #ifdef CONFIG_ARC_HAS_ICACHE | |
196 | temp &= ~IC_CTRL_CACHE_DISABLE; | |
197 | #else | |
198 | temp |= IC_CTRL_CACHE_DISABLE; | |
199 | #endif | |
200 | ||
201 | write_aux_reg(ARC_REG_IC_CTRL, temp); | |
202 | ||
d626f547 VG |
203 | chk_dc: |
204 | if (!dc->ver) | |
205 | return; | |
95d6976d | 206 | |
d626f547 | 207 | #ifdef CONFIG_ARC_HAS_DCACHE |
30499186 | 208 | if (dc->line_len != ARC_DCACHE_LINE_LEN) |
af617428 | 209 | panic("Cache H/W doesn't match kernel Config"); |
4102b533 | 210 | |
95d6976d | 211 | /* check for D-Cache aliasing */ |
30499186 VG |
212 | dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; |
213 | ||
4102b533 VG |
214 | if (dcache_does_alias && !cache_is_vipt_aliasing()) |
215 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
216 | else if (!dcache_does_alias && cache_is_vipt_aliasing()) | |
217 | panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
95d6976d VG |
218 | #endif |
219 | ||
220 | /* Set the default Invalidate Mode to "simpy discard dirty lines" | |
221 | * as this is more frequent then flush before invalidate | |
222 | * Ofcourse we toggle this default behviour when desired | |
223 | */ | |
224 | temp = read_aux_reg(ARC_REG_DC_CTRL); | |
225 | temp &= ~DC_CTRL_INV_MODE_FLUSH; | |
226 | ||
227 | #ifdef CONFIG_ARC_HAS_DCACHE | |
228 | /* Enable D-Cache: Clear Bit 0 */ | |
229 | write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); | |
230 | #else | |
231 | /* Flush D cache */ | |
232 | write_aux_reg(ARC_REG_DC_FLSH, 0x1); | |
233 | /* Disable D cache */ | |
234 | write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); | |
235 | #endif | |
236 | ||
237 | return; | |
238 | } | |
239 | ||
240 | #define OP_INV 0x1 | |
241 | #define OP_FLUSH 0x2 | |
242 | #define OP_FLUSH_N_INV 0x3 | |
243 | ||
244 | #ifdef CONFIG_ARC_HAS_DCACHE | |
245 | ||
246 | /*************************************************************** | |
247 | * Machine specific helpers for Entire D-Cache or Per Line ops | |
248 | */ | |
249 | ||
250 | static inline void wait_for_flush(void) | |
251 | { | |
252 | while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS) | |
253 | ; | |
254 | } | |
255 | ||
256 | /* | |
257 | * Operation on Entire D-Cache | |
258 | * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} | |
259 | * Note that constant propagation ensures all the checks are gone | |
260 | * in generated code | |
261 | */ | |
262 | static inline void __dc_entire_op(const int cacheop) | |
263 | { | |
336e199e | 264 | unsigned int tmp = tmp; |
95d6976d VG |
265 | int aux; |
266 | ||
95d6976d VG |
267 | if (cacheop == OP_FLUSH_N_INV) { |
268 | /* Dcache provides 2 cmd: FLUSH or INV | |
269 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
270 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
271 | * Default INV sub-mode is DISCARD, which needs to be toggled | |
272 | */ | |
273 | tmp = read_aux_reg(ARC_REG_DC_CTRL); | |
274 | write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); | |
275 | } | |
276 | ||
277 | if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ | |
278 | aux = ARC_REG_DC_IVDC; | |
279 | else | |
280 | aux = ARC_REG_DC_FLSH; | |
281 | ||
282 | write_aux_reg(aux, 0x1); | |
283 | ||
284 | if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ | |
285 | wait_for_flush(); | |
286 | ||
287 | /* Switch back the DISCARD ONLY Invalidate mode */ | |
288 | if (cacheop == OP_FLUSH_N_INV) | |
289 | write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); | |
95d6976d VG |
290 | } |
291 | ||
292 | /* | |
293 | * Per Line Operation on D-Cache | |
294 | * Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete | |
295 | * It's sole purpose is to help gcc generate ZOL | |
6ec18a81 | 296 | * (aliasing VIPT dcache flushing needs both vaddr and paddr) |
95d6976d | 297 | */ |
6ec18a81 VG |
298 | static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr, |
299 | unsigned long sz, const int aux_reg) | |
95d6976d | 300 | { |
a690984d | 301 | int num_lines; |
95d6976d VG |
302 | |
303 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
a690984d | 304 | * and have @paddr - aligned to cache line and integral @num_lines. |
95d6976d | 305 | * This however can be avoided for page sized since: |
a690984d | 306 | * -@paddr will be cache-line aligned already (being page aligned) |
95d6976d VG |
307 | * -@sz will be integral multiple of line size (being page sized). |
308 | */ | |
309 | if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) { | |
a690984d VG |
310 | sz += paddr & ~DCACHE_LINE_MASK; |
311 | paddr &= DCACHE_LINE_MASK; | |
6ec18a81 | 312 | vaddr &= DCACHE_LINE_MASK; |
95d6976d VG |
313 | } |
314 | ||
315 | num_lines = DIV_ROUND_UP(sz, ARC_DCACHE_LINE_LEN); | |
316 | ||
6ec18a81 VG |
317 | #if (CONFIG_ARC_MMU_VER <= 2) |
318 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; | |
319 | #endif | |
320 | ||
95d6976d VG |
321 | while (num_lines-- > 0) { |
322 | #if (CONFIG_ARC_MMU_VER > 2) | |
323 | /* | |
324 | * Just as for I$, in MMU v3, D$ ops also require | |
325 | * "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops | |
95d6976d | 326 | */ |
a690984d | 327 | write_aux_reg(ARC_REG_DC_PTAG, paddr); |
6ec18a81 VG |
328 | |
329 | write_aux_reg(aux_reg, vaddr); | |
330 | vaddr += ARC_DCACHE_LINE_LEN; | |
331 | #else | |
332 | /* paddr contains stuffed vaddrs bits */ | |
a690984d | 333 | write_aux_reg(aux_reg, paddr); |
6ec18a81 | 334 | #endif |
a690984d | 335 | paddr += ARC_DCACHE_LINE_LEN; |
95d6976d VG |
336 | } |
337 | } | |
338 | ||
4102b533 | 339 | /* For kernel mappings cache operation: index is same as paddr */ |
6ec18a81 VG |
340 | #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) |
341 | ||
95d6976d VG |
342 | /* |
343 | * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback) | |
344 | */ | |
6ec18a81 VG |
345 | static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, |
346 | unsigned long sz, const int cacheop) | |
95d6976d VG |
347 | { |
348 | unsigned long flags, tmp = tmp; | |
349 | int aux; | |
350 | ||
351 | local_irq_save(flags); | |
352 | ||
353 | if (cacheop == OP_FLUSH_N_INV) { | |
354 | /* | |
355 | * Dcache provides 2 cmd: FLUSH or INV | |
356 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
357 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
358 | * Default INV sub-mode is DISCARD, which needs to be toggled | |
359 | */ | |
360 | tmp = read_aux_reg(ARC_REG_DC_CTRL); | |
361 | write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); | |
362 | } | |
363 | ||
364 | if (cacheop & OP_INV) /* Inv / flush-n-inv use same cmd reg */ | |
365 | aux = ARC_REG_DC_IVDL; | |
366 | else | |
367 | aux = ARC_REG_DC_FLDL; | |
368 | ||
6ec18a81 | 369 | __dc_line_loop(paddr, vaddr, sz, aux); |
95d6976d VG |
370 | |
371 | if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ | |
372 | wait_for_flush(); | |
373 | ||
374 | /* Switch back the DISCARD ONLY Invalidate mode */ | |
375 | if (cacheop == OP_FLUSH_N_INV) | |
376 | write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); | |
377 | ||
378 | local_irq_restore(flags); | |
379 | } | |
380 | ||
381 | #else | |
382 | ||
383 | #define __dc_entire_op(cacheop) | |
6ec18a81 VG |
384 | #define __dc_line_op(paddr, vaddr, sz, cacheop) |
385 | #define __dc_line_op_k(paddr, sz, cacheop) | |
95d6976d VG |
386 | |
387 | #endif /* CONFIG_ARC_HAS_DCACHE */ | |
388 | ||
389 | ||
390 | #ifdef CONFIG_ARC_HAS_ICACHE | |
391 | ||
392 | /* | |
393 | * I-Cache Aliasing in ARC700 VIPT caches | |
394 | * | |
7f250a0f VG |
395 | * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. |
396 | * The orig Cache Management Module "CDU" only required paddr to invalidate a | |
397 | * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. | |
398 | * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching | |
399 | * the exact same line. | |
95d6976d | 400 | * |
7f250a0f VG |
401 | * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, |
402 | * paddr alone could not be used to correctly index the cache. | |
95d6976d VG |
403 | * |
404 | * ------------------ | |
405 | * MMU v1/v2 (Fixed Page Size 8k) | |
406 | * ------------------ | |
407 | * The solution was to provide CDU with these additonal vaddr bits. These | |
7f250a0f VG |
408 | * would be bits [x:13], x would depend on cache-geometry, 13 comes from |
409 | * standard page size of 8k. | |
95d6976d VG |
410 | * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits |
411 | * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the | |
412 | * orig 5 bits of paddr were anyways ignored by CDU line ops, as they | |
413 | * represent the offset within cache-line. The adv of using this "clumsy" | |
7f250a0f VG |
414 | * interface for additional info was no new reg was needed in CDU programming |
415 | * model. | |
95d6976d VG |
416 | * |
417 | * 17:13 represented the max num of bits passable, actual bits needed were | |
418 | * fewer, based on the num-of-aliases possible. | |
419 | * -for 2 alias possibility, only bit 13 needed (32K cache) | |
420 | * -for 4 alias possibility, bits 14:13 needed (64K cache) | |
421 | * | |
95d6976d VG |
422 | * ------------------ |
423 | * MMU v3 | |
424 | * ------------------ | |
7f250a0f VG |
425 | * This ver of MMU supports variable page sizes (1k-16k): although Linux will |
426 | * only support 8k (default), 16k and 4k. | |
95d6976d VG |
427 | * However from hardware perspective, smaller page sizes aggrevate aliasing |
428 | * meaning more vaddr bits needed to disambiguate the cache-line-op ; | |
429 | * the existing scheme of piggybacking won't work for certain configurations. | |
430 | * Two new registers IC_PTAG and DC_PTAG inttoduced. | |
431 | * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs | |
432 | */ | |
433 | ||
434 | /*********************************************************** | |
7f250a0f | 435 | * Machine specific helper for per line I-Cache invalidate. |
95d6976d | 436 | */ |
a690984d | 437 | static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, |
7f250a0f | 438 | unsigned long sz) |
95d6976d VG |
439 | { |
440 | unsigned long flags; | |
a690984d | 441 | int num_lines; |
95d6976d | 442 | |
764531cc VG |
443 | /* |
444 | * Ensure we properly floor/ceil the non-line aligned/sized requests: | |
445 | * However page sized flushes can be compile time optimised. | |
a690984d | 446 | * -@paddr will be cache-line aligned already (being page aligned) |
764531cc VG |
447 | * -@sz will be integral multiple of line size (being page sized). |
448 | */ | |
449 | if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) { | |
a690984d VG |
450 | sz += paddr & ~ICACHE_LINE_MASK; |
451 | paddr &= ICACHE_LINE_MASK; | |
452 | vaddr &= ICACHE_LINE_MASK; | |
764531cc VG |
453 | } |
454 | ||
95d6976d VG |
455 | num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN); |
456 | ||
a690984d | 457 | #if (CONFIG_ARC_MMU_VER <= 2) |
95d6976d | 458 | /* bits 17:13 of vaddr go as bits 4:0 of paddr */ |
a690984d | 459 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; |
95d6976d VG |
460 | #endif |
461 | ||
462 | local_irq_save(flags); | |
463 | while (num_lines-- > 0) { | |
464 | #if (CONFIG_ARC_MMU_VER > 2) | |
465 | /* tag comes from phy addr */ | |
a690984d | 466 | write_aux_reg(ARC_REG_IC_PTAG, paddr); |
95d6976d VG |
467 | |
468 | /* index bits come from vaddr */ | |
469 | write_aux_reg(ARC_REG_IC_IVIL, vaddr); | |
470 | vaddr += ARC_ICACHE_LINE_LEN; | |
471 | #else | |
7f250a0f | 472 | /* paddr contains stuffed vaddrs bits */ |
a690984d | 473 | write_aux_reg(ARC_REG_IC_IVIL, paddr); |
95d6976d | 474 | #endif |
a690984d | 475 | paddr += ARC_ICACHE_LINE_LEN; |
95d6976d VG |
476 | } |
477 | local_irq_restore(flags); | |
478 | } | |
479 | ||
336e199e VG |
480 | static inline void __ic_entire_inv(void) |
481 | { | |
482 | write_aux_reg(ARC_REG_IC_IVIC, 1); | |
483 | read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
484 | } | |
485 | ||
95d6976d VG |
486 | #else |
487 | ||
336e199e | 488 | #define __ic_entire_inv() |
95d6976d VG |
489 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
490 | ||
491 | #endif /* CONFIG_ARC_HAS_ICACHE */ | |
492 | ||
493 | ||
494 | /*********************************************************** | |
495 | * Exported APIs | |
496 | */ | |
497 | ||
4102b533 VG |
498 | /* |
499 | * Handle cache congruency of kernel and userspace mappings of page when kernel | |
500 | * writes-to/reads-from | |
501 | * | |
502 | * The idea is to defer flushing of kernel mapping after a WRITE, possible if: | |
503 | * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent | |
504 | * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) | |
505 | * -In SMP, if hardware caches are coherent | |
506 | * | |
507 | * There's a corollary case, where kernel READs from a userspace mapped page. | |
508 | * If the U-mapping is not congruent to to K-mapping, former needs flushing. | |
509 | */ | |
95d6976d VG |
510 | void flush_dcache_page(struct page *page) |
511 | { | |
4102b533 VG |
512 | struct address_space *mapping; |
513 | ||
514 | if (!cache_is_vipt_aliasing()) { | |
515 | set_bit(PG_arch_1, &page->flags); | |
516 | return; | |
517 | } | |
518 | ||
519 | /* don't handle anon pages here */ | |
520 | mapping = page_mapping(page); | |
521 | if (!mapping) | |
522 | return; | |
523 | ||
524 | /* | |
525 | * pagecache page, file not yet mapped to userspace | |
526 | * Make a note that K-mapping is dirty | |
527 | */ | |
528 | if (!mapping_mapped(mapping)) { | |
529 | set_bit(PG_arch_1, &page->flags); | |
530 | } else if (page_mapped(page)) { | |
531 | ||
532 | /* kernel reading from page with U-mapping */ | |
533 | void *paddr = page_address(page); | |
534 | unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; | |
535 | ||
536 | if (addr_not_cache_congruent(paddr, vaddr)) | |
537 | __flush_dcache_page(paddr, vaddr); | |
538 | } | |
95d6976d VG |
539 | } |
540 | EXPORT_SYMBOL(flush_dcache_page); | |
541 | ||
542 | ||
543 | void dma_cache_wback_inv(unsigned long start, unsigned long sz) | |
544 | { | |
6ec18a81 | 545 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); |
95d6976d VG |
546 | } |
547 | EXPORT_SYMBOL(dma_cache_wback_inv); | |
548 | ||
549 | void dma_cache_inv(unsigned long start, unsigned long sz) | |
550 | { | |
6ec18a81 | 551 | __dc_line_op_k(start, sz, OP_INV); |
95d6976d VG |
552 | } |
553 | EXPORT_SYMBOL(dma_cache_inv); | |
554 | ||
555 | void dma_cache_wback(unsigned long start, unsigned long sz) | |
556 | { | |
6ec18a81 | 557 | __dc_line_op_k(start, sz, OP_FLUSH); |
95d6976d VG |
558 | } |
559 | EXPORT_SYMBOL(dma_cache_wback); | |
560 | ||
561 | /* | |
7586bf72 VG |
562 | * This is API for making I/D Caches consistent when modifying |
563 | * kernel code (loadable modules, kprobes, kgdb...) | |
95d6976d VG |
564 | * This is called on insmod, with kernel virtual address for CODE of |
565 | * the module. ARC cache maintenance ops require PHY address thus we | |
566 | * need to convert vmalloc addr to PHY addr | |
567 | */ | |
568 | void flush_icache_range(unsigned long kstart, unsigned long kend) | |
569 | { | |
570 | unsigned int tot_sz, off, sz; | |
571 | unsigned long phy, pfn; | |
95d6976d VG |
572 | |
573 | /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */ | |
574 | ||
575 | /* This is not the right API for user virtual address */ | |
576 | if (kstart < TASK_SIZE) { | |
577 | BUG_ON("Flush icache range for user virtual addr space"); | |
578 | return; | |
579 | } | |
580 | ||
581 | /* Shortcut for bigger flush ranges. | |
582 | * Here we don't care if this was kernel virtual or phy addr | |
583 | */ | |
584 | tot_sz = kend - kstart; | |
585 | if (tot_sz > PAGE_SIZE) { | |
586 | flush_cache_all(); | |
587 | return; | |
588 | } | |
589 | ||
590 | /* Case: Kernel Phy addr (0x8000_0000 onwards) */ | |
591 | if (likely(kstart > PAGE_OFFSET)) { | |
7586bf72 VG |
592 | /* |
593 | * The 2nd arg despite being paddr will be used to index icache | |
594 | * This is OK since no alternate virtual mappings will exist | |
595 | * given the callers for this case: kprobe/kgdb in built-in | |
596 | * kernel code only. | |
597 | */ | |
94bad1af | 598 | __sync_icache_dcache(kstart, kstart, kend - kstart); |
95d6976d VG |
599 | return; |
600 | } | |
601 | ||
602 | /* | |
603 | * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) | |
604 | * (1) ARC Cache Maintenance ops only take Phy addr, hence special | |
605 | * handling of kernel vaddr. | |
606 | * | |
607 | * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), | |
608 | * it still needs to handle a 2 page scenario, where the range | |
609 | * straddles across 2 virtual pages and hence need for loop | |
610 | */ | |
611 | while (tot_sz > 0) { | |
612 | off = kstart % PAGE_SIZE; | |
613 | pfn = vmalloc_to_pfn((void *)kstart); | |
614 | phy = (pfn << PAGE_SHIFT) + off; | |
615 | sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); | |
94bad1af | 616 | __sync_icache_dcache(phy, kstart, sz); |
95d6976d VG |
617 | kstart += sz; |
618 | tot_sz -= sz; | |
619 | } | |
620 | } | |
621 | ||
622 | /* | |
94bad1af VG |
623 | * General purpose helper to make I and D cache lines consistent. |
624 | * @paddr is phy addr of region | |
625 | * @vaddr is typically user or kernel vaddr (vmalloc) | |
626 | * Howver in one instance, flush_icache_range() by kprobe (for a breakpt in | |
627 | * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will | |
628 | * use a paddr to index the cache (despite VIPT). This is fine since since a | |
629 | * built-in kernel page will not have any virtual mappings (not even kernel) | |
630 | * kprobe on loadable module is different as it will have kvaddr. | |
95d6976d | 631 | */ |
94bad1af | 632 | void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) |
95d6976d | 633 | { |
94bad1af VG |
634 | unsigned long flags; |
635 | ||
636 | local_irq_save(flags); | |
637 | __ic_line_inv_vaddr(paddr, vaddr, len); | |
f538881c | 638 | __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); |
94bad1af | 639 | local_irq_restore(flags); |
95d6976d VG |
640 | } |
641 | ||
24603fdd VG |
642 | /* wrapper to compile time eliminate alignment checks in flush loop */ |
643 | void __inv_icache_page(unsigned long paddr, unsigned long vaddr) | |
95d6976d | 644 | { |
24603fdd | 645 | __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); |
95d6976d VG |
646 | } |
647 | ||
6ec18a81 VG |
648 | /* |
649 | * wrapper to clearout kernel or userspace mappings of a page | |
650 | * For kernel mappings @vaddr == @paddr | |
651 | */ | |
de2a852c | 652 | void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr) |
eacd0e95 | 653 | { |
6ec18a81 | 654 | __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); |
eacd0e95 VG |
655 | } |
656 | ||
95d6976d VG |
657 | noinline void flush_cache_all(void) |
658 | { | |
659 | unsigned long flags; | |
660 | ||
661 | local_irq_save(flags); | |
662 | ||
336e199e | 663 | __ic_entire_inv(); |
95d6976d VG |
664 | __dc_entire_op(OP_FLUSH_N_INV); |
665 | ||
666 | local_irq_restore(flags); | |
667 | ||
668 | } | |
669 | ||
4102b533 VG |
670 | #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING |
671 | ||
672 | void flush_cache_mm(struct mm_struct *mm) | |
673 | { | |
674 | flush_cache_all(); | |
675 | } | |
676 | ||
677 | void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, | |
678 | unsigned long pfn) | |
679 | { | |
680 | unsigned int paddr = pfn << PAGE_SHIFT; | |
681 | ||
5971bc71 VG |
682 | u_vaddr &= PAGE_MASK; |
683 | ||
684 | ___flush_dcache_page(paddr, u_vaddr); | |
685 | ||
686 | if (vma->vm_flags & VM_EXEC) | |
687 | __inv_icache_page(paddr, u_vaddr); | |
4102b533 VG |
688 | } |
689 | ||
690 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
691 | unsigned long end) | |
692 | { | |
693 | flush_cache_all(); | |
694 | } | |
695 | ||
7bb66f6e VG |
696 | void flush_anon_page(struct vm_area_struct *vma, struct page *page, |
697 | unsigned long u_vaddr) | |
698 | { | |
699 | /* TBD: do we really need to clear the kernel mapping */ | |
700 | __flush_dcache_page(page_address(page), u_vaddr); | |
701 | __flush_dcache_page(page_address(page), page_address(page)); | |
702 | ||
703 | } | |
704 | ||
705 | #endif | |
706 | ||
4102b533 VG |
707 | void copy_user_highpage(struct page *to, struct page *from, |
708 | unsigned long u_vaddr, struct vm_area_struct *vma) | |
709 | { | |
710 | void *kfrom = page_address(from); | |
711 | void *kto = page_address(to); | |
712 | int clean_src_k_mappings = 0; | |
713 | ||
714 | /* | |
715 | * If SRC page was already mapped in userspace AND it's U-mapping is | |
716 | * not congruent with K-mapping, sync former to physical page so that | |
717 | * K-mapping in memcpy below, sees the right data | |
718 | * | |
719 | * Note that while @u_vaddr refers to DST page's userspace vaddr, it is | |
720 | * equally valid for SRC page as well | |
721 | */ | |
722 | if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { | |
723 | __flush_dcache_page(kfrom, u_vaddr); | |
724 | clean_src_k_mappings = 1; | |
725 | } | |
726 | ||
727 | copy_page(kto, kfrom); | |
728 | ||
729 | /* | |
730 | * Mark DST page K-mapping as dirty for a later finalization by | |
731 | * update_mmu_cache(). Although the finalization could have been done | |
732 | * here as well (given that both vaddr/paddr are available). | |
733 | * But update_mmu_cache() already has code to do that for other | |
734 | * non copied user pages (e.g. read faults which wire in pagecache page | |
735 | * directly). | |
736 | */ | |
737 | set_bit(PG_arch_1, &to->flags); | |
738 | ||
739 | /* | |
740 | * if SRC was already usermapped and non-congruent to kernel mapping | |
741 | * sync the kernel mapping back to physical page | |
742 | */ | |
743 | if (clean_src_k_mappings) { | |
744 | __flush_dcache_page(kfrom, kfrom); | |
fedf5b9b | 745 | clear_bit(PG_arch_1, &from->flags); |
4102b533 VG |
746 | } else { |
747 | set_bit(PG_arch_1, &from->flags); | |
748 | } | |
749 | } | |
750 | ||
751 | void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) | |
752 | { | |
753 | clear_page(to); | |
754 | set_bit(PG_arch_1, &page->flags); | |
755 | } | |
756 | ||
4102b533 | 757 | |
95d6976d VG |
758 | /********************************************************************** |
759 | * Explicit Cache flush request from user space via syscall | |
760 | * Needed for JITs which generate code on the fly | |
761 | */ | |
762 | SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) | |
763 | { | |
764 | /* TBD: optimize this */ | |
765 | flush_cache_all(); | |
766 | return 0; | |
767 | } |