Commit | Line | Data |
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95d6976d | 1 | /* |
8ea2ddff | 2 | * ARC Cache Management |
95d6976d | 3 | * |
8ea2ddff | 4 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
95d6976d VG |
5 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
95d6976d VG |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/cache.h> | |
16 | #include <linux/mmu_context.h> | |
17 | #include <linux/syscalls.h> | |
18 | #include <linux/uaccess.h> | |
4102b533 | 19 | #include <linux/pagemap.h> |
95d6976d VG |
20 | #include <asm/cacheflush.h> |
21 | #include <asm/cachectl.h> | |
22 | #include <asm/setup.h> | |
23 | ||
795f4558 | 24 | static int l2_line_sz; |
f2b0b25a | 25 | int ioc_exists; |
1648c70d | 26 | volatile int slc_enable = 1, ioc_enable = 1; |
795f4558 | 27 | |
bcc4d65a VG |
28 | void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr, |
29 | unsigned long sz, const int cacheop); | |
30 | ||
f2b0b25a AB |
31 | void (*__dma_cache_wback_inv)(unsigned long start, unsigned long sz); |
32 | void (*__dma_cache_inv)(unsigned long start, unsigned long sz); | |
33 | void (*__dma_cache_wback)(unsigned long start, unsigned long sz); | |
34 | ||
c3441edd | 35 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
af617428 VG |
36 | { |
37 | int n = 0; | |
d1f317d8 | 38 | struct cpuinfo_arc_cache *p; |
af617428 | 39 | |
da40ff48 | 40 | #define PR_CACHE(p, cfg, str) \ |
af617428 VG |
41 | if (!(p)->ver) \ |
42 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ | |
43 | else \ | |
44 | n += scnprintf(buf + n, len - n, \ | |
da40ff48 VG |
45 | str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ |
46 | (p)->sz_k, (p)->assoc, (p)->line_len, \ | |
47 | (p)->vipt ? "VIPT" : "PIPT", \ | |
48 | (p)->alias ? " aliasing" : "", \ | |
964cf28f | 49 | IS_USED_CFG(cfg)); |
af617428 | 50 | |
da40ff48 VG |
51 | PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); |
52 | PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); | |
af617428 | 53 | |
fd0881a2 VG |
54 | if (!is_isa_arcv2()) |
55 | return buf; | |
56 | ||
d1f317d8 VG |
57 | p = &cpuinfo_arc700[c].slc; |
58 | if (p->ver) | |
59 | n += scnprintf(buf + n, len - n, | |
79335a2c VG |
60 | "SLC\t\t: %uK, %uB Line%s\n", |
61 | p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); | |
d1f317d8 | 62 | |
f2b0b25a | 63 | if (ioc_exists) |
1648c70d | 64 | n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n", |
964cf28f | 65 | IS_DISABLED_RUN(ioc_enable)); |
f2b0b25a | 66 | |
af617428 VG |
67 | return buf; |
68 | } | |
69 | ||
95d6976d VG |
70 | /* |
71 | * Read the Cache Build Confuration Registers, Decode them and save into | |
72 | * the cpuinfo structure for later use. | |
73 | * No Validation done here, simply read/convert the BCRs | |
74 | */ | |
fd0881a2 | 75 | static void read_decode_cache_bcr_arcv2(int cpu) |
95d6976d | 76 | { |
fd0881a2 | 77 | struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc; |
d1f317d8 VG |
78 | struct bcr_generic sbcr; |
79 | ||
80 | struct bcr_slc_cfg { | |
81 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
82 | unsigned int pad:24, way:2, lsz:2, sz:4; | |
83 | #else | |
84 | unsigned int sz:4, lsz:2, way:2, pad:24; | |
85 | #endif | |
86 | } slc_cfg; | |
87 | ||
f2b0b25a AB |
88 | struct bcr_clust_cfg { |
89 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
90 | unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; | |
91 | #else | |
92 | unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; | |
93 | #endif | |
94 | } cbcr; | |
95 | ||
fd0881a2 VG |
96 | READ_BCR(ARC_REG_SLC_BCR, sbcr); |
97 | if (sbcr.ver) { | |
98 | READ_BCR(ARC_REG_SLC_CFG, slc_cfg); | |
99 | p_slc->ver = sbcr.ver; | |
100 | p_slc->sz_k = 128 << slc_cfg.sz; | |
101 | l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; | |
102 | } | |
103 | ||
104 | READ_BCR(ARC_REG_CLUSTER_BCR, cbcr); | |
105 | if (cbcr.c && ioc_enable) | |
106 | ioc_exists = 1; | |
107 | } | |
108 | ||
109 | void read_decode_cache_bcr(void) | |
110 | { | |
111 | struct cpuinfo_arc_cache *p_ic, *p_dc; | |
112 | unsigned int cpu = smp_processor_id(); | |
113 | struct bcr_cache { | |
114 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
115 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
116 | #else | |
117 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
118 | #endif | |
119 | } ibcr, dbcr; | |
120 | ||
95d6976d VG |
121 | p_ic = &cpuinfo_arc700[cpu].icache; |
122 | READ_BCR(ARC_REG_IC_BCR, ibcr); | |
123 | ||
da40ff48 VG |
124 | if (!ibcr.ver) |
125 | goto dc_chk; | |
126 | ||
d1f317d8 VG |
127 | if (ibcr.ver <= 3) { |
128 | BUG_ON(ibcr.config != 3); | |
129 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ | |
130 | } else if (ibcr.ver >= 4) { | |
131 | p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */ | |
132 | } | |
133 | ||
95d6976d | 134 | p_ic->line_len = 8 << ibcr.line_len; |
da40ff48 | 135 | p_ic->sz_k = 1 << (ibcr.sz - 1); |
95d6976d | 136 | p_ic->ver = ibcr.ver; |
da40ff48 VG |
137 | p_ic->vipt = 1; |
138 | p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; | |
95d6976d | 139 | |
da40ff48 | 140 | dc_chk: |
95d6976d VG |
141 | p_dc = &cpuinfo_arc700[cpu].dcache; |
142 | READ_BCR(ARC_REG_DC_BCR, dbcr); | |
143 | ||
da40ff48 | 144 | if (!dbcr.ver) |
d1f317d8 VG |
145 | goto slc_chk; |
146 | ||
147 | if (dbcr.ver <= 3) { | |
148 | BUG_ON(dbcr.config != 2); | |
149 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ | |
150 | p_dc->vipt = 1; | |
151 | p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; | |
152 | } else if (dbcr.ver >= 4) { | |
153 | p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */ | |
154 | p_dc->vipt = 0; | |
155 | p_dc->alias = 0; /* PIPT so can't VIPT alias */ | |
156 | } | |
da40ff48 | 157 | |
95d6976d | 158 | p_dc->line_len = 16 << dbcr.line_len; |
da40ff48 | 159 | p_dc->sz_k = 1 << (dbcr.sz - 1); |
95d6976d | 160 | p_dc->ver = dbcr.ver; |
d1f317d8 VG |
161 | |
162 | slc_chk: | |
fd0881a2 VG |
163 | if (is_isa_arcv2()) |
164 | read_decode_cache_bcr_arcv2(cpu); | |
95d6976d VG |
165 | } |
166 | ||
167 | /* | |
8ea2ddff | 168 | * Line Operation on {I,D}-Cache |
95d6976d | 169 | */ |
95d6976d VG |
170 | |
171 | #define OP_INV 0x1 | |
172 | #define OP_FLUSH 0x2 | |
173 | #define OP_FLUSH_N_INV 0x3 | |
bd12976c VG |
174 | #define OP_INV_IC 0x4 |
175 | ||
176 | /* | |
8ea2ddff VG |
177 | * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3) |
178 | * | |
179 | * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. | |
180 | * The orig Cache Management Module "CDU" only required paddr to invalidate a | |
181 | * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. | |
182 | * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching | |
183 | * the exact same line. | |
184 | * | |
185 | * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, | |
186 | * paddr alone could not be used to correctly index the cache. | |
187 | * | |
188 | * ------------------ | |
189 | * MMU v1/v2 (Fixed Page Size 8k) | |
190 | * ------------------ | |
191 | * The solution was to provide CDU with these additonal vaddr bits. These | |
192 | * would be bits [x:13], x would depend on cache-geometry, 13 comes from | |
193 | * standard page size of 8k. | |
194 | * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits | |
195 | * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the | |
196 | * orig 5 bits of paddr were anyways ignored by CDU line ops, as they | |
197 | * represent the offset within cache-line. The adv of using this "clumsy" | |
198 | * interface for additional info was no new reg was needed in CDU programming | |
199 | * model. | |
200 | * | |
201 | * 17:13 represented the max num of bits passable, actual bits needed were | |
202 | * fewer, based on the num-of-aliases possible. | |
203 | * -for 2 alias possibility, only bit 13 needed (32K cache) | |
204 | * -for 4 alias possibility, bits 14:13 needed (64K cache) | |
205 | * | |
206 | * ------------------ | |
207 | * MMU v3 | |
208 | * ------------------ | |
209 | * This ver of MMU supports variable page sizes (1k-16k): although Linux will | |
210 | * only support 8k (default), 16k and 4k. | |
211 | * However from hardware perspective, smaller page sizes aggrevate aliasing | |
212 | * meaning more vaddr bits needed to disambiguate the cache-line-op ; | |
213 | * the existing scheme of piggybacking won't work for certain configurations. | |
214 | * Two new registers IC_PTAG and DC_PTAG inttoduced. | |
215 | * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs | |
bd12976c | 216 | */ |
8ea2ddff | 217 | |
11e14896 VG |
218 | static inline |
219 | void __cache_line_loop_v2(unsigned long paddr, unsigned long vaddr, | |
220 | unsigned long sz, const int op) | |
bd12976c | 221 | { |
11e14896 | 222 | unsigned int aux_cmd; |
bd12976c | 223 | int num_lines; |
11e14896 | 224 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; |
bd12976c | 225 | |
8ea2ddff | 226 | if (op == OP_INV_IC) { |
bd12976c | 227 | aux_cmd = ARC_REG_IC_IVIL; |
11e14896 | 228 | } else { |
bd12976c | 229 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ |
8ea2ddff | 230 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; |
bd12976c VG |
231 | } |
232 | ||
233 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
234 | * and have @paddr - aligned to cache line and integral @num_lines. | |
235 | * This however can be avoided for page sized since: | |
236 | * -@paddr will be cache-line aligned already (being page aligned) | |
237 | * -@sz will be integral multiple of line size (being page sized). | |
238 | */ | |
11e14896 | 239 | if (!full_page) { |
bd12976c VG |
240 | sz += paddr & ~CACHE_LINE_MASK; |
241 | paddr &= CACHE_LINE_MASK; | |
242 | vaddr &= CACHE_LINE_MASK; | |
243 | } | |
244 | ||
245 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
246 | ||
bd12976c VG |
247 | /* MMUv2 and before: paddr contains stuffed vaddrs bits */ |
248 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; | |
11e14896 VG |
249 | |
250 | while (num_lines-- > 0) { | |
251 | write_aux_reg(aux_cmd, paddr); | |
252 | paddr += L1_CACHE_BYTES; | |
253 | } | |
254 | } | |
255 | ||
256 | static inline | |
257 | void __cache_line_loop_v3(unsigned long paddr, unsigned long vaddr, | |
258 | unsigned long sz, const int op) | |
259 | { | |
260 | unsigned int aux_cmd, aux_tag; | |
261 | int num_lines; | |
262 | const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
263 | ||
264 | if (op == OP_INV_IC) { | |
265 | aux_cmd = ARC_REG_IC_IVIL; | |
266 | aux_tag = ARC_REG_IC_PTAG; | |
267 | } else { | |
268 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
269 | aux_tag = ARC_REG_DC_PTAG; | |
270 | } | |
271 | ||
272 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
273 | * and have @paddr - aligned to cache line and integral @num_lines. | |
274 | * This however can be avoided for page sized since: | |
275 | * -@paddr will be cache-line aligned already (being page aligned) | |
276 | * -@sz will be integral multiple of line size (being page sized). | |
277 | */ | |
278 | if (!full_page) { | |
279 | sz += paddr & ~CACHE_LINE_MASK; | |
280 | paddr &= CACHE_LINE_MASK; | |
281 | vaddr &= CACHE_LINE_MASK; | |
282 | } | |
283 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
284 | ||
285 | /* | |
286 | * MMUv3, cache ops require paddr in PTAG reg | |
287 | * if V-P const for loop, PTAG can be written once outside loop | |
288 | */ | |
289 | if (full_page) | |
b053940d | 290 | write_aux_reg(aux_tag, paddr); |
bd12976c VG |
291 | |
292 | while (num_lines-- > 0) { | |
11e14896 | 293 | if (!full_page) { |
d4599baf VG |
294 | write_aux_reg(aux_tag, paddr); |
295 | paddr += L1_CACHE_BYTES; | |
296 | } | |
bd12976c VG |
297 | |
298 | write_aux_reg(aux_cmd, vaddr); | |
299 | vaddr += L1_CACHE_BYTES; | |
bd12976c VG |
300 | } |
301 | } | |
95d6976d | 302 | |
d1f317d8 VG |
303 | /* |
304 | * In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache | |
305 | * maintenance ops (in IVIL reg), as long as icache doesn't alias. | |
306 | * | |
307 | * For Aliasing icache, vaddr is also needed (in IVIL), while paddr is | |
308 | * specified in PTAG (similar to MMU v3) | |
309 | */ | |
310 | static inline | |
311 | void __cache_line_loop_v4(unsigned long paddr, unsigned long vaddr, | |
312 | unsigned long sz, const int cacheop) | |
313 | { | |
314 | unsigned int aux_cmd; | |
315 | int num_lines; | |
316 | const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; | |
317 | ||
318 | if (cacheop == OP_INV_IC) { | |
319 | aux_cmd = ARC_REG_IC_IVIL; | |
320 | } else { | |
321 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ | |
322 | aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; | |
323 | } | |
324 | ||
325 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
326 | * and have @paddr - aligned to cache line and integral @num_lines. | |
327 | * This however can be avoided for page sized since: | |
328 | * -@paddr will be cache-line aligned already (being page aligned) | |
329 | * -@sz will be integral multiple of line size (being page sized). | |
330 | */ | |
331 | if (!full_page_op) { | |
332 | sz += paddr & ~CACHE_LINE_MASK; | |
333 | paddr &= CACHE_LINE_MASK; | |
334 | } | |
335 | ||
336 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
337 | ||
338 | while (num_lines-- > 0) { | |
339 | write_aux_reg(aux_cmd, paddr); | |
340 | paddr += L1_CACHE_BYTES; | |
341 | } | |
342 | } | |
343 | ||
11e14896 VG |
344 | #if (CONFIG_ARC_MMU_VER < 3) |
345 | #define __cache_line_loop __cache_line_loop_v2 | |
346 | #elif (CONFIG_ARC_MMU_VER == 3) | |
347 | #define __cache_line_loop __cache_line_loop_v3 | |
d1f317d8 VG |
348 | #elif (CONFIG_ARC_MMU_VER > 3) |
349 | #define __cache_line_loop __cache_line_loop_v4 | |
11e14896 VG |
350 | #endif |
351 | ||
95d6976d VG |
352 | #ifdef CONFIG_ARC_HAS_DCACHE |
353 | ||
354 | /*************************************************************** | |
355 | * Machine specific helpers for Entire D-Cache or Per Line ops | |
356 | */ | |
357 | ||
6c310681 | 358 | static inline void __before_dc_op(const int op) |
95d6976d | 359 | { |
1b1a22b1 VG |
360 | if (op == OP_FLUSH_N_INV) { |
361 | /* Dcache provides 2 cmd: FLUSH or INV | |
362 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
363 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
364 | * So toggle INV sub-mode depending on op request and default | |
365 | */ | |
6c310681 VG |
366 | const unsigned int ctl = ARC_REG_DC_CTRL; |
367 | write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); | |
1b1a22b1 | 368 | } |
1b1a22b1 VG |
369 | } |
370 | ||
6c310681 | 371 | static inline void __after_dc_op(const int op) |
1b1a22b1 | 372 | { |
6c310681 VG |
373 | if (op & OP_FLUSH) { |
374 | const unsigned int ctl = ARC_REG_DC_CTRL; | |
375 | unsigned int reg; | |
1b1a22b1 | 376 | |
6c310681 VG |
377 | /* flush / flush-n-inv both wait */ |
378 | while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) | |
379 | ; | |
380 | ||
381 | /* Switch back to default Invalidate mode */ | |
382 | if (op == OP_FLUSH_N_INV) | |
383 | write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); | |
384 | } | |
95d6976d VG |
385 | } |
386 | ||
387 | /* | |
388 | * Operation on Entire D-Cache | |
8ea2ddff | 389 | * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} |
95d6976d VG |
390 | * Note that constant propagation ensures all the checks are gone |
391 | * in generated code | |
392 | */ | |
8ea2ddff | 393 | static inline void __dc_entire_op(const int op) |
95d6976d | 394 | { |
95d6976d VG |
395 | int aux; |
396 | ||
6c310681 | 397 | __before_dc_op(op); |
95d6976d | 398 | |
8ea2ddff | 399 | if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ |
95d6976d VG |
400 | aux = ARC_REG_DC_IVDC; |
401 | else | |
402 | aux = ARC_REG_DC_FLSH; | |
403 | ||
404 | write_aux_reg(aux, 0x1); | |
405 | ||
6c310681 | 406 | __after_dc_op(op); |
95d6976d VG |
407 | } |
408 | ||
4102b533 | 409 | /* For kernel mappings cache operation: index is same as paddr */ |
6ec18a81 VG |
410 | #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) |
411 | ||
95d6976d | 412 | /* |
8ea2ddff | 413 | * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback) |
95d6976d | 414 | */ |
6ec18a81 | 415 | static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, |
8ea2ddff | 416 | unsigned long sz, const int op) |
95d6976d | 417 | { |
1b1a22b1 | 418 | unsigned long flags; |
95d6976d VG |
419 | |
420 | local_irq_save(flags); | |
421 | ||
6c310681 | 422 | __before_dc_op(op); |
95d6976d | 423 | |
8ea2ddff | 424 | __cache_line_loop(paddr, vaddr, sz, op); |
95d6976d | 425 | |
6c310681 | 426 | __after_dc_op(op); |
95d6976d VG |
427 | |
428 | local_irq_restore(flags); | |
429 | } | |
430 | ||
431 | #else | |
432 | ||
8ea2ddff VG |
433 | #define __dc_entire_op(op) |
434 | #define __dc_line_op(paddr, vaddr, sz, op) | |
435 | #define __dc_line_op_k(paddr, sz, op) | |
95d6976d VG |
436 | |
437 | #endif /* CONFIG_ARC_HAS_DCACHE */ | |
438 | ||
95d6976d VG |
439 | #ifdef CONFIG_ARC_HAS_ICACHE |
440 | ||
af5abf1b VG |
441 | static inline void __ic_entire_inv(void) |
442 | { | |
443 | write_aux_reg(ARC_REG_IC_IVIC, 1); | |
444 | read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
445 | } | |
446 | ||
447 | static inline void | |
448 | __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, | |
449 | unsigned long sz) | |
95d6976d VG |
450 | { |
451 | unsigned long flags; | |
95d6976d VG |
452 | |
453 | local_irq_save(flags); | |
bcc4d65a | 454 | (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); |
95d6976d VG |
455 | local_irq_restore(flags); |
456 | } | |
457 | ||
af5abf1b VG |
458 | #ifndef CONFIG_SMP |
459 | ||
460 | #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) | |
461 | ||
462 | #else | |
336e199e | 463 | |
af5abf1b | 464 | struct ic_inv_args { |
2328af0c VG |
465 | unsigned long paddr, vaddr; |
466 | int sz; | |
467 | }; | |
468 | ||
469 | static void __ic_line_inv_vaddr_helper(void *info) | |
470 | { | |
014018e0 | 471 | struct ic_inv_args *ic_inv = info; |
af5abf1b | 472 | |
2328af0c VG |
473 | __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); |
474 | } | |
475 | ||
476 | static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, | |
477 | unsigned long sz) | |
478 | { | |
af5abf1b VG |
479 | struct ic_inv_args ic_inv = { |
480 | .paddr = paddr, | |
481 | .vaddr = vaddr, | |
482 | .sz = sz | |
483 | }; | |
484 | ||
2328af0c VG |
485 | on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); |
486 | } | |
af5abf1b VG |
487 | |
488 | #endif /* CONFIG_SMP */ | |
489 | ||
490 | #else /* !CONFIG_ARC_HAS_ICACHE */ | |
95d6976d | 491 | |
336e199e | 492 | #define __ic_entire_inv() |
95d6976d VG |
493 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
494 | ||
495 | #endif /* CONFIG_ARC_HAS_ICACHE */ | |
496 | ||
795f4558 VG |
497 | noinline void slc_op(unsigned long paddr, unsigned long sz, const int op) |
498 | { | |
499 | #ifdef CONFIG_ISA_ARCV2 | |
b607eddd AB |
500 | /* |
501 | * SLC is shared between all cores and concurrent aux operations from | |
502 | * multiple cores need to be serialized using a spinlock | |
503 | * A concurrent operation can be silently ignored and/or the old/new | |
504 | * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop | |
505 | * below) | |
506 | */ | |
507 | static DEFINE_SPINLOCK(lock); | |
795f4558 VG |
508 | unsigned long flags; |
509 | unsigned int ctrl; | |
510 | ||
b607eddd | 511 | spin_lock_irqsave(&lock, flags); |
795f4558 VG |
512 | |
513 | /* | |
514 | * The Region Flush operation is specified by CTRL.RGN_OP[11..9] | |
515 | * - b'000 (default) is Flush, | |
516 | * - b'001 is Invalidate if CTRL.IM == 0 | |
517 | * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 | |
518 | */ | |
519 | ctrl = read_aux_reg(ARC_REG_SLC_CTRL); | |
520 | ||
521 | /* Don't rely on default value of IM bit */ | |
522 | if (!(op & OP_FLUSH)) /* i.e. OP_INV */ | |
523 | ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ | |
524 | else | |
525 | ctrl |= SLC_CTRL_IM; | |
526 | ||
527 | if (op & OP_INV) | |
528 | ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ | |
529 | else | |
530 | ctrl &= ~SLC_CTRL_RGN_OP_INV; | |
531 | ||
532 | write_aux_reg(ARC_REG_SLC_CTRL, ctrl); | |
533 | ||
534 | /* | |
535 | * Lower bits are ignored, no need to clip | |
536 | * END needs to be setup before START (latter triggers the operation) | |
537 | * END can't be same as START, so add (l2_line_sz - 1) to sz | |
538 | */ | |
539 | write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); | |
540 | write_aux_reg(ARC_REG_SLC_RGN_START, paddr); | |
541 | ||
542 | while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); | |
543 | ||
b607eddd | 544 | spin_unlock_irqrestore(&lock, flags); |
795f4558 VG |
545 | #endif |
546 | } | |
547 | ||
95d6976d VG |
548 | /*********************************************************** |
549 | * Exported APIs | |
550 | */ | |
551 | ||
4102b533 VG |
552 | /* |
553 | * Handle cache congruency of kernel and userspace mappings of page when kernel | |
554 | * writes-to/reads-from | |
555 | * | |
556 | * The idea is to defer flushing of kernel mapping after a WRITE, possible if: | |
557 | * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent | |
558 | * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) | |
559 | * -In SMP, if hardware caches are coherent | |
560 | * | |
561 | * There's a corollary case, where kernel READs from a userspace mapped page. | |
562 | * If the U-mapping is not congruent to to K-mapping, former needs flushing. | |
563 | */ | |
95d6976d VG |
564 | void flush_dcache_page(struct page *page) |
565 | { | |
4102b533 VG |
566 | struct address_space *mapping; |
567 | ||
568 | if (!cache_is_vipt_aliasing()) { | |
2ed21dae | 569 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
570 | return; |
571 | } | |
572 | ||
573 | /* don't handle anon pages here */ | |
574 | mapping = page_mapping(page); | |
575 | if (!mapping) | |
576 | return; | |
577 | ||
578 | /* | |
579 | * pagecache page, file not yet mapped to userspace | |
580 | * Make a note that K-mapping is dirty | |
581 | */ | |
582 | if (!mapping_mapped(mapping)) { | |
2ed21dae | 583 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
584 | } else if (page_mapped(page)) { |
585 | ||
586 | /* kernel reading from page with U-mapping */ | |
45309493 | 587 | unsigned long paddr = (unsigned long)page_address(page); |
4102b533 VG |
588 | unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; |
589 | ||
590 | if (addr_not_cache_congruent(paddr, vaddr)) | |
591 | __flush_dcache_page(paddr, vaddr); | |
592 | } | |
95d6976d VG |
593 | } |
594 | EXPORT_SYMBOL(flush_dcache_page); | |
595 | ||
f2b0b25a AB |
596 | /* |
597 | * DMA ops for systems with L1 cache only | |
598 | * Make memory coherent with L1 cache by flushing/invalidating L1 lines | |
599 | */ | |
600 | static void __dma_cache_wback_inv_l1(unsigned long start, unsigned long sz) | |
95d6976d | 601 | { |
6ec18a81 | 602 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); |
f2b0b25a | 603 | } |
795f4558 | 604 | |
f2b0b25a AB |
605 | static void __dma_cache_inv_l1(unsigned long start, unsigned long sz) |
606 | { | |
607 | __dc_line_op_k(start, sz, OP_INV); | |
95d6976d | 608 | } |
95d6976d | 609 | |
f2b0b25a AB |
610 | static void __dma_cache_wback_l1(unsigned long start, unsigned long sz) |
611 | { | |
612 | __dc_line_op_k(start, sz, OP_FLUSH); | |
613 | } | |
614 | ||
615 | /* | |
616 | * DMA ops for systems with both L1 and L2 caches, but without IOC | |
617 | * Both L1 and L2 lines need to be explicity flushed/invalidated | |
618 | */ | |
619 | static void __dma_cache_wback_inv_slc(unsigned long start, unsigned long sz) | |
620 | { | |
621 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); | |
622 | slc_op(start, sz, OP_FLUSH_N_INV); | |
623 | } | |
624 | ||
625 | static void __dma_cache_inv_slc(unsigned long start, unsigned long sz) | |
95d6976d | 626 | { |
6ec18a81 | 627 | __dc_line_op_k(start, sz, OP_INV); |
f2b0b25a AB |
628 | slc_op(start, sz, OP_INV); |
629 | } | |
795f4558 | 630 | |
f2b0b25a AB |
631 | static void __dma_cache_wback_slc(unsigned long start, unsigned long sz) |
632 | { | |
633 | __dc_line_op_k(start, sz, OP_FLUSH); | |
634 | slc_op(start, sz, OP_FLUSH); | |
635 | } | |
636 | ||
637 | /* | |
638 | * DMA ops for systems with IOC | |
639 | * IOC hardware snoops all DMA traffic keeping the caches consistent with | |
640 | * memory - eliding need for any explicit cache maintenance of DMA buffers | |
641 | */ | |
642 | static void __dma_cache_wback_inv_ioc(unsigned long start, unsigned long sz) {} | |
643 | static void __dma_cache_inv_ioc(unsigned long start, unsigned long sz) {} | |
644 | static void __dma_cache_wback_ioc(unsigned long start, unsigned long sz) {} | |
645 | ||
646 | /* | |
647 | * Exported DMA API | |
648 | */ | |
649 | void dma_cache_wback_inv(unsigned long start, unsigned long sz) | |
650 | { | |
651 | __dma_cache_wback_inv(start, sz); | |
652 | } | |
653 | EXPORT_SYMBOL(dma_cache_wback_inv); | |
654 | ||
655 | void dma_cache_inv(unsigned long start, unsigned long sz) | |
656 | { | |
657 | __dma_cache_inv(start, sz); | |
95d6976d VG |
658 | } |
659 | EXPORT_SYMBOL(dma_cache_inv); | |
660 | ||
661 | void dma_cache_wback(unsigned long start, unsigned long sz) | |
662 | { | |
f2b0b25a | 663 | __dma_cache_wback(start, sz); |
95d6976d VG |
664 | } |
665 | EXPORT_SYMBOL(dma_cache_wback); | |
666 | ||
667 | /* | |
7586bf72 VG |
668 | * This is API for making I/D Caches consistent when modifying |
669 | * kernel code (loadable modules, kprobes, kgdb...) | |
95d6976d VG |
670 | * This is called on insmod, with kernel virtual address for CODE of |
671 | * the module. ARC cache maintenance ops require PHY address thus we | |
672 | * need to convert vmalloc addr to PHY addr | |
673 | */ | |
674 | void flush_icache_range(unsigned long kstart, unsigned long kend) | |
675 | { | |
c59414cc | 676 | unsigned int tot_sz; |
95d6976d | 677 | |
c59414cc | 678 | WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); |
95d6976d VG |
679 | |
680 | /* Shortcut for bigger flush ranges. | |
681 | * Here we don't care if this was kernel virtual or phy addr | |
682 | */ | |
683 | tot_sz = kend - kstart; | |
684 | if (tot_sz > PAGE_SIZE) { | |
685 | flush_cache_all(); | |
686 | return; | |
687 | } | |
688 | ||
689 | /* Case: Kernel Phy addr (0x8000_0000 onwards) */ | |
690 | if (likely(kstart > PAGE_OFFSET)) { | |
7586bf72 VG |
691 | /* |
692 | * The 2nd arg despite being paddr will be used to index icache | |
693 | * This is OK since no alternate virtual mappings will exist | |
694 | * given the callers for this case: kprobe/kgdb in built-in | |
695 | * kernel code only. | |
696 | */ | |
94bad1af | 697 | __sync_icache_dcache(kstart, kstart, kend - kstart); |
95d6976d VG |
698 | return; |
699 | } | |
700 | ||
701 | /* | |
702 | * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) | |
703 | * (1) ARC Cache Maintenance ops only take Phy addr, hence special | |
704 | * handling of kernel vaddr. | |
705 | * | |
706 | * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), | |
707 | * it still needs to handle a 2 page scenario, where the range | |
708 | * straddles across 2 virtual pages and hence need for loop | |
709 | */ | |
710 | while (tot_sz > 0) { | |
c59414cc VG |
711 | unsigned int off, sz; |
712 | unsigned long phy, pfn; | |
713 | ||
95d6976d VG |
714 | off = kstart % PAGE_SIZE; |
715 | pfn = vmalloc_to_pfn((void *)kstart); | |
716 | phy = (pfn << PAGE_SHIFT) + off; | |
717 | sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); | |
94bad1af | 718 | __sync_icache_dcache(phy, kstart, sz); |
95d6976d VG |
719 | kstart += sz; |
720 | tot_sz -= sz; | |
721 | } | |
722 | } | |
e3560305 | 723 | EXPORT_SYMBOL(flush_icache_range); |
95d6976d VG |
724 | |
725 | /* | |
94bad1af VG |
726 | * General purpose helper to make I and D cache lines consistent. |
727 | * @paddr is phy addr of region | |
4b06ff35 VG |
728 | * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) |
729 | * However in one instance, when called by kprobe (for a breakpt in | |
94bad1af VG |
730 | * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will |
731 | * use a paddr to index the cache (despite VIPT). This is fine since since a | |
4b06ff35 VG |
732 | * builtin kernel page will not have any virtual mappings. |
733 | * kprobe on loadable module will be kernel vaddr. | |
95d6976d | 734 | */ |
94bad1af | 735 | void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) |
95d6976d | 736 | { |
f538881c | 737 | __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); |
2328af0c | 738 | __ic_line_inv_vaddr(paddr, vaddr, len); |
95d6976d VG |
739 | } |
740 | ||
24603fdd VG |
741 | /* wrapper to compile time eliminate alignment checks in flush loop */ |
742 | void __inv_icache_page(unsigned long paddr, unsigned long vaddr) | |
95d6976d | 743 | { |
24603fdd | 744 | __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); |
95d6976d VG |
745 | } |
746 | ||
6ec18a81 VG |
747 | /* |
748 | * wrapper to clearout kernel or userspace mappings of a page | |
749 | * For kernel mappings @vaddr == @paddr | |
750 | */ | |
45309493 | 751 | void __flush_dcache_page(unsigned long paddr, unsigned long vaddr) |
eacd0e95 | 752 | { |
6ec18a81 | 753 | __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); |
eacd0e95 VG |
754 | } |
755 | ||
95d6976d VG |
756 | noinline void flush_cache_all(void) |
757 | { | |
758 | unsigned long flags; | |
759 | ||
760 | local_irq_save(flags); | |
761 | ||
336e199e | 762 | __ic_entire_inv(); |
95d6976d VG |
763 | __dc_entire_op(OP_FLUSH_N_INV); |
764 | ||
765 | local_irq_restore(flags); | |
766 | ||
767 | } | |
768 | ||
4102b533 VG |
769 | #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING |
770 | ||
771 | void flush_cache_mm(struct mm_struct *mm) | |
772 | { | |
773 | flush_cache_all(); | |
774 | } | |
775 | ||
776 | void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, | |
777 | unsigned long pfn) | |
778 | { | |
779 | unsigned int paddr = pfn << PAGE_SHIFT; | |
780 | ||
5971bc71 VG |
781 | u_vaddr &= PAGE_MASK; |
782 | ||
45309493 | 783 | __flush_dcache_page(paddr, u_vaddr); |
5971bc71 VG |
784 | |
785 | if (vma->vm_flags & VM_EXEC) | |
786 | __inv_icache_page(paddr, u_vaddr); | |
4102b533 VG |
787 | } |
788 | ||
789 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
790 | unsigned long end) | |
791 | { | |
792 | flush_cache_all(); | |
793 | } | |
794 | ||
7bb66f6e VG |
795 | void flush_anon_page(struct vm_area_struct *vma, struct page *page, |
796 | unsigned long u_vaddr) | |
797 | { | |
798 | /* TBD: do we really need to clear the kernel mapping */ | |
799 | __flush_dcache_page(page_address(page), u_vaddr); | |
800 | __flush_dcache_page(page_address(page), page_address(page)); | |
801 | ||
802 | } | |
803 | ||
804 | #endif | |
805 | ||
4102b533 VG |
806 | void copy_user_highpage(struct page *to, struct page *from, |
807 | unsigned long u_vaddr, struct vm_area_struct *vma) | |
808 | { | |
336e2136 VG |
809 | void *kfrom = kmap_atomic(from); |
810 | void *kto = kmap_atomic(to); | |
4102b533 VG |
811 | int clean_src_k_mappings = 0; |
812 | ||
813 | /* | |
814 | * If SRC page was already mapped in userspace AND it's U-mapping is | |
815 | * not congruent with K-mapping, sync former to physical page so that | |
816 | * K-mapping in memcpy below, sees the right data | |
817 | * | |
818 | * Note that while @u_vaddr refers to DST page's userspace vaddr, it is | |
819 | * equally valid for SRC page as well | |
336e2136 VG |
820 | * |
821 | * For !VIPT cache, all of this gets compiled out as | |
822 | * addr_not_cache_congruent() is 0 | |
4102b533 VG |
823 | */ |
824 | if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { | |
336e2136 | 825 | __flush_dcache_page((unsigned long)kfrom, u_vaddr); |
4102b533 VG |
826 | clean_src_k_mappings = 1; |
827 | } | |
828 | ||
336e2136 | 829 | copy_page(kto, kfrom); |
4102b533 VG |
830 | |
831 | /* | |
832 | * Mark DST page K-mapping as dirty for a later finalization by | |
833 | * update_mmu_cache(). Although the finalization could have been done | |
834 | * here as well (given that both vaddr/paddr are available). | |
835 | * But update_mmu_cache() already has code to do that for other | |
836 | * non copied user pages (e.g. read faults which wire in pagecache page | |
837 | * directly). | |
838 | */ | |
2ed21dae | 839 | clear_bit(PG_dc_clean, &to->flags); |
4102b533 VG |
840 | |
841 | /* | |
842 | * if SRC was already usermapped and non-congruent to kernel mapping | |
843 | * sync the kernel mapping back to physical page | |
844 | */ | |
845 | if (clean_src_k_mappings) { | |
336e2136 | 846 | __flush_dcache_page((unsigned long)kfrom, (unsigned long)kfrom); |
2ed21dae | 847 | set_bit(PG_dc_clean, &from->flags); |
4102b533 | 848 | } else { |
2ed21dae | 849 | clear_bit(PG_dc_clean, &from->flags); |
4102b533 | 850 | } |
336e2136 VG |
851 | |
852 | kunmap_atomic(kto); | |
853 | kunmap_atomic(kfrom); | |
4102b533 VG |
854 | } |
855 | ||
856 | void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) | |
857 | { | |
858 | clear_page(to); | |
2ed21dae | 859 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
860 | } |
861 | ||
4102b533 | 862 | |
95d6976d VG |
863 | /********************************************************************** |
864 | * Explicit Cache flush request from user space via syscall | |
865 | * Needed for JITs which generate code on the fly | |
866 | */ | |
867 | SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) | |
868 | { | |
869 | /* TBD: optimize this */ | |
870 | flush_cache_all(); | |
871 | return 0; | |
872 | } | |
8ea2ddff VG |
873 | |
874 | void arc_cache_init(void) | |
875 | { | |
876 | unsigned int __maybe_unused cpu = smp_processor_id(); | |
877 | char str[256]; | |
878 | ||
879 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | |
880 | ||
881 | if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { | |
882 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | |
883 | ||
884 | if (!ic->ver) | |
885 | panic("cache support enabled but non-existent cache\n"); | |
886 | ||
887 | if (ic->line_len != L1_CACHE_BYTES) | |
888 | panic("ICache line [%d] != kernel Config [%d]", | |
889 | ic->line_len, L1_CACHE_BYTES); | |
890 | ||
891 | if (ic->ver != CONFIG_ARC_MMU_VER) | |
892 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", | |
893 | ic->ver, CONFIG_ARC_MMU_VER); | |
bcc4d65a VG |
894 | |
895 | /* | |
896 | * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG | |
897 | * pair to provide vaddr/paddr respectively, just as in MMU v3 | |
898 | */ | |
899 | if (is_isa_arcv2() && ic->alias) | |
900 | _cache_line_loop_ic_fn = __cache_line_loop_v3; | |
901 | else | |
902 | _cache_line_loop_ic_fn = __cache_line_loop; | |
8ea2ddff VG |
903 | } |
904 | ||
905 | if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { | |
906 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
8ea2ddff VG |
907 | |
908 | if (!dc->ver) | |
909 | panic("cache support enabled but non-existent cache\n"); | |
910 | ||
911 | if (dc->line_len != L1_CACHE_BYTES) | |
912 | panic("DCache line [%d] != kernel Config [%d]", | |
913 | dc->line_len, L1_CACHE_BYTES); | |
914 | ||
d1f317d8 VG |
915 | /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ |
916 | if (is_isa_arcompact()) { | |
917 | int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); | |
8ea2ddff | 918 | |
d1f317d8 VG |
919 | if (dc->alias && !handled) |
920 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
921 | else if (!dc->alias && handled) | |
922 | panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
923 | } | |
8ea2ddff | 924 | } |
f2b0b25a | 925 | |
79335a2c VG |
926 | if (is_isa_arcv2() && l2_line_sz && !slc_enable) { |
927 | ||
928 | /* IM set : flush before invalidate */ | |
929 | write_aux_reg(ARC_REG_SLC_CTRL, | |
930 | read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM); | |
931 | ||
932 | write_aux_reg(ARC_REG_SLC_INVALIDATE, 1); | |
933 | ||
934 | /* Important to wait for flush to complete */ | |
935 | while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); | |
936 | write_aux_reg(ARC_REG_SLC_CTRL, | |
937 | read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE); | |
938 | } | |
939 | ||
f2b0b25a AB |
940 | if (is_isa_arcv2() && ioc_exists) { |
941 | /* IO coherency base - 0x8z */ | |
942 | write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000); | |
943 | /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ | |
944 | write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11); | |
945 | /* Enable partial writes */ | |
946 | write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1); | |
947 | /* Enable IO coherency */ | |
948 | write_aux_reg(ARC_REG_IO_COH_ENABLE, 1); | |
949 | ||
950 | __dma_cache_wback_inv = __dma_cache_wback_inv_ioc; | |
951 | __dma_cache_inv = __dma_cache_inv_ioc; | |
952 | __dma_cache_wback = __dma_cache_wback_ioc; | |
79335a2c | 953 | } else if (is_isa_arcv2() && l2_line_sz && slc_enable) { |
f2b0b25a AB |
954 | __dma_cache_wback_inv = __dma_cache_wback_inv_slc; |
955 | __dma_cache_inv = __dma_cache_inv_slc; | |
956 | __dma_cache_wback = __dma_cache_wback_slc; | |
957 | } else { | |
958 | __dma_cache_wback_inv = __dma_cache_wback_inv_l1; | |
959 | __dma_cache_inv = __dma_cache_inv_l1; | |
960 | __dma_cache_wback = __dma_cache_wback_l1; | |
961 | } | |
8ea2ddff | 962 | } |