Commit | Line | Data |
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c121c506 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/seq_file.h> | |
10 | #include <linux/fs.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/root_dev.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/cpu.h> | |
d7f8a085 | 16 | #include <linux/clk-provider.h> |
999159a5 | 17 | #include <linux/of_fdt.h> |
d7f8a085 | 18 | #include <linux/of_platform.h> |
1ec9db10 | 19 | #include <linux/cache.h> |
999159a5 | 20 | #include <asm/sections.h> |
c121c506 VG |
21 | #include <asm/arcregs.h> |
22 | #include <asm/tlb.h> | |
c121c506 VG |
23 | #include <asm/setup.h> |
24 | #include <asm/page.h> | |
25 | #include <asm/irq.h> | |
854a0d95 | 26 | #include <asm/unwind.h> |
af617428 | 27 | #include <asm/clk.h> |
03a6d28c | 28 | #include <asm/mach_desc.h> |
619f3018 | 29 | #include <asm/smp.h> |
c121c506 VG |
30 | |
31 | #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) | |
32 | ||
4255b07f VG |
33 | unsigned int intr_to_DE_cnt; |
34 | ||
59ed9413 VG |
35 | /* Part of U-boot ABI: see head.S */ |
36 | int __initdata uboot_tag; | |
37 | char __initdata *uboot_arg; | |
38 | ||
880beb88 | 39 | const struct machine_desc *machine_desc; |
c121c506 VG |
40 | |
41 | struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ | |
42 | ||
43 | struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; | |
44 | ||
a150b085 VG |
45 | static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) |
46 | { | |
47 | if (is_isa_arcompact()) { | |
48 | struct bcr_iccm_arcompact iccm; | |
49 | struct bcr_dccm_arcompact dccm; | |
50 | ||
51 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
52 | if (iccm.ver) { | |
53 | cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ | |
54 | cpu->iccm.base_addr = iccm.base << 16; | |
55 | } | |
56 | ||
57 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
58 | if (dccm.ver) { | |
59 | unsigned long base; | |
60 | cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ | |
61 | ||
62 | base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); | |
63 | cpu->dccm.base_addr = base & ~0xF; | |
64 | } | |
65 | } else { | |
66 | struct bcr_iccm_arcv2 iccm; | |
67 | struct bcr_dccm_arcv2 dccm; | |
68 | unsigned long region; | |
69 | ||
70 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
71 | if (iccm.ver) { | |
72 | cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ | |
73 | if (iccm.sz00 == 0xF && iccm.sz01 > 0) | |
74 | cpu->iccm.sz <<= iccm.sz01; | |
75 | ||
76 | region = read_aux_reg(ARC_REG_AUX_ICCM); | |
77 | cpu->iccm.base_addr = region & 0xF0000000; | |
78 | } | |
79 | ||
80 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
81 | if (dccm.ver) { | |
82 | cpu->dccm.sz = 256 << dccm.sz0; | |
83 | if (dccm.sz0 == 0xF && dccm.sz1 > 0) | |
84 | cpu->dccm.sz <<= dccm.sz1; | |
85 | ||
86 | region = read_aux_reg(ARC_REG_AUX_DCCM); | |
87 | cpu->dccm.base_addr = region & 0xF0000000; | |
88 | } | |
89 | } | |
90 | } | |
91 | ||
8e457d6a | 92 | static void read_arc_build_cfg_regs(void) |
c121c506 | 93 | { |
b89bd1f4 | 94 | struct bcr_timer timer; |
56372082 | 95 | struct bcr_generic bcr; |
af617428 VG |
96 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
97 | FIX_PTR(cpu); | |
98 | ||
99 | READ_BCR(AUX_IDENTITY, cpu->core); | |
56372082 | 100 | READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); |
af617428 | 101 | |
b89bd1f4 VG |
102 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
103 | cpu->extn.timer0 = timer.t0; | |
104 | cpu->extn.timer1 = timer.t1; | |
105 | cpu->extn.rtc = timer.rtc; | |
106 | ||
af617428 | 107 | cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); |
af617428 | 108 | |
56372082 | 109 | READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); |
af617428 | 110 | |
56372082 VG |
111 | cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ |
112 | cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ | |
113 | cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ | |
114 | cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; | |
115 | cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ | |
af617428 VG |
116 | READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); |
117 | ||
a150b085 VG |
118 | /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ |
119 | read_decode_ccm_bcr(cpu); | |
120 | ||
c121c506 VG |
121 | read_decode_mmu_bcr(); |
122 | read_decode_cache_bcr(); | |
af617428 | 123 | |
1f6ccfff | 124 | if (is_isa_arcompact()) { |
56372082 VG |
125 | struct bcr_fp_arcompact sp, dp; |
126 | struct bcr_bpu_arcompact bpu; | |
127 | ||
128 | READ_BCR(ARC_REG_FP_BCR, sp); | |
129 | READ_BCR(ARC_REG_DPFP_BCR, dp); | |
130 | cpu->extn.fpu_sp = sp.ver ? 1 : 0; | |
131 | cpu->extn.fpu_dp = dp.ver ? 1 : 0; | |
132 | ||
133 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
134 | cpu->bpu.ver = bpu.ver; | |
135 | cpu->bpu.full = bpu.fam ? 1 : 0; | |
136 | if (bpu.ent) { | |
137 | cpu->bpu.num_cache = 256 << (bpu.ent - 1); | |
138 | cpu->bpu.num_pred = 256 << (bpu.ent - 1); | |
139 | } | |
1f6ccfff VG |
140 | } else { |
141 | struct bcr_fp_arcv2 spdp; | |
142 | struct bcr_bpu_arcv2 bpu; | |
143 | ||
144 | READ_BCR(ARC_REG_FP_V2_BCR, spdp); | |
145 | cpu->extn.fpu_sp = spdp.sp ? 1 : 0; | |
146 | cpu->extn.fpu_dp = spdp.dp ? 1 : 0; | |
147 | ||
148 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
149 | cpu->bpu.ver = bpu.ver; | |
150 | cpu->bpu.full = bpu.ft; | |
151 | cpu->bpu.num_cache = 256 << bpu.bce; | |
152 | cpu->bpu.num_pred = 2048 << bpu.pte; | |
56372082 VG |
153 | } |
154 | ||
155 | READ_BCR(ARC_REG_AP_BCR, bcr); | |
156 | cpu->extn.ap = bcr.ver ? 1 : 0; | |
157 | ||
158 | READ_BCR(ARC_REG_SMART_BCR, bcr); | |
159 | cpu->extn.smart = bcr.ver ? 1 : 0; | |
160 | ||
a44ec8bd VG |
161 | READ_BCR(ARC_REG_RTT_BCR, bcr); |
162 | cpu->extn.rtt = bcr.ver ? 1 : 0; | |
163 | ||
164 | cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; | |
af617428 VG |
165 | } |
166 | ||
167 | static const struct cpuinfo_data arc_cpu_tbl[] = { | |
624b71ee | 168 | #ifdef CONFIG_ISA_ARCOMPACT |
af617428 VG |
169 | { {0x20, "ARC 600" }, 0x2F}, |
170 | { {0x30, "ARC 700" }, 0x33}, | |
171 | { {0x34, "ARC 700 R4.10"}, 0x34}, | |
56372082 | 172 | { {0x35, "ARC 700 R4.11"}, 0x35}, |
624b71ee VG |
173 | #else |
174 | { {0x50, "ARC HS38 R2.0"}, 0x51}, | |
175 | { {0x52, "ARC HS38 R2.1"}, 0x52}, | |
176 | #endif | |
af617428 VG |
177 | { {0x00, NULL } } |
178 | }; | |
179 | ||
56372082 | 180 | |
8e457d6a | 181 | static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 | 182 | { |
af617428 VG |
183 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; |
184 | struct bcr_identity *core = &cpu->core; | |
185 | const struct cpuinfo_data *tbl; | |
56372082 VG |
186 | char *isa_nm; |
187 | int i, be, atomic; | |
188 | int n = 0; | |
189 | ||
af617428 VG |
190 | FIX_PTR(cpu); |
191 | ||
1f6ccfff | 192 | if (is_isa_arcompact()) { |
56372082 VG |
193 | isa_nm = "ARCompact"; |
194 | be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); | |
195 | ||
196 | atomic = cpu->isa.atomic1; | |
197 | if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ | |
198 | atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); | |
1f6ccfff VG |
199 | } else { |
200 | isa_nm = "ARCv2"; | |
201 | be = cpu->isa.be; | |
202 | atomic = cpu->isa.atomic; | |
56372082 VG |
203 | } |
204 | ||
af617428 | 205 | n += scnprintf(buf + n, len - n, |
56372082 VG |
206 | "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", |
207 | core->family, core->cpu_id, core->chip_id); | |
af617428 VG |
208 | |
209 | for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { | |
210 | if ((core->family >= tbl->info.id) && | |
211 | (core->family <= tbl->up_range)) { | |
212 | n += scnprintf(buf + n, len - n, | |
56372082 VG |
213 | "processor [%d]\t: %s (%s ISA) %s\n", |
214 | cpu_id, tbl->info.str, isa_nm, | |
215 | IS_AVAIL1(be, "[Big-Endian]")); | |
af617428 VG |
216 | break; |
217 | } | |
218 | } | |
219 | ||
220 | if (tbl->info.id == 0) | |
221 | n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n"); | |
222 | ||
223 | n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n", | |
224 | (unsigned int)(arc_get_core_freq() / 1000000), | |
225 | (unsigned int)(arc_get_core_freq() / 10000) % 100); | |
226 | ||
aa93e8ef | 227 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", |
b89bd1f4 VG |
228 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), |
229 | IS_AVAIL1(cpu->extn.timer1, "Timer1 "), | |
230 | IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", | |
aa93e8ef | 231 | CONFIG_ARC_HAS_RTC)); |
af617428 | 232 | |
1f6ccfff VG |
233 | n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", |
234 | IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC), | |
235 | IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), | |
236 | IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); | |
af617428 | 237 | |
56372082 VG |
238 | if (i) |
239 | n += scnprintf(buf + n, len - n, "\n\t\t: "); | |
af617428 | 240 | |
1f6ccfff VG |
241 | if (cpu->extn_mpy.ver) { |
242 | if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ | |
243 | n += scnprintf(buf + n, len - n, "mpy "); | |
244 | } else { | |
245 | int opt = 2; /* stock MPY/MPYH */ | |
246 | ||
247 | if (cpu->extn_mpy.dsp) /* OPT 7-9 */ | |
248 | opt = cpu->extn_mpy.dsp + 6; | |
249 | ||
250 | n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); | |
251 | } | |
1f6ccfff VG |
252 | } |
253 | ||
56372082 | 254 | n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", |
1f6ccfff | 255 | IS_AVAIL1(cpu->isa.div_rem, "div_rem "), |
56372082 VG |
256 | IS_AVAIL1(cpu->extn.norm, "norm "), |
257 | IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), | |
258 | IS_AVAIL1(cpu->extn.swap, "swap "), | |
259 | IS_AVAIL1(cpu->extn.minmax, "minmax "), | |
260 | IS_AVAIL1(cpu->extn.crc, "crc "), | |
261 | IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); | |
af617428 | 262 | |
56372082 VG |
263 | if (cpu->bpu.ver) |
264 | n += scnprintf(buf + n, len - n, | |
265 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", | |
266 | IS_AVAIL1(cpu->bpu.full, "full"), | |
267 | IS_AVAIL1(!cpu->bpu.full, "partial"), | |
268 | cpu->bpu.num_cache, cpu->bpu.num_pred); | |
af617428 | 269 | |
56372082 VG |
270 | return buf; |
271 | } | |
af617428 | 272 | |
8e457d6a | 273 | static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 VG |
274 | { |
275 | int n = 0; | |
276 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | |
277 | ||
278 | FIX_PTR(cpu); | |
af617428 VG |
279 | |
280 | n += scnprintf(buf + n, len - n, | |
deaf7565 VG |
281 | "Vector Table\t: %#x\nUncached Base\t: %#lx\n", |
282 | cpu->vec_base, perip_base); | |
56372082 VG |
283 | |
284 | if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) | |
285 | n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", | |
286 | IS_AVAIL1(cpu->extn.fpu_sp, "SP "), | |
287 | IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); | |
288 | ||
289 | if (cpu->extn.debug) | |
290 | n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", | |
291 | IS_AVAIL1(cpu->extn.ap, "ActionPoint "), | |
292 | IS_AVAIL1(cpu->extn.smart, "smaRT "), | |
293 | IS_AVAIL1(cpu->extn.rtt, "RTT ")); | |
294 | ||
295 | if (cpu->dccm.sz || cpu->iccm.sz) | |
296 | n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", | |
297 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | |
af617428 VG |
298 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); |
299 | ||
af617428 | 300 | n += scnprintf(buf + n, len - n, |
8ff14bbc | 301 | "OS ABI [v3]\t: no-legacy-syscalls\n"); |
af617428 VG |
302 | |
303 | return buf; | |
304 | } | |
305 | ||
c4b9856b | 306 | static void arc_chk_core_config(void) |
8b5850f8 | 307 | { |
8b5850f8 | 308 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
c4b9856b | 309 | int fpu_enabled; |
8b5850f8 | 310 | |
b89bd1f4 | 311 | if (!cpu->extn.timer0) |
56372082 VG |
312 | panic("Timer0 is not present!\n"); |
313 | ||
b89bd1f4 | 314 | if (!cpu->extn.timer1) |
56372082 VG |
315 | panic("Timer1 is not present!\n"); |
316 | ||
b89bd1f4 | 317 | if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc) |
aa93e8ef VG |
318 | panic("RTC is not present\n"); |
319 | ||
8b5850f8 VG |
320 | #ifdef CONFIG_ARC_HAS_DCCM |
321 | /* | |
322 | * DCCM can be arbit placed in hardware. | |
323 | * Make sure it's placement/sz matches what Linux is built with | |
324 | */ | |
325 | if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) | |
326 | panic("Linux built with incorrect DCCM Base address\n"); | |
327 | ||
328 | if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) | |
329 | panic("Linux built with incorrect DCCM Size\n"); | |
330 | #endif | |
331 | ||
332 | #ifdef CONFIG_ARC_HAS_ICCM | |
333 | if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) | |
334 | panic("Linux built with incorrect ICCM Size\n"); | |
335 | #endif | |
8b5850f8 | 336 | |
c4b9856b VG |
337 | /* |
338 | * FP hardware/software config sanity | |
339 | * -If hardware contains DPFP, kernel needs to save/restore FPU state | |
340 | * -If not, it will crash trying to save/restore the non-existant regs | |
341 | * | |
342 | * (only DPDP checked since SP has no arch visible regs) | |
343 | */ | |
344 | fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); | |
af617428 | 345 | |
56372082 | 346 | if (cpu->extn.fpu_dp && !fpu_enabled) |
c4b9856b | 347 | pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n"); |
56372082 | 348 | else if (!cpu->extn.fpu_dp && fpu_enabled) |
c4b9856b | 349 | panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n"); |
c121c506 VG |
350 | } |
351 | ||
352 | /* | |
353 | * Initialize and setup the processor core | |
354 | * This is called by all the CPUs thus should not do special case stuff | |
355 | * such as only for boot CPU etc | |
356 | */ | |
357 | ||
ce759956 | 358 | void setup_processor(void) |
c121c506 | 359 | { |
af617428 VG |
360 | char str[512]; |
361 | int cpu_id = smp_processor_id(); | |
362 | ||
c121c506 VG |
363 | read_arc_build_cfg_regs(); |
364 | arc_init_IRQ(); | |
af617428 VG |
365 | |
366 | printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); | |
367 | ||
c121c506 VG |
368 | arc_mmu_init(); |
369 | arc_cache_init(); | |
af617428 VG |
370 | |
371 | printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); | |
af617428 | 372 | printk(arc_platform_smp_cpuinfo()); |
af617428 | 373 | |
c4b9856b | 374 | arc_chk_core_config(); |
c121c506 VG |
375 | } |
376 | ||
59ed9413 VG |
377 | static inline int is_kernel(unsigned long addr) |
378 | { | |
379 | if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) | |
380 | return 1; | |
381 | return 0; | |
382 | } | |
383 | ||
c121c506 VG |
384 | void __init setup_arch(char **cmdline_p) |
385 | { | |
036b2c56 | 386 | #ifdef CONFIG_ARC_UBOOT_SUPPORT |
e57d339a VG |
387 | /* make sure that uboot passed pointer to cmdline/dtb is valid */ |
388 | if (uboot_tag && is_kernel((unsigned long)uboot_arg)) | |
389 | panic("Invalid uboot arg\n"); | |
390 | ||
391 | /* See if u-boot passed an external Device Tree blob */ | |
392 | machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */ | |
036b2c56 VG |
393 | if (!machine_desc) |
394 | #endif | |
395 | { | |
e57d339a | 396 | /* No, so try the embedded one */ |
59ed9413 VG |
397 | machine_desc = setup_machine_fdt(__dtb_start); |
398 | if (!machine_desc) | |
399 | panic("Embedded DT invalid\n"); | |
400 | ||
401 | /* | |
e57d339a VG |
402 | * If we are here, it is established that @uboot_arg didn't |
403 | * point to DT blob. Instead if u-boot says it is cmdline, | |
404 | * Appent to embedded DT cmdline. | |
59ed9413 VG |
405 | * setup_machine_fdt() would have populated @boot_command_line |
406 | */ | |
407 | if (uboot_tag == 1) { | |
59ed9413 VG |
408 | /* Ensure a whitespace between the 2 cmdlines */ |
409 | strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); | |
410 | strlcat(boot_command_line, uboot_arg, | |
411 | COMMAND_LINE_SIZE); | |
412 | } | |
e57d339a | 413 | } |
c121c506 VG |
414 | |
415 | /* Save unparsed command line copy for /proc/cmdline */ | |
9593a933 | 416 | *cmdline_p = boot_command_line; |
999159a5 | 417 | |
c121c506 VG |
418 | /* To force early parsing of things like mem=xxx */ |
419 | parse_early_param(); | |
420 | ||
421 | /* Platform/board specific: e.g. early console registration */ | |
03a6d28c VG |
422 | if (machine_desc->init_early) |
423 | machine_desc->init_early(); | |
c121c506 | 424 | |
41195d23 | 425 | smp_init_cpus(); |
e55af4da VG |
426 | |
427 | setup_processor(); | |
c121c506 VG |
428 | setup_arch_memory(); |
429 | ||
eab6a08c | 430 | /* copy flat DT out of .init and then unflatten it */ |
1efc959e | 431 | unflatten_and_copy_device_tree(); |
999159a5 | 432 | |
c121c506 VG |
433 | /* Can be issue if someone passes cmd line arg "ro" |
434 | * But that is unlikely so keeping it as it is | |
435 | */ | |
436 | root_mountflags &= ~MS_RDONLY; | |
437 | ||
c121c506 VG |
438 | #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) |
439 | conswitchp = &dummy_con; | |
440 | #endif | |
441 | ||
854a0d95 | 442 | arc_unwind_init(); |
c121c506 VG |
443 | } |
444 | ||
03a6d28c VG |
445 | static int __init customize_machine(void) |
446 | { | |
d7f8a085 VG |
447 | of_clk_init(NULL); |
448 | /* | |
449 | * Traverses flattened DeviceTree - registering platform devices | |
450 | * (if any) complete with their resources | |
451 | */ | |
26cf9cc5 | 452 | of_platform_default_populate(NULL, NULL, NULL); |
d7f8a085 | 453 | |
03a6d28c VG |
454 | if (machine_desc->init_machine) |
455 | machine_desc->init_machine(); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | arch_initcall(customize_machine); | |
460 | ||
461 | static int __init init_late_machine(void) | |
462 | { | |
463 | if (machine_desc->init_late) | |
464 | machine_desc->init_late(); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | late_initcall(init_late_machine); | |
c121c506 VG |
469 | /* |
470 | * Get CPU information for use by the procfs. | |
471 | */ | |
472 | ||
473 | #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) | |
474 | #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) | |
475 | ||
476 | static int show_cpuinfo(struct seq_file *m, void *v) | |
477 | { | |
478 | char *str; | |
479 | int cpu_id = ptr_to_cpu(v); | |
480 | ||
4c86231c VG |
481 | if (!cpu_online(cpu_id)) { |
482 | seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); | |
483 | goto done; | |
484 | } | |
485 | ||
c121c506 VG |
486 | str = (char *)__get_free_page(GFP_TEMPORARY); |
487 | if (!str) | |
488 | goto done; | |
489 | ||
af617428 | 490 | seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
c121c506 | 491 | |
56372082 | 492 | seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", |
c121c506 VG |
493 | loops_per_jiffy / (500000 / HZ), |
494 | (loops_per_jiffy / (5000 / HZ)) % 100); | |
495 | ||
af617428 | 496 | seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 497 | seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 498 | seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 499 | seq_printf(m, arc_platform_smp_cpuinfo()); |
af617428 | 500 | |
c121c506 VG |
501 | free_page((unsigned long)str); |
502 | done: | |
4c86231c | 503 | seq_printf(m, "\n"); |
c121c506 VG |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static void *c_start(struct seq_file *m, loff_t *pos) | |
509 | { | |
510 | /* | |
511 | * Callback returns cpu-id to iterator for show routine, NULL to stop. | |
512 | * However since NULL is also a valid cpu-id (0), we use a round-about | |
513 | * way to pass it w/o having to kmalloc/free a 2 byte string. | |
514 | * Encode cpu-id as 0xFFcccc, which is decoded by show routine. | |
515 | */ | |
516 | return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL; | |
517 | } | |
518 | ||
519 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
520 | { | |
521 | ++*pos; | |
522 | return c_start(m, pos); | |
523 | } | |
524 | ||
525 | static void c_stop(struct seq_file *m, void *v) | |
526 | { | |
527 | } | |
528 | ||
529 | const struct seq_operations cpuinfo_op = { | |
530 | .start = c_start, | |
531 | .next = c_next, | |
532 | .stop = c_stop, | |
533 | .show = show_cpuinfo | |
534 | }; | |
535 | ||
536 | static DEFINE_PER_CPU(struct cpu, cpu_topology); | |
537 | ||
538 | static int __init topology_init(void) | |
539 | { | |
540 | int cpu; | |
541 | ||
542 | for_each_present_cpu(cpu) | |
543 | register_cpu(&per_cpu(cpu_topology, cpu), cpu); | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | subsys_initcall(topology_init); |