Commit | Line | Data |
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c121c506 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/seq_file.h> | |
10 | #include <linux/fs.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/root_dev.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/cpu.h> | |
999159a5 | 16 | #include <linux/of_fdt.h> |
1ce0b585 | 17 | #include <linux/of.h> |
1ec9db10 | 18 | #include <linux/cache.h> |
999159a5 | 19 | #include <asm/sections.h> |
c121c506 VG |
20 | #include <asm/arcregs.h> |
21 | #include <asm/tlb.h> | |
c121c506 VG |
22 | #include <asm/setup.h> |
23 | #include <asm/page.h> | |
24 | #include <asm/irq.h> | |
854a0d95 | 25 | #include <asm/unwind.h> |
03a6d28c | 26 | #include <asm/mach_desc.h> |
619f3018 | 27 | #include <asm/smp.h> |
c121c506 VG |
28 | |
29 | #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) | |
30 | ||
4255b07f VG |
31 | unsigned int intr_to_DE_cnt; |
32 | ||
59ed9413 VG |
33 | /* Part of U-boot ABI: see head.S */ |
34 | int __initdata uboot_tag; | |
35 | char __initdata *uboot_arg; | |
36 | ||
880beb88 | 37 | const struct machine_desc *machine_desc; |
c121c506 VG |
38 | |
39 | struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ | |
40 | ||
41 | struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; | |
42 | ||
73e284d2 VG |
43 | static const struct cpuinfo_data arc_cpu_tbl[] = { |
44 | #ifdef CONFIG_ISA_ARCOMPACT | |
45 | { {0x20, "ARC 600" }, 0x2F}, | |
46 | { {0x30, "ARC 700" }, 0x33}, | |
47 | { {0x34, "ARC 700 R4.10"}, 0x34}, | |
48 | { {0x35, "ARC 700 R4.11"}, 0x35}, | |
49 | #else | |
50 | { {0x50, "ARC HS38 R2.0"}, 0x51}, | |
51 | { {0x52, "ARC HS38 R2.1"}, 0x52}, | |
52 | { {0x53, "ARC HS38 R3.0"}, 0x53}, | |
53 | #endif | |
54 | { {0x00, NULL } } | |
55 | }; | |
56 | ||
a150b085 VG |
57 | static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) |
58 | { | |
59 | if (is_isa_arcompact()) { | |
60 | struct bcr_iccm_arcompact iccm; | |
61 | struct bcr_dccm_arcompact dccm; | |
62 | ||
63 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
64 | if (iccm.ver) { | |
65 | cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ | |
66 | cpu->iccm.base_addr = iccm.base << 16; | |
67 | } | |
68 | ||
69 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
70 | if (dccm.ver) { | |
71 | unsigned long base; | |
72 | cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ | |
73 | ||
74 | base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); | |
75 | cpu->dccm.base_addr = base & ~0xF; | |
76 | } | |
77 | } else { | |
78 | struct bcr_iccm_arcv2 iccm; | |
79 | struct bcr_dccm_arcv2 dccm; | |
80 | unsigned long region; | |
81 | ||
82 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
83 | if (iccm.ver) { | |
84 | cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ | |
85 | if (iccm.sz00 == 0xF && iccm.sz01 > 0) | |
86 | cpu->iccm.sz <<= iccm.sz01; | |
87 | ||
88 | region = read_aux_reg(ARC_REG_AUX_ICCM); | |
89 | cpu->iccm.base_addr = region & 0xF0000000; | |
90 | } | |
91 | ||
92 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
93 | if (dccm.ver) { | |
94 | cpu->dccm.sz = 256 << dccm.sz0; | |
95 | if (dccm.sz0 == 0xF && dccm.sz1 > 0) | |
96 | cpu->dccm.sz <<= dccm.sz1; | |
97 | ||
98 | region = read_aux_reg(ARC_REG_AUX_DCCM); | |
99 | cpu->dccm.base_addr = region & 0xF0000000; | |
100 | } | |
101 | } | |
102 | } | |
103 | ||
8e457d6a | 104 | static void read_arc_build_cfg_regs(void) |
c121c506 | 105 | { |
b89bd1f4 | 106 | struct bcr_timer timer; |
56372082 | 107 | struct bcr_generic bcr; |
af617428 | 108 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
73e284d2 VG |
109 | const struct cpuinfo_data *tbl; |
110 | ||
af617428 VG |
111 | FIX_PTR(cpu); |
112 | ||
113 | READ_BCR(AUX_IDENTITY, cpu->core); | |
56372082 | 114 | READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); |
af617428 | 115 | |
73e284d2 VG |
116 | for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { |
117 | if ((cpu->core.family >= tbl->info.id) && | |
118 | (cpu->core.family <= tbl->up_range)) { | |
119 | cpu->details = tbl->info.str; | |
120 | break; | |
121 | } | |
122 | } | |
123 | ||
124 | if (tbl->info.id == 0) | |
125 | cpu->details = "UNKNOWN"; | |
126 | ||
b89bd1f4 VG |
127 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
128 | cpu->extn.timer0 = timer.t0; | |
129 | cpu->extn.timer1 = timer.t1; | |
130 | cpu->extn.rtc = timer.rtc; | |
131 | ||
af617428 | 132 | cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); |
af617428 | 133 | |
56372082 | 134 | READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); |
af617428 | 135 | |
56372082 VG |
136 | cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ |
137 | cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ | |
138 | cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ | |
139 | cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; | |
140 | cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ | |
af617428 VG |
141 | READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); |
142 | ||
a150b085 VG |
143 | /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ |
144 | read_decode_ccm_bcr(cpu); | |
145 | ||
c121c506 VG |
146 | read_decode_mmu_bcr(); |
147 | read_decode_cache_bcr(); | |
af617428 | 148 | |
1f6ccfff | 149 | if (is_isa_arcompact()) { |
56372082 VG |
150 | struct bcr_fp_arcompact sp, dp; |
151 | struct bcr_bpu_arcompact bpu; | |
152 | ||
153 | READ_BCR(ARC_REG_FP_BCR, sp); | |
154 | READ_BCR(ARC_REG_DPFP_BCR, dp); | |
155 | cpu->extn.fpu_sp = sp.ver ? 1 : 0; | |
156 | cpu->extn.fpu_dp = dp.ver ? 1 : 0; | |
157 | ||
158 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
159 | cpu->bpu.ver = bpu.ver; | |
160 | cpu->bpu.full = bpu.fam ? 1 : 0; | |
161 | if (bpu.ent) { | |
162 | cpu->bpu.num_cache = 256 << (bpu.ent - 1); | |
163 | cpu->bpu.num_pred = 256 << (bpu.ent - 1); | |
164 | } | |
1f6ccfff VG |
165 | } else { |
166 | struct bcr_fp_arcv2 spdp; | |
167 | struct bcr_bpu_arcv2 bpu; | |
168 | ||
169 | READ_BCR(ARC_REG_FP_V2_BCR, spdp); | |
170 | cpu->extn.fpu_sp = spdp.sp ? 1 : 0; | |
171 | cpu->extn.fpu_dp = spdp.dp ? 1 : 0; | |
172 | ||
173 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
174 | cpu->bpu.ver = bpu.ver; | |
175 | cpu->bpu.full = bpu.ft; | |
176 | cpu->bpu.num_cache = 256 << bpu.bce; | |
177 | cpu->bpu.num_pred = 2048 << bpu.pte; | |
56372082 VG |
178 | } |
179 | ||
180 | READ_BCR(ARC_REG_AP_BCR, bcr); | |
181 | cpu->extn.ap = bcr.ver ? 1 : 0; | |
182 | ||
183 | READ_BCR(ARC_REG_SMART_BCR, bcr); | |
184 | cpu->extn.smart = bcr.ver ? 1 : 0; | |
185 | ||
a44ec8bd VG |
186 | READ_BCR(ARC_REG_RTT_BCR, bcr); |
187 | cpu->extn.rtt = bcr.ver ? 1 : 0; | |
188 | ||
189 | cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; | |
af617428 | 190 | |
73e284d2 VG |
191 | /* some hacks for lack of feature BCR info in old ARC700 cores */ |
192 | if (is_isa_arcompact()) { | |
193 | if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ | |
194 | cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); | |
195 | else | |
196 | cpu->isa.atomic = cpu->isa.atomic1; | |
af617428 | 197 | |
73e284d2 VG |
198 | cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); |
199 | } | |
200 | } | |
56372082 | 201 | |
8e457d6a | 202 | static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 | 203 | { |
af617428 VG |
204 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; |
205 | struct bcr_identity *core = &cpu->core; | |
73e284d2 | 206 | int i, n = 0; |
56372082 | 207 | |
af617428 VG |
208 | FIX_PTR(cpu); |
209 | ||
210 | n += scnprintf(buf + n, len - n, | |
56372082 VG |
211 | "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", |
212 | core->family, core->cpu_id, core->chip_id); | |
af617428 | 213 | |
73e284d2 VG |
214 | n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s\n", |
215 | cpu_id, cpu->details, | |
216 | is_isa_arcompact() ? "ARCompact" : "ARCv2", | |
217 | IS_AVAIL1(cpu->isa.be, "[Big-Endian]")); | |
af617428 | 218 | |
aa93e8ef | 219 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", |
b89bd1f4 VG |
220 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), |
221 | IS_AVAIL1(cpu->extn.timer1, "Timer1 "), | |
222 | IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", | |
aa93e8ef | 223 | CONFIG_ARC_HAS_RTC)); |
af617428 | 224 | |
1f6ccfff | 225 | n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", |
73e284d2 | 226 | IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), |
1f6ccfff VG |
227 | IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), |
228 | IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); | |
af617428 | 229 | |
56372082 VG |
230 | if (i) |
231 | n += scnprintf(buf + n, len - n, "\n\t\t: "); | |
af617428 | 232 | |
1f6ccfff VG |
233 | if (cpu->extn_mpy.ver) { |
234 | if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ | |
235 | n += scnprintf(buf + n, len - n, "mpy "); | |
236 | } else { | |
237 | int opt = 2; /* stock MPY/MPYH */ | |
238 | ||
239 | if (cpu->extn_mpy.dsp) /* OPT 7-9 */ | |
240 | opt = cpu->extn_mpy.dsp + 6; | |
241 | ||
242 | n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); | |
243 | } | |
1f6ccfff VG |
244 | } |
245 | ||
56372082 | 246 | n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", |
1f6ccfff | 247 | IS_AVAIL1(cpu->isa.div_rem, "div_rem "), |
56372082 VG |
248 | IS_AVAIL1(cpu->extn.norm, "norm "), |
249 | IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), | |
250 | IS_AVAIL1(cpu->extn.swap, "swap "), | |
251 | IS_AVAIL1(cpu->extn.minmax, "minmax "), | |
252 | IS_AVAIL1(cpu->extn.crc, "crc "), | |
253 | IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); | |
af617428 | 254 | |
56372082 VG |
255 | if (cpu->bpu.ver) |
256 | n += scnprintf(buf + n, len - n, | |
257 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", | |
258 | IS_AVAIL1(cpu->bpu.full, "full"), | |
259 | IS_AVAIL1(!cpu->bpu.full, "partial"), | |
260 | cpu->bpu.num_cache, cpu->bpu.num_pred); | |
af617428 | 261 | |
56372082 VG |
262 | return buf; |
263 | } | |
af617428 | 264 | |
8e457d6a | 265 | static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 VG |
266 | { |
267 | int n = 0; | |
268 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | |
269 | ||
270 | FIX_PTR(cpu); | |
af617428 | 271 | |
711c1f26 | 272 | n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); |
56372082 VG |
273 | |
274 | if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) | |
275 | n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", | |
276 | IS_AVAIL1(cpu->extn.fpu_sp, "SP "), | |
277 | IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); | |
278 | ||
279 | if (cpu->extn.debug) | |
280 | n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", | |
281 | IS_AVAIL1(cpu->extn.ap, "ActionPoint "), | |
282 | IS_AVAIL1(cpu->extn.smart, "smaRT "), | |
283 | IS_AVAIL1(cpu->extn.rtt, "RTT ")); | |
284 | ||
285 | if (cpu->dccm.sz || cpu->iccm.sz) | |
286 | n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", | |
287 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | |
af617428 VG |
288 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); |
289 | ||
840c054f VG |
290 | n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", |
291 | EF_ARC_OSABI_CURRENT >> 8, | |
292 | EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? | |
293 | "no-legacy-syscalls" : "64-bit data any register aligned"); | |
af617428 VG |
294 | |
295 | return buf; | |
296 | } | |
297 | ||
c4b9856b | 298 | static void arc_chk_core_config(void) |
8b5850f8 | 299 | { |
8b5850f8 | 300 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
c4b9856b | 301 | int fpu_enabled; |
8b5850f8 | 302 | |
b89bd1f4 | 303 | if (!cpu->extn.timer0) |
56372082 VG |
304 | panic("Timer0 is not present!\n"); |
305 | ||
b89bd1f4 | 306 | if (!cpu->extn.timer1) |
56372082 VG |
307 | panic("Timer1 is not present!\n"); |
308 | ||
8b5850f8 VG |
309 | #ifdef CONFIG_ARC_HAS_DCCM |
310 | /* | |
311 | * DCCM can be arbit placed in hardware. | |
312 | * Make sure it's placement/sz matches what Linux is built with | |
313 | */ | |
314 | if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) | |
315 | panic("Linux built with incorrect DCCM Base address\n"); | |
316 | ||
317 | if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) | |
318 | panic("Linux built with incorrect DCCM Size\n"); | |
319 | #endif | |
320 | ||
321 | #ifdef CONFIG_ARC_HAS_ICCM | |
322 | if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) | |
323 | panic("Linux built with incorrect ICCM Size\n"); | |
324 | #endif | |
8b5850f8 | 325 | |
c4b9856b VG |
326 | /* |
327 | * FP hardware/software config sanity | |
328 | * -If hardware contains DPFP, kernel needs to save/restore FPU state | |
329 | * -If not, it will crash trying to save/restore the non-existant regs | |
330 | * | |
331 | * (only DPDP checked since SP has no arch visible regs) | |
332 | */ | |
333 | fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); | |
af617428 | 334 | |
56372082 | 335 | if (cpu->extn.fpu_dp && !fpu_enabled) |
c4b9856b | 336 | pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n"); |
56372082 | 337 | else if (!cpu->extn.fpu_dp && fpu_enabled) |
c4b9856b | 338 | panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n"); |
c121c506 VG |
339 | } |
340 | ||
341 | /* | |
342 | * Initialize and setup the processor core | |
343 | * This is called by all the CPUs thus should not do special case stuff | |
344 | * such as only for boot CPU etc | |
345 | */ | |
346 | ||
ce759956 | 347 | void setup_processor(void) |
c121c506 | 348 | { |
af617428 VG |
349 | char str[512]; |
350 | int cpu_id = smp_processor_id(); | |
351 | ||
c121c506 VG |
352 | read_arc_build_cfg_regs(); |
353 | arc_init_IRQ(); | |
af617428 VG |
354 | |
355 | printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); | |
356 | ||
c121c506 VG |
357 | arc_mmu_init(); |
358 | arc_cache_init(); | |
af617428 VG |
359 | |
360 | printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); | |
af617428 | 361 | printk(arc_platform_smp_cpuinfo()); |
af617428 | 362 | |
c4b9856b | 363 | arc_chk_core_config(); |
c121c506 VG |
364 | } |
365 | ||
59ed9413 VG |
366 | static inline int is_kernel(unsigned long addr) |
367 | { | |
368 | if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) | |
369 | return 1; | |
370 | return 0; | |
371 | } | |
372 | ||
c121c506 VG |
373 | void __init setup_arch(char **cmdline_p) |
374 | { | |
036b2c56 | 375 | #ifdef CONFIG_ARC_UBOOT_SUPPORT |
e57d339a VG |
376 | /* make sure that uboot passed pointer to cmdline/dtb is valid */ |
377 | if (uboot_tag && is_kernel((unsigned long)uboot_arg)) | |
378 | panic("Invalid uboot arg\n"); | |
379 | ||
380 | /* See if u-boot passed an external Device Tree blob */ | |
381 | machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */ | |
036b2c56 VG |
382 | if (!machine_desc) |
383 | #endif | |
384 | { | |
e57d339a | 385 | /* No, so try the embedded one */ |
59ed9413 VG |
386 | machine_desc = setup_machine_fdt(__dtb_start); |
387 | if (!machine_desc) | |
388 | panic("Embedded DT invalid\n"); | |
389 | ||
390 | /* | |
e57d339a VG |
391 | * If we are here, it is established that @uboot_arg didn't |
392 | * point to DT blob. Instead if u-boot says it is cmdline, | |
2547476a | 393 | * append to embedded DT cmdline. |
59ed9413 VG |
394 | * setup_machine_fdt() would have populated @boot_command_line |
395 | */ | |
396 | if (uboot_tag == 1) { | |
59ed9413 VG |
397 | /* Ensure a whitespace between the 2 cmdlines */ |
398 | strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); | |
399 | strlcat(boot_command_line, uboot_arg, | |
400 | COMMAND_LINE_SIZE); | |
401 | } | |
e57d339a | 402 | } |
c121c506 VG |
403 | |
404 | /* Save unparsed command line copy for /proc/cmdline */ | |
9593a933 | 405 | *cmdline_p = boot_command_line; |
999159a5 | 406 | |
c121c506 VG |
407 | /* To force early parsing of things like mem=xxx */ |
408 | parse_early_param(); | |
409 | ||
410 | /* Platform/board specific: e.g. early console registration */ | |
03a6d28c VG |
411 | if (machine_desc->init_early) |
412 | machine_desc->init_early(); | |
c121c506 | 413 | |
41195d23 | 414 | smp_init_cpus(); |
e55af4da VG |
415 | |
416 | setup_processor(); | |
c121c506 VG |
417 | setup_arch_memory(); |
418 | ||
eab6a08c | 419 | /* copy flat DT out of .init and then unflatten it */ |
1efc959e | 420 | unflatten_and_copy_device_tree(); |
999159a5 | 421 | |
c121c506 VG |
422 | /* Can be issue if someone passes cmd line arg "ro" |
423 | * But that is unlikely so keeping it as it is | |
424 | */ | |
425 | root_mountflags &= ~MS_RDONLY; | |
426 | ||
c121c506 VG |
427 | #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) |
428 | conswitchp = &dummy_con; | |
429 | #endif | |
430 | ||
854a0d95 | 431 | arc_unwind_init(); |
c121c506 VG |
432 | } |
433 | ||
03a6d28c VG |
434 | static int __init customize_machine(void) |
435 | { | |
03a6d28c VG |
436 | if (machine_desc->init_machine) |
437 | machine_desc->init_machine(); | |
438 | ||
439 | return 0; | |
440 | } | |
441 | arch_initcall(customize_machine); | |
442 | ||
443 | static int __init init_late_machine(void) | |
444 | { | |
445 | if (machine_desc->init_late) | |
446 | machine_desc->init_late(); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | late_initcall(init_late_machine); | |
c121c506 VG |
451 | /* |
452 | * Get CPU information for use by the procfs. | |
453 | */ | |
454 | ||
455 | #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) | |
456 | #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) | |
457 | ||
458 | static int show_cpuinfo(struct seq_file *m, void *v) | |
459 | { | |
460 | char *str; | |
461 | int cpu_id = ptr_to_cpu(v); | |
20c7dbbd AB |
462 | struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk"); |
463 | u32 freq = 0; | |
c121c506 | 464 | |
4c86231c VG |
465 | if (!cpu_online(cpu_id)) { |
466 | seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); | |
467 | goto done; | |
468 | } | |
469 | ||
c121c506 VG |
470 | str = (char *)__get_free_page(GFP_TEMPORARY); |
471 | if (!str) | |
472 | goto done; | |
473 | ||
af617428 | 474 | seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
c121c506 | 475 | |
20c7dbbd AB |
476 | of_property_read_u32(core_clk, "clock-frequency", &freq); |
477 | if (freq) | |
478 | seq_printf(m, "CPU speed\t: %u.%02u Mhz\n", | |
479 | freq / 1000000, (freq / 10000) % 100); | |
480 | ||
56372082 | 481 | seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", |
c121c506 VG |
482 | loops_per_jiffy / (500000 / HZ), |
483 | (loops_per_jiffy / (5000 / HZ)) % 100); | |
484 | ||
af617428 | 485 | seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 486 | seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 487 | seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 488 | seq_printf(m, arc_platform_smp_cpuinfo()); |
af617428 | 489 | |
c121c506 VG |
490 | free_page((unsigned long)str); |
491 | done: | |
4c86231c | 492 | seq_printf(m, "\n"); |
c121c506 VG |
493 | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static void *c_start(struct seq_file *m, loff_t *pos) | |
498 | { | |
499 | /* | |
500 | * Callback returns cpu-id to iterator for show routine, NULL to stop. | |
501 | * However since NULL is also a valid cpu-id (0), we use a round-about | |
502 | * way to pass it w/o having to kmalloc/free a 2 byte string. | |
503 | * Encode cpu-id as 0xFFcccc, which is decoded by show routine. | |
504 | */ | |
3da43104 | 505 | return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; |
c121c506 VG |
506 | } |
507 | ||
508 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
509 | { | |
510 | ++*pos; | |
511 | return c_start(m, pos); | |
512 | } | |
513 | ||
514 | static void c_stop(struct seq_file *m, void *v) | |
515 | { | |
516 | } | |
517 | ||
518 | const struct seq_operations cpuinfo_op = { | |
519 | .start = c_start, | |
520 | .next = c_next, | |
521 | .stop = c_stop, | |
522 | .show = show_cpuinfo | |
523 | }; | |
524 | ||
525 | static DEFINE_PER_CPU(struct cpu, cpu_topology); | |
526 | ||
527 | static int __init topology_init(void) | |
528 | { | |
529 | int cpu; | |
530 | ||
531 | for_each_present_cpu(cpu) | |
532 | register_cpu(&per_cpu(cpu_topology, cpu), cpu); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | subsys_initcall(topology_init); |