[linux-2.6-block.git] / arch / arc / kernel / setup.c

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/seq_file.h>
#include <linux/fs.h>
#include <linux/delay.h>
#include <linux/root_dev.h>
#include <linux/console.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/of_fdt.h>
#include <linux/of.h>
#include <linux/cache.h>
#include <asm/sections.h>
#include <asm/arcregs.h>
#include <asm/tlb.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/unwind.h>
#include <asm/mach_desc.h>
#include <asm/smp.h>

#define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))

unsigned int intr_to_DE_cnt;

/* Part of U-boot ABI: see head.S */
int __initdata uboot_tag;
char __initdata *uboot_arg;

const struct machine_desc *machine_desc;

struct task_struct *_current_task[NR_CPUS];	/* For stack switching */

struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];

static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
{
	if (is_isa_arcompact()) {
		struct bcr_iccm_arcompact iccm;
		struct bcr_dccm_arcompact dccm;

		READ_BCR(ARC_REG_ICCM_BUILD, iccm);
		if (iccm.ver) {
			cpu->iccm.sz = 4096 << iccm.sz;	/* 8K to 512K */
			cpu->iccm.base_addr = iccm.base << 16;
		}

		READ_BCR(ARC_REG_DCCM_BUILD, dccm);
		if (dccm.ver) {
			unsigned long base;
			cpu->dccm.sz = 2048 << dccm.sz;	/* 2K to 256K */

			base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
			cpu->dccm.base_addr = base & ~0xF;
		}
	} else {
		struct bcr_iccm_arcv2 iccm;
		struct bcr_dccm_arcv2 dccm;
		unsigned long region;

		READ_BCR(ARC_REG_ICCM_BUILD, iccm);
		if (iccm.ver) {
			cpu->iccm.sz = 256 << iccm.sz00;	/* 512B to 16M */
			if (iccm.sz00 == 0xF && iccm.sz01 > 0)
				cpu->iccm.sz <<= iccm.sz01;

			region = read_aux_reg(ARC_REG_AUX_ICCM);
			cpu->iccm.base_addr = region & 0xF0000000;
		}

		READ_BCR(ARC_REG_DCCM_BUILD, dccm);
		if (dccm.ver) {
			cpu->dccm.sz = 256 << dccm.sz0;
			if (dccm.sz0 == 0xF && dccm.sz1 > 0)
				cpu->dccm.sz <<= dccm.sz1;

			region = read_aux_reg(ARC_REG_AUX_DCCM);
			cpu->dccm.base_addr = region & 0xF0000000;
		}
	}
}

static void read_arc_build_cfg_regs(void)
{
	struct bcr_timer timer;
	struct bcr_generic bcr;
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	FIX_PTR(cpu);

	READ_BCR(AUX_IDENTITY, cpu->core);
	READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);

	READ_BCR(ARC_REG_TIMERS_BCR, timer);
	cpu->extn.timer0 = timer.t0;
	cpu->extn.timer1 = timer.t1;
	cpu->extn.rtc = timer.rtc;

	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);

	READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);

	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0;        /* 1,3 */
	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);

	/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
	read_decode_ccm_bcr(cpu);

	read_decode_mmu_bcr();
	read_decode_cache_bcr();

	if (is_isa_arcompact()) {
		struct bcr_fp_arcompact sp, dp;
		struct bcr_bpu_arcompact bpu;

		READ_BCR(ARC_REG_FP_BCR, sp);
		READ_BCR(ARC_REG_DPFP_BCR, dp);
		cpu->extn.fpu_sp = sp.ver ? 1 : 0;
		cpu->extn.fpu_dp = dp.ver ? 1 : 0;

		READ_BCR(ARC_REG_BPU_BCR, bpu);
		cpu->bpu.ver = bpu.ver;
		cpu->bpu.full = bpu.fam ? 1 : 0;
		if (bpu.ent) {
			cpu->bpu.num_cache = 256 << (bpu.ent - 1);
			cpu->bpu.num_pred = 256 << (bpu.ent - 1);
		}
	} else {
		struct bcr_fp_arcv2 spdp;
		struct bcr_bpu_arcv2 bpu;

		READ_BCR(ARC_REG_FP_V2_BCR, spdp);
		cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
		cpu->extn.fpu_dp = spdp.dp ? 1 : 0;

		READ_BCR(ARC_REG_BPU_BCR, bpu);
		cpu->bpu.ver = bpu.ver;
		cpu->bpu.full = bpu.ft;
		cpu->bpu.num_cache = 256 << bpu.bce;
		cpu->bpu.num_pred = 2048 << bpu.pte;
	}

	READ_BCR(ARC_REG_AP_BCR, bcr);
	cpu->extn.ap = bcr.ver ? 1 : 0;

	READ_BCR(ARC_REG_SMART_BCR, bcr);
	cpu->extn.smart = bcr.ver ? 1 : 0;

	READ_BCR(ARC_REG_RTT_BCR, bcr);
	cpu->extn.rtt = bcr.ver ? 1 : 0;

	cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
}

static const struct cpuinfo_data arc_cpu_tbl[] = {
#ifdef CONFIG_ISA_ARCOMPACT
	{ {0x20, "ARC 600"      }, 0x2F},
	{ {0x30, "ARC 700"      }, 0x33},
	{ {0x34, "ARC 700 R4.10"}, 0x34},
	{ {0x35, "ARC 700 R4.11"}, 0x35},
#else
	{ {0x50, "ARC HS38 R2.0"}, 0x51},
	{ {0x52, "ARC HS38 R2.1"}, 0x52},
	{ {0x53, "ARC HS38 R3.0"}, 0x53},
#endif
	{ {0x00, NULL		} }
};


static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
{
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
	struct bcr_identity *core = &cpu->core;
	const struct cpuinfo_data *tbl;
	char *isa_nm;
	int i, be, atomic;
	int n = 0;

	FIX_PTR(cpu);

	if (is_isa_arcompact()) {
		isa_nm = "ARCompact";
		be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);

		atomic = cpu->isa.atomic1;
		if (!cpu->isa.ver)	/* ISA BCR absent, use Kconfig info */
			atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
	} else {
		isa_nm = "ARCv2";
		be = cpu->isa.be;
		atomic = cpu->isa.atomic;
	}

	n += scnprintf(buf + n, len - n,
		       "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
		       core->family, core->cpu_id, core->chip_id);

	for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
		if ((core->family >= tbl->info.id) &&
		    (core->family <= tbl->up_range)) {
			n += scnprintf(buf + n, len - n,
				       "processor [%d]\t: %s (%s ISA) %s\n",
				       cpu_id, tbl->info.str, isa_nm,
				       IS_AVAIL1(be, "[Big-Endian]"));
			break;
		}
	}

	if (tbl->info.id == 0)
		n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");

	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
		       IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
		       IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
		       IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
				 CONFIG_ARC_HAS_RTC));

	n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
			   IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
			   IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
			   IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));

	if (i)
		n += scnprintf(buf + n, len - n, "\n\t\t: ");

	if (cpu->extn_mpy.ver) {
		if (cpu->extn_mpy.ver <= 0x2) {	/* ARCompact */
			n += scnprintf(buf + n, len - n, "mpy ");
		} else {
			int opt = 2;	/* stock MPY/MPYH */

			if (cpu->extn_mpy.dsp)	/* OPT 7-9 */
				opt = cpu->extn_mpy.dsp + 6;

			n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
		}
	}

	n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
		       IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
		       IS_AVAIL1(cpu->extn.norm, "norm "),
		       IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
		       IS_AVAIL1(cpu->extn.swap, "swap "),
		       IS_AVAIL1(cpu->extn.minmax, "minmax "),
		       IS_AVAIL1(cpu->extn.crc, "crc "),
		       IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));

	if (cpu->bpu.ver)
		n += scnprintf(buf + n, len - n,
			      "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
			      IS_AVAIL1(cpu->bpu.full, "full"),
			      IS_AVAIL1(!cpu->bpu.full, "partial"),
			      cpu->bpu.num_cache, cpu->bpu.num_pred);

	return buf;
}

static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
{
	int n = 0;
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];

	FIX_PTR(cpu);

	n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);

	if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
		n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
			       IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
			       IS_AVAIL1(cpu->extn.fpu_dp, "DP "));

	if (cpu->extn.debug)
		n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
			       IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
			       IS_AVAIL1(cpu->extn.smart, "smaRT "),
			       IS_AVAIL1(cpu->extn.rtt, "RTT "));

	if (cpu->dccm.sz || cpu->iccm.sz)
		n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
			       cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
			       cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));

	n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
			EF_ARC_OSABI_CURRENT >> 8,
			EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
			"no-legacy-syscalls" : "64-bit data any register aligned");

	return buf;
}

static void arc_chk_core_config(void)
{
	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	int fpu_enabled;

	if (!cpu->extn.timer0)
		panic("Timer0 is not present!\n");

	if (!cpu->extn.timer1)
		panic("Timer1 is not present!\n");

#ifdef CONFIG_ARC_HAS_DCCM
	/*
	 * DCCM can be arbit placed in hardware.
	 * Make sure it's placement/sz matches what Linux is built with
	 */
	if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
		panic("Linux built with incorrect DCCM Base address\n");

	if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
		panic("Linux built with incorrect DCCM Size\n");
#endif

#ifdef CONFIG_ARC_HAS_ICCM
	if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
		panic("Linux built with incorrect ICCM Size\n");
#endif

	/*
	 * FP hardware/software config sanity
	 * -If hardware contains DPFP, kernel needs to save/restore FPU state
	 * -If not, it will crash trying to save/restore the non-existant regs
	 *
	 * (only DPDP checked since SP has no arch visible regs)
	 */
	fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);

	if (cpu->extn.fpu_dp && !fpu_enabled)
		pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
	else if (!cpu->extn.fpu_dp && fpu_enabled)
		panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
}

/*
 * Initialize and setup the processor core
 * This is called by all the CPUs thus should not do special case stuff
 *    such as only for boot CPU etc
 */

void setup_processor(void)
{
	char str[512];
	int cpu_id = smp_processor_id();

	read_arc_build_cfg_regs();
	arc_init_IRQ();

	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));

	arc_mmu_init();
	arc_cache_init();

	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
	printk(arc_platform_smp_cpuinfo());

	arc_chk_core_config();
}

static inline int is_kernel(unsigned long addr)
{
	if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
		return 1;
	return 0;
}

void __init setup_arch(char **cmdline_p)
{
#ifdef CONFIG_ARC_UBOOT_SUPPORT
	/* make sure that uboot passed pointer to cmdline/dtb is valid */
	if (uboot_tag && is_kernel((unsigned long)uboot_arg))
		panic("Invalid uboot arg\n");

	/* See if u-boot passed an external Device Tree blob */
	machine_desc = setup_machine_fdt(uboot_arg);	/* uboot_tag == 2 */
	if (!machine_desc)
#endif
	{
		/* No, so try the embedded one */
		machine_desc = setup_machine_fdt(__dtb_start);
		if (!machine_desc)
			panic("Embedded DT invalid\n");

		/*
		 * If we are here, it is established that @uboot_arg didn't
		 * point to DT blob. Instead if u-boot says it is cmdline,
		 * append to embedded DT cmdline.
		 * setup_machine_fdt() would have populated @boot_command_line
		 */
		if (uboot_tag == 1) {
			/* Ensure a whitespace between the 2 cmdlines */
			strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
			strlcat(boot_command_line, uboot_arg,
				COMMAND_LINE_SIZE);
		}
	}

	/* Save unparsed command line copy for /proc/cmdline */
	*cmdline_p = boot_command_line;

	/* To force early parsing of things like mem=xxx */
	parse_early_param();

	/* Platform/board specific: e.g. early console registration */
	if (machine_desc->init_early)
		machine_desc->init_early();

	smp_init_cpus();

	setup_processor();
	setup_arch_memory();

	/* copy flat DT out of .init and then unflatten it */
	unflatten_and_copy_device_tree();

	/* Can be issue if someone passes cmd line arg "ro"
	 * But that is unlikely so keeping it as it is
	 */
	root_mountflags &= ~MS_RDONLY;

#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
#endif

	arc_unwind_init();
}

static int __init customize_machine(void)
{
	if (machine_desc->init_machine)
		machine_desc->init_machine();

	return 0;
}
arch_initcall(customize_machine);

static int __init init_late_machine(void)
{
	if (machine_desc->init_late)
		machine_desc->init_late();

	return 0;
}
late_initcall(init_late_machine);
/*
 *  Get CPU information for use by the procfs.
 */

#define cpu_to_ptr(c)	((void *)(0xFFFF0000 | (unsigned int)(c)))
#define ptr_to_cpu(p)	(~0xFFFF0000UL & (unsigned int)(p))

static int show_cpuinfo(struct seq_file *m, void *v)
{
	char *str;
	int cpu_id = ptr_to_cpu(v);
	struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk");
	u32 freq = 0;

	if (!cpu_online(cpu_id)) {
		seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
		goto done;
	}

	str = (char *)__get_free_page(GFP_TEMPORARY);
	if (!str)
		goto done;

	seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));

	of_property_read_u32(core_clk, "clock-frequency", &freq);
	if (freq)
		seq_printf(m, "CPU speed\t: %u.%02u Mhz\n",
			   freq / 1000000, (freq / 10000) % 100);

	seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
		   loops_per_jiffy / (500000 / HZ),
		   (loops_per_jiffy / (5000 / HZ)) % 100);

	seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
	seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
	seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
	seq_printf(m, arc_platform_smp_cpuinfo());

	free_page((unsigned long)str);
done:
	seq_printf(m, "\n");

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	/*
	 * Callback returns cpu-id to iterator for show routine, NULL to stop.
	 * However since NULL is also a valid cpu-id (0), we use a round-about
	 * way to pass it w/o having to kmalloc/free a 2 byte string.
	 * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
	 */
	return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return c_start(m, pos);
}

static void c_stop(struct seq_file *m, void *v)
{
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= show_cpuinfo
};

static DEFINE_PER_CPU(struct cpu, cpu_topology);

static int __init topology_init(void)
{
	int cpu;

	for_each_present_cpu(cpu)
	    register_cpu(&per_cpu(cpu_topology, cpu), cpu);

	return 0;
}

subsys_initcall(topology_init);
Commit	Line	Data
c121c506 VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/seq_file.h>
	10	#include <linux/fs.h>
	11	#include <linux/delay.h>
	12	#include <linux/root_dev.h>
	13	#include <linux/console.h>
	14	#include <linux/module.h>
	15	#include <linux/cpu.h>
999159a5	16	#include <linux/of_fdt.h>
1ce0b585	17	#include <linux/of.h>
1ec9db10	18	#include <linux/cache.h>
999159a5	19	#include <asm/sections.h>
c121c506 VG	20	#include <asm/arcregs.h>
c121c506 VG	21	#include <asm/tlb.h>
c121c506 VG	22	#include <asm/setup.h>
	23	#include <asm/page.h>
	24	#include <asm/irq.h>
854a0d95	25	#include <asm/unwind.h>
03a6d28c	26	#include <asm/mach_desc.h>
619f3018	27	#include <asm/smp.h>
c121c506 VG	28
	29	#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
	30
4255b07f VG	31	unsigned int intr_to_DE_cnt;
4255b07f VG	32
59ed9413 VG	33	/* Part of U-boot ABI: see head.S */
	34	int __initdata uboot_tag;
	35	char __initdata *uboot_arg;
	36
880beb88	37	const struct machine_desc *machine_desc;
c121c506 VG	38
	39	struct task_struct _current_task[NR_CPUS]; / For stack switching */
	40
	41	struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
	42
a150b085 VG	43	static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
	44	{
	45	if (is_isa_arcompact()) {
	46	struct bcr_iccm_arcompact iccm;
	47	struct bcr_dccm_arcompact dccm;
	48
	49	READ_BCR(ARC_REG_ICCM_BUILD, iccm);
	50	if (iccm.ver) {
	51	cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
	52	cpu->iccm.base_addr = iccm.base << 16;
	53	}
	54
	55	READ_BCR(ARC_REG_DCCM_BUILD, dccm);
	56	if (dccm.ver) {
	57	unsigned long base;
	58	cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
	59
	60	base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
	61	cpu->dccm.base_addr = base & ~0xF;
	62	}
	63	} else {
	64	struct bcr_iccm_arcv2 iccm;
	65	struct bcr_dccm_arcv2 dccm;
	66	unsigned long region;
	67
	68	READ_BCR(ARC_REG_ICCM_BUILD, iccm);
	69	if (iccm.ver) {
	70	cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
	71	if (iccm.sz00 == 0xF && iccm.sz01 > 0)
	72	cpu->iccm.sz <<= iccm.sz01;
	73
	74	region = read_aux_reg(ARC_REG_AUX_ICCM);
	75	cpu->iccm.base_addr = region & 0xF0000000;
	76	}
	77
	78	READ_BCR(ARC_REG_DCCM_BUILD, dccm);
	79	if (dccm.ver) {
	80	cpu->dccm.sz = 256 << dccm.sz0;
	81	if (dccm.sz0 == 0xF && dccm.sz1 > 0)
	82	cpu->dccm.sz <<= dccm.sz1;
	83
	84	region = read_aux_reg(ARC_REG_AUX_DCCM);
	85	cpu->dccm.base_addr = region & 0xF0000000;
	86	}
	87	}
	88	}
	89
8e457d6a	90	static void read_arc_build_cfg_regs(void)
c121c506	91	{
b89bd1f4	92	struct bcr_timer timer;
56372082	93	struct bcr_generic bcr;
af617428 VG	94	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
	95	FIX_PTR(cpu);
	96
	97	READ_BCR(AUX_IDENTITY, cpu->core);
56372082	98	READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
af617428	99
b89bd1f4 VG	100	READ_BCR(ARC_REG_TIMERS_BCR, timer);
	101	cpu->extn.timer0 = timer.t0;
	102	cpu->extn.timer1 = timer.t1;
	103	cpu->extn.rtc = timer.rtc;
	104
af617428	105	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
af617428	106
56372082	107	READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
af617428	108
56372082 VG	109	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
	110	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
	111	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
	112	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
	113	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
af617428 VG	114	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
af617428 VG	115
a150b085 VG	116	/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
	117	read_decode_ccm_bcr(cpu);
	118
c121c506 VG	119	read_decode_mmu_bcr();
c121c506 VG	120	read_decode_cache_bcr();
af617428	121
1f6ccfff	122	if (is_isa_arcompact()) {
56372082 VG	123	struct bcr_fp_arcompact sp, dp;
	124	struct bcr_bpu_arcompact bpu;
	125
	126	READ_BCR(ARC_REG_FP_BCR, sp);
	127	READ_BCR(ARC_REG_DPFP_BCR, dp);
	128	cpu->extn.fpu_sp = sp.ver ? 1 : 0;
	129	cpu->extn.fpu_dp = dp.ver ? 1 : 0;
	130
	131	READ_BCR(ARC_REG_BPU_BCR, bpu);
	132	cpu->bpu.ver = bpu.ver;
	133	cpu->bpu.full = bpu.fam ? 1 : 0;
	134	if (bpu.ent) {
	135	cpu->bpu.num_cache = 256 << (bpu.ent - 1);
	136	cpu->bpu.num_pred = 256 << (bpu.ent - 1);
	137	}
1f6ccfff VG	138	} else {
	139	struct bcr_fp_arcv2 spdp;
	140	struct bcr_bpu_arcv2 bpu;
	141
	142	READ_BCR(ARC_REG_FP_V2_BCR, spdp);
	143	cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
	144	cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
	145
	146	READ_BCR(ARC_REG_BPU_BCR, bpu);
	147	cpu->bpu.ver = bpu.ver;
	148	cpu->bpu.full = bpu.ft;
	149	cpu->bpu.num_cache = 256 << bpu.bce;
	150	cpu->bpu.num_pred = 2048 << bpu.pte;
56372082 VG	151	}
	152
	153	READ_BCR(ARC_REG_AP_BCR, bcr);
	154	cpu->extn.ap = bcr.ver ? 1 : 0;
	155
	156	READ_BCR(ARC_REG_SMART_BCR, bcr);
	157	cpu->extn.smart = bcr.ver ? 1 : 0;
	158
a44ec8bd VG	159	READ_BCR(ARC_REG_RTT_BCR, bcr);
	160	cpu->extn.rtt = bcr.ver ? 1 : 0;
	161
	162	cpu->extn.debug = cpu->extn.ap \| cpu->extn.smart \| cpu->extn.rtt;
af617428 VG	163	}
	164
	165	static const struct cpuinfo_data arc_cpu_tbl[] = {
624b71ee	166	#ifdef CONFIG_ISA_ARCOMPACT
af617428 VG	167	{ {0x20, "ARC 600" }, 0x2F},
	168	{ {0x30, "ARC 700" }, 0x33},
	169	{ {0x34, "ARC 700 R4.10"}, 0x34},
56372082	170	{ {0x35, "ARC 700 R4.11"}, 0x35},
624b71ee VG	171	#else
	172	{ {0x50, "ARC HS38 R2.0"}, 0x51},
	173	{ {0x52, "ARC HS38 R2.1"}, 0x52},
f5076846	174	{ {0x53, "ARC HS38 R3.0"}, 0x53},
624b71ee	175	#endif
af617428 VG	176	{ {0x00, NULL } }
	177	};
	178
56372082	179
8e457d6a	180	static char arc_cpu_mumbojumbo(int cpu_id, char buf, int len)
af617428	181	{
af617428 VG	182	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
	183	struct bcr_identity *core = &cpu->core;
	184	const struct cpuinfo_data *tbl;
56372082 VG	185	char *isa_nm;
	186	int i, be, atomic;
	187	int n = 0;
	188
af617428 VG	189	FIX_PTR(cpu);
af617428 VG	190
1f6ccfff	191	if (is_isa_arcompact()) {
56372082 VG	192	isa_nm = "ARCompact";
	193	be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
	194
	195	atomic = cpu->isa.atomic1;
	196	if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
	197	atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
1f6ccfff VG	198	} else {
	199	isa_nm = "ARCv2";
	200	be = cpu->isa.be;
	201	atomic = cpu->isa.atomic;
56372082 VG	202	}
56372082 VG	203
af617428	204	n += scnprintf(buf + n, len - n,
56372082 VG	205	"\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
56372082 VG	206	core->family, core->cpu_id, core->chip_id);
af617428 VG	207
	208	for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
	209	if ((core->family >= tbl->info.id) &&
	210	(core->family <= tbl->up_range)) {
	211	n += scnprintf(buf + n, len - n,
56372082 VG	212	"processor [%d]\t: %s (%s ISA) %s\n",
	213	cpu_id, tbl->info.str, isa_nm,
	214	IS_AVAIL1(be, "[Big-Endian]"));
af617428 VG	215	break;
	216	}
	217	}
	218
	219	if (tbl->info.id == 0)
	220	n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
	221
aa93e8ef	222	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
b89bd1f4 VG	223	IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
	224	IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
	225	IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
aa93e8ef	226	CONFIG_ARC_HAS_RTC));
af617428	227
1f6ccfff VG	228	n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
	229	IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
	230	IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
	231	IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
af617428	232
56372082 VG	233	if (i)
56372082 VG	234	n += scnprintf(buf + n, len - n, "\n\t\t: ");
af617428	235
1f6ccfff VG	236	if (cpu->extn_mpy.ver) {
	237	if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */
	238	n += scnprintf(buf + n, len - n, "mpy ");
	239	} else {
	240	int opt = 2; /* stock MPY/MPYH */
	241
	242	if (cpu->extn_mpy.dsp) /* OPT 7-9 */
	243	opt = cpu->extn_mpy.dsp + 6;
	244
	245	n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
	246	}
1f6ccfff VG	247	}
1f6ccfff VG	248
56372082	249	n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
1f6ccfff	250	IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
56372082 VG	251	IS_AVAIL1(cpu->extn.norm, "norm "),
	252	IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
	253	IS_AVAIL1(cpu->extn.swap, "swap "),
	254	IS_AVAIL1(cpu->extn.minmax, "minmax "),
	255	IS_AVAIL1(cpu->extn.crc, "crc "),
	256	IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
af617428	257
56372082 VG	258	if (cpu->bpu.ver)
	259	n += scnprintf(buf + n, len - n,
	260	"BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
	261	IS_AVAIL1(cpu->bpu.full, "full"),
	262	IS_AVAIL1(!cpu->bpu.full, "partial"),
	263	cpu->bpu.num_cache, cpu->bpu.num_pred);
af617428	264
56372082 VG	265	return buf;
56372082 VG	266	}
af617428	267
8e457d6a	268	static char arc_extn_mumbojumbo(int cpu_id, char buf, int len)
af617428 VG	269	{
	270	int n = 0;
	271	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
	272
	273	FIX_PTR(cpu);
af617428	274
711c1f26	275	n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
56372082 VG	276
	277	if (cpu->extn.fpu_sp \|\| cpu->extn.fpu_dp)
	278	n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
	279	IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
	280	IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
	281
	282	if (cpu->extn.debug)
	283	n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
	284	IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
	285	IS_AVAIL1(cpu->extn.smart, "smaRT "),
	286	IS_AVAIL1(cpu->extn.rtt, "RTT "));
	287
	288	if (cpu->dccm.sz \|\| cpu->iccm.sz)
	289	n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
	290	cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
af617428 VG	291	cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
af617428 VG	292
840c054f VG	293	n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
	294	EF_ARC_OSABI_CURRENT >> 8,
	295	EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
	296	"no-legacy-syscalls" : "64-bit data any register aligned");
af617428 VG	297
	298	return buf;
	299	}
	300
c4b9856b	301	static void arc_chk_core_config(void)
8b5850f8	302	{
8b5850f8	303	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
c4b9856b	304	int fpu_enabled;
8b5850f8	305
b89bd1f4	306	if (!cpu->extn.timer0)
56372082 VG	307	panic("Timer0 is not present!\n");
56372082 VG	308
b89bd1f4	309	if (!cpu->extn.timer1)
56372082 VG	310	panic("Timer1 is not present!\n");
56372082 VG	311
8b5850f8 VG	312	#ifdef CONFIG_ARC_HAS_DCCM
	313	/*
	314	* DCCM can be arbit placed in hardware.
	315	* Make sure it's placement/sz matches what Linux is built with
	316	*/
	317	if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
	318	panic("Linux built with incorrect DCCM Base address\n");
	319
	320	if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
	321	panic("Linux built with incorrect DCCM Size\n");
	322	#endif
	323
	324	#ifdef CONFIG_ARC_HAS_ICCM
	325	if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
	326	panic("Linux built with incorrect ICCM Size\n");
	327	#endif
8b5850f8	328
c4b9856b VG	329	/*
	330	* FP hardware/software config sanity
	331	* -If hardware contains DPFP, kernel needs to save/restore FPU state
	332	* -If not, it will crash trying to save/restore the non-existant regs
	333	*
	334	* (only DPDP checked since SP has no arch visible regs)
	335	*/
	336	fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
af617428	337
56372082	338	if (cpu->extn.fpu_dp && !fpu_enabled)
c4b9856b	339	pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
56372082	340	else if (!cpu->extn.fpu_dp && fpu_enabled)
c4b9856b	341	panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
c121c506 VG	342	}
	343
	344	/*
	345	* Initialize and setup the processor core
	346	* This is called by all the CPUs thus should not do special case stuff
	347	* such as only for boot CPU etc
	348	*/
	349
ce759956	350	void setup_processor(void)
c121c506	351	{
af617428 VG	352	char str[512];
	353	int cpu_id = smp_processor_id();
	354
c121c506 VG	355	read_arc_build_cfg_regs();
c121c506 VG	356	arc_init_IRQ();
af617428 VG	357
	358	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
	359
c121c506 VG	360	arc_mmu_init();
c121c506 VG	361	arc_cache_init();
af617428 VG	362
af617428 VG	363	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
af617428	364	printk(arc_platform_smp_cpuinfo());
af617428	365
c4b9856b	366	arc_chk_core_config();
c121c506 VG	367	}
c121c506 VG	368
59ed9413 VG	369	static inline int is_kernel(unsigned long addr)
	370	{
	371	if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
	372	return 1;
	373	return 0;
	374	}
	375
c121c506 VG	376	void __init setup_arch(char **cmdline_p)
c121c506 VG	377	{
036b2c56	378	#ifdef CONFIG_ARC_UBOOT_SUPPORT
e57d339a VG	379	/* make sure that uboot passed pointer to cmdline/dtb is valid */
	380	if (uboot_tag && is_kernel((unsigned long)uboot_arg))
	381	panic("Invalid uboot arg\n");
	382
	383	/* See if u-boot passed an external Device Tree blob */
	384	machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */
036b2c56 VG	385	if (!machine_desc)
	386	#endif
	387	{
e57d339a	388	/* No, so try the embedded one */
59ed9413 VG	389	machine_desc = setup_machine_fdt(__dtb_start);
	390	if (!machine_desc)
	391	panic("Embedded DT invalid\n");
	392
	393	/*
e57d339a VG	394	* If we are here, it is established that @uboot_arg didn't
e57d339a VG	395	* point to DT blob. Instead if u-boot says it is cmdline,
2547476a	396	* append to embedded DT cmdline.
59ed9413 VG	397	* setup_machine_fdt() would have populated @boot_command_line
	398	*/
	399	if (uboot_tag == 1) {
59ed9413 VG	400	/* Ensure a whitespace between the 2 cmdlines */
	401	strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
	402	strlcat(boot_command_line, uboot_arg,
	403	COMMAND_LINE_SIZE);
	404	}
e57d339a	405	}
c121c506 VG	406
c121c506 VG	407	/* Save unparsed command line copy for /proc/cmdline */
9593a933	408	*cmdline_p = boot_command_line;
999159a5	409
c121c506 VG	410	/* To force early parsing of things like mem=xxx */
	411	parse_early_param();
	412
	413	/* Platform/board specific: e.g. early console registration */
03a6d28c VG	414	if (machine_desc->init_early)
03a6d28c VG	415	machine_desc->init_early();
c121c506	416
41195d23	417	smp_init_cpus();
e55af4da VG	418
e55af4da VG	419	setup_processor();
c121c506 VG	420	setup_arch_memory();
c121c506 VG	421
eab6a08c	422	/* copy flat DT out of .init and then unflatten it */
1efc959e	423	unflatten_and_copy_device_tree();
999159a5	424
c121c506 VG	425	/* Can be issue if someone passes cmd line arg "ro"
	426	* But that is unlikely so keeping it as it is
	427	*/
	428	root_mountflags &= ~MS_RDONLY;
	429
c121c506 VG	430	#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
	431	conswitchp = &dummy_con;
	432	#endif
	433
854a0d95	434	arc_unwind_init();
c121c506 VG	435	}
c121c506 VG	436
03a6d28c VG	437	static int __init customize_machine(void)
03a6d28c VG	438	{
03a6d28c VG	439	if (machine_desc->init_machine)
	440	machine_desc->init_machine();
	441
	442	return 0;
	443	}
	444	arch_initcall(customize_machine);
	445
	446	static int __init init_late_machine(void)
	447	{
	448	if (machine_desc->init_late)
	449	machine_desc->init_late();
	450
	451	return 0;
	452	}
	453	late_initcall(init_late_machine);
c121c506 VG	454	/*
	455	* Get CPU information for use by the procfs.
	456	*/
	457
	458	#define cpu_to_ptr(c) ((void *)(0xFFFF0000 \| (unsigned int)(c)))
	459	#define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
	460
	461	static int show_cpuinfo(struct seq_file m, void v)
	462	{
	463	char *str;
	464	int cpu_id = ptr_to_cpu(v);
20c7dbbd AB	465	struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk");
20c7dbbd AB	466	u32 freq = 0;
c121c506	467
4c86231c VG	468	if (!cpu_online(cpu_id)) {
	469	seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
	470	goto done;
	471	}
	472
c121c506 VG	473	str = (char *)__get_free_page(GFP_TEMPORARY);
	474	if (!str)
	475	goto done;
	476
af617428	477	seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
c121c506	478
20c7dbbd AB	479	of_property_read_u32(core_clk, "clock-frequency", &freq);
	480	if (freq)
	481	seq_printf(m, "CPU speed\t: %u.%02u Mhz\n",
	482	freq / 1000000, (freq / 10000) % 100);
	483
56372082	484	seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
c121c506 VG	485	loops_per_jiffy / (500000 / HZ),
	486	(loops_per_jiffy / (5000 / HZ)) % 100);
	487
af617428	488	seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
af617428	489	seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
af617428	490	seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
af617428	491	seq_printf(m, arc_platform_smp_cpuinfo());
af617428	492
c121c506 VG	493	free_page((unsigned long)str);
c121c506 VG	494	done:
4c86231c	495	seq_printf(m, "\n");
c121c506 VG	496
	497	return 0;
	498	}
	499
	500	static void c_start(struct seq_file m, loff_t *pos)
	501	{
	502	/*
	503	* Callback returns cpu-id to iterator for show routine, NULL to stop.
	504	* However since NULL is also a valid cpu-id (0), we use a round-about
	505	* way to pass it w/o having to kmalloc/free a 2 byte string.
	506	* Encode cpu-id as 0xFFcccc, which is decoded by show routine.
	507	*/
3da43104	508	return pos < nr_cpu_ids ? cpu_to_ptr(pos) : NULL;
c121c506 VG	509	}
	510
	511	static void c_next(struct seq_file m, void v, loff_t pos)
	512	{
	513	++*pos;
	514	return c_start(m, pos);
	515	}
	516
	517	static void c_stop(struct seq_file m, void v)
	518	{
	519	}
	520
	521	const struct seq_operations cpuinfo_op = {
	522	.start = c_start,
	523	.next = c_next,
	524	.stop = c_stop,
	525	.show = show_cpuinfo
	526	};
	527
	528	static DEFINE_PER_CPU(struct cpu, cpu_topology);
	529
	530	static int __init topology_init(void)
	531	{
	532	int cpu;
	533
	534	for_each_present_cpu(cpu)
	535	register_cpu(&per_cpu(cpu_topology, cpu), cpu);
	536
	537	return 0;
	538	}
	539
	540	subsys_initcall(topology_init);