Commit | Line | Data |
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82fea5a1 VG |
1 | /* |
2 | * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) | |
3 | * | |
4 | * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/smp.h> | |
12 | #include <linux/irq.h> | |
e51d5d02 | 13 | #include <linux/irqchip/chained_irq.h> |
82fea5a1 | 14 | #include <linux/spinlock.h> |
2d7f5c48 | 15 | #include <soc/arc/mcip.h> |
bb143f81 | 16 | #include <asm/irqflags-arcv2.h> |
964cf28f | 17 | #include <asm/setup.h> |
82fea5a1 | 18 | |
82fea5a1 VG |
19 | static DEFINE_RAW_SPINLOCK(mcip_lock); |
20 | ||
3ce0fefc VG |
21 | #ifdef CONFIG_SMP |
22 | ||
23 | static char smp_cpuinfo_buf[128]; | |
24 | ||
aa0efcde | 25 | static void mcip_setup_per_cpu(int cpu) |
82fea5a1 VG |
26 | { |
27 | smp_ipi_irq_setup(cpu, IPI_IRQ); | |
bb143f81 | 28 | smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); |
82fea5a1 VG |
29 | } |
30 | ||
31 | static void mcip_ipi_send(int cpu) | |
32 | { | |
33 | unsigned long flags; | |
aa6083ed VG |
34 | int ipi_was_pending; |
35 | ||
bb143f81 VG |
36 | /* ARConnect can only send IPI to others */ |
37 | if (unlikely(cpu == raw_smp_processor_id())) { | |
38 | arc_softirq_trigger(SOFTIRQ_IRQ); | |
39 | return; | |
40 | } | |
41 | ||
3dea30ca VG |
42 | raw_spin_lock_irqsave(&mcip_lock, flags); |
43 | ||
aa6083ed | 44 | /* |
3dea30ca VG |
45 | * If receiver already has a pending interrupt, elide sending this one. |
46 | * Linux cross core calling works well with concurrent IPIs | |
47 | * coalesced into one | |
48 | * see arch/arc/kernel/smp.c: ipi_send_msg_one() | |
aa6083ed | 49 | */ |
3dea30ca VG |
50 | __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); |
51 | ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); | |
52 | if (!ipi_was_pending) | |
53 | __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); | |
aa6083ed | 54 | |
82fea5a1 VG |
55 | raw_spin_unlock_irqrestore(&mcip_lock, flags); |
56 | } | |
57 | ||
58 | static void mcip_ipi_clear(int irq) | |
59 | { | |
aa6083ed | 60 | unsigned int cpu, c; |
82fea5a1 VG |
61 | unsigned long flags; |
62 | ||
bb143f81 VG |
63 | if (unlikely(irq == SOFTIRQ_IRQ)) { |
64 | arc_softirq_clear(irq); | |
65 | return; | |
66 | } | |
67 | ||
82fea5a1 VG |
68 | raw_spin_lock_irqsave(&mcip_lock, flags); |
69 | ||
70 | /* Who sent the IPI */ | |
71 | __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); | |
72 | ||
d73b73f5 | 73 | cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ |
82fea5a1 | 74 | |
aa6083ed VG |
75 | /* |
76 | * In rare case, multiple concurrent IPIs sent to same target can | |
77 | * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be | |
78 | * "vectored" (multiple bits sets) as opposed to typical single bit | |
79 | */ | |
80 | do { | |
81 | c = __ffs(cpu); /* 0,1,2,3 */ | |
82 | __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); | |
83 | cpu &= ~(1U << c); | |
84 | } while (cpu); | |
82fea5a1 VG |
85 | |
86 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
87 | } | |
88 | ||
26b8f996 | 89 | static void mcip_probe_n_setup(void) |
82fea5a1 | 90 | { |
3ce0fefc | 91 | struct mcip_bcr mp; |
82fea5a1 VG |
92 | |
93 | READ_BCR(ARC_REG_MCIP_BCR, mp); | |
94 | ||
95 | sprintf(smp_cpuinfo_buf, | |
98341f7d | 96 | "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n", |
82fea5a1 VG |
97 | mp.ver, mp.num_cores, |
98 | IS_AVAIL1(mp.ipi, "IPI "), | |
99 | IS_AVAIL1(mp.idu, "IDU "), | |
98341f7d | 100 | IS_AVAIL1(mp.llm, "LLM "), |
82fea5a1 | 101 | IS_AVAIL1(mp.dbg, "DEBUG "), |
d584f0fb | 102 | IS_AVAIL1(mp.gfrc, "GFRC")); |
82fea5a1 | 103 | |
e608b53e | 104 | cpuinfo_arc700[0].extn.gfrc = mp.gfrc; |
eaf0ecc3 | 105 | |
82fea5a1 VG |
106 | if (mp.dbg) { |
107 | __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); | |
108 | __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); | |
109 | } | |
110 | } | |
eaf0ecc3 | 111 | |
26b8f996 VG |
112 | struct plat_smp_ops plat_smp_ops = { |
113 | .info = smp_cpuinfo_buf, | |
114 | .init_early_smp = mcip_probe_n_setup, | |
b474a023 | 115 | .init_per_cpu = mcip_setup_per_cpu, |
26b8f996 VG |
116 | .ipi_send = mcip_ipi_send, |
117 | .ipi_clear = mcip_ipi_clear, | |
118 | }; | |
119 | ||
3ce0fefc VG |
120 | #endif |
121 | ||
eaf0ecc3 VG |
122 | /*************************************************************************** |
123 | * ARCv2 Interrupt Distribution Unit (IDU) | |
124 | * | |
125 | * Connects external "COMMON" IRQs to core intc, providing: | |
126 | * -dynamic routing (IRQ affinity) | |
127 | * -load balancing (Round Robin interrupt distribution) | |
128 | * -1:N distribution | |
129 | * | |
130 | * It physically resides in the MCIP hw block | |
131 | */ | |
132 | ||
133 | #include <linux/irqchip.h> | |
134 | #include <linux/of.h> | |
135 | #include <linux/of_irq.h> | |
eaf0ecc3 VG |
136 | |
137 | /* | |
138 | * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) | |
139 | */ | |
140 | static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) | |
141 | { | |
142 | __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); | |
143 | } | |
144 | ||
145 | static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, | |
146 | unsigned int distr) | |
147 | { | |
148 | union { | |
149 | unsigned int word; | |
150 | struct { | |
151 | unsigned int distr:2, pad:2, lvl:1, pad2:27; | |
152 | }; | |
153 | } data; | |
154 | ||
155 | data.distr = distr; | |
156 | data.lvl = lvl; | |
157 | __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); | |
158 | } | |
159 | ||
160 | static void idu_irq_mask(struct irq_data *data) | |
161 | { | |
162 | unsigned long flags; | |
163 | ||
164 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
165 | __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); | |
166 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
167 | } | |
168 | ||
169 | static void idu_irq_unmask(struct irq_data *data) | |
170 | { | |
171 | unsigned long flags; | |
172 | ||
173 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
174 | __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); | |
175 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
176 | } | |
177 | ||
83ce3e6f | 178 | #ifdef CONFIG_SMP |
eaf0ecc3 | 179 | static int |
83ce3e6f VG |
180 | idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, |
181 | bool force) | |
eaf0ecc3 | 182 | { |
83ce3e6f VG |
183 | unsigned long flags; |
184 | cpumask_t online; | |
0a0a047d YK |
185 | unsigned int destination_bits; |
186 | unsigned int distribution_mode; | |
83ce3e6f VG |
187 | |
188 | /* errout if no online cpu per @cpumask */ | |
189 | if (!cpumask_and(&online, cpumask, cpu_online_mask)) | |
190 | return -EINVAL; | |
191 | ||
192 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
193 | ||
0a0a047d YK |
194 | destination_bits = cpumask_bits(&online)[0]; |
195 | idu_set_dest(data->hwirq, destination_bits); | |
196 | ||
197 | if (ffs(destination_bits) == fls(destination_bits)) | |
198 | distribution_mode = IDU_M_DISTRI_DEST; | |
199 | else | |
200 | distribution_mode = IDU_M_DISTRI_RR; | |
201 | ||
202 | idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode); | |
83ce3e6f VG |
203 | |
204 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
205 | ||
eaf0ecc3 VG |
206 | return IRQ_SET_MASK_OK; |
207 | } | |
83ce3e6f | 208 | #endif |
eaf0ecc3 VG |
209 | |
210 | static struct irq_chip idu_irq_chip = { | |
211 | .name = "MCIP IDU Intc", | |
212 | .irq_mask = idu_irq_mask, | |
213 | .irq_unmask = idu_irq_unmask, | |
214 | #ifdef CONFIG_SMP | |
215 | .irq_set_affinity = idu_irq_set_affinity, | |
216 | #endif | |
217 | ||
218 | }; | |
219 | ||
34e71e4c | 220 | static irq_hw_number_t idu_first_hwirq; |
eaf0ecc3 | 221 | |
bd0b9ac4 | 222 | static void idu_cascade_isr(struct irq_desc *desc) |
eaf0ecc3 | 223 | { |
34e71e4c | 224 | struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); |
e51d5d02 | 225 | struct irq_chip *core_chip = irq_desc_get_chip(desc); |
34e71e4c YK |
226 | irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); |
227 | irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq; | |
eaf0ecc3 | 228 | |
e51d5d02 | 229 | chained_irq_enter(core_chip, desc); |
34e71e4c | 230 | generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); |
e51d5d02 | 231 | chained_irq_exit(core_chip, desc); |
eaf0ecc3 VG |
232 | } |
233 | ||
234 | static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) | |
235 | { | |
236 | irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); | |
237 | irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, | |
243 | const u32 *intspec, unsigned int intsize, | |
244 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | |
245 | { | |
246 | irq_hw_number_t hwirq = *out_hwirq = intspec[0]; | |
247 | int distri = intspec[1]; | |
248 | unsigned long flags; | |
249 | ||
250 | *out_type = IRQ_TYPE_NONE; | |
251 | ||
252 | /* XXX: validate distribution scheme again online cpu mask */ | |
253 | if (distri == 0) { | |
254 | /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ | |
255 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
256 | idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); | |
257 | idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); | |
258 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
259 | } else { | |
260 | /* | |
261 | * DEST based distribution for Level Triggered intr can only | |
262 | * have 1 CPU, so generalize it to always contain 1 cpu | |
263 | */ | |
264 | int cpu = ffs(distri); | |
265 | ||
266 | if (cpu != fls(distri)) | |
267 | pr_warn("IDU irq %lx distri mode set to cpu %x\n", | |
268 | hwirq, cpu); | |
269 | ||
270 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
271 | idu_set_dest(hwirq, cpu); | |
272 | idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); | |
273 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static const struct irq_domain_ops idu_irq_ops = { | |
280 | .xlate = idu_irq_xlate, | |
281 | .map = idu_irq_map, | |
282 | }; | |
283 | ||
284 | /* | |
285 | * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) | |
286 | * [24, 23+C]: If C > 0 then "C" common IRQs | |
287 | * [24+C, N]: Not statically assigned, private-per-core | |
288 | */ | |
289 | ||
290 | ||
291 | static int __init | |
292 | idu_of_init(struct device_node *intc, struct device_node *parent) | |
293 | { | |
294 | struct irq_domain *domain; | |
295 | /* Read IDU BCR to confirm nr_irqs */ | |
296 | int nr_irqs = of_irq_count(intc); | |
34e71e4c | 297 | int i, virq; |
3ce0fefc VG |
298 | struct mcip_bcr mp; |
299 | ||
300 | READ_BCR(ARC_REG_MCIP_BCR, mp); | |
eaf0ecc3 | 301 | |
3ce0fefc | 302 | if (!mp.idu) |
eaf0ecc3 VG |
303 | panic("IDU not detected, but DeviceTree using it"); |
304 | ||
305 | pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); | |
306 | ||
307 | domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); | |
308 | ||
309 | /* Parent interrupts (core-intc) are already mapped */ | |
310 | ||
311 | for (i = 0; i < nr_irqs; i++) { | |
312 | /* | |
313 | * Return parent uplink IRQs (towards core intc) 24,25,..... | |
314 | * this step has been done before already | |
315 | * however we need it to get the parent virq and set IDU handler | |
316 | * as first level isr | |
317 | */ | |
34e71e4c | 318 | virq = irq_of_parse_and_map(intc, i); |
eaf0ecc3 | 319 | if (!i) |
34e71e4c | 320 | idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); |
eaf0ecc3 | 321 | |
34e71e4c | 322 | irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain); |
eaf0ecc3 VG |
323 | } |
324 | ||
325 | __mcip_cmd(CMD_IDU_ENABLE, 0); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); |