[linux-2.6-block.git] / arch / arc / kernel / mcip.c

/*
 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
 *
 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/smp.h>
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/mcip.h>

static char smp_cpuinfo_buf[128];
static int idu_detected;

static DEFINE_RAW_SPINLOCK(mcip_lock);

/*
 * Any SMP specific init any CPU does when it comes up.
 * Here we setup the CPU to enable Inter-Processor-Interrupts
 * Called for each CPU
 * -Master      : init_IRQ()
 * -Other(s)    : start_kernel_secondary()
 */
void mcip_init_smp(unsigned int cpu)
{
	smp_ipi_irq_setup(cpu, IPI_IRQ);
}

static void mcip_ipi_send(int cpu)
{
	unsigned long flags;
	int ipi_was_pending;

	/*
	 * NOTE: We must spin here if the other cpu hasn't yet
	 * serviced a previous message. This can burn lots
	 * of time, but we MUST follows this protocol or
	 * ipi messages can be lost!!!
	 * Also, we must release the lock in this loop because
	 * the other side may get to this same loop and not
	 * be able to ack -- thus causing deadlock.
	 */

	do {
		raw_spin_lock_irqsave(&mcip_lock, flags);
		__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
		ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
		if (ipi_was_pending == 0)
			break; /* break out but keep lock */
		raw_spin_unlock_irqrestore(&mcip_lock, flags);
	} while (1);

	__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
	raw_spin_unlock_irqrestore(&mcip_lock, flags);

#ifdef CONFIG_ARC_IPI_DBG
	if (ipi_was_pending)
		pr_info("IPI ACK delayed from cpu %d\n", cpu);
#endif
}

static void mcip_ipi_clear(int irq)
{
	unsigned int cpu, c;
	unsigned long flags;
	unsigned int __maybe_unused copy;

	raw_spin_lock_irqsave(&mcip_lock, flags);

	/* Who sent the IPI */
	__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);

	copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK);	/* 1,2,4,8... */

	/*
	 * In rare case, multiple concurrent IPIs sent to same target can
	 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
	 * "vectored" (multiple bits sets) as opposed to typical single bit
	 */
	do {
		c = __ffs(cpu);			/* 0,1,2,3 */
		__mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
		cpu &= ~(1U << c);
	} while (cpu);

	raw_spin_unlock_irqrestore(&mcip_lock, flags);

#ifdef CONFIG_ARC_IPI_DBG
	if (c != __ffs(copy))
		pr_info("IPIs from %x coalesced to %x\n",
			copy, raw_smp_processor_id());
#endif
}

volatile int wake_flag;

static void mcip_wakeup_cpu(int cpu, unsigned long pc)
{
	BUG_ON(cpu == 0);
	wake_flag = cpu;
}

void arc_platform_smp_wait_to_boot(int cpu)
{
	while (wake_flag != cpu)
		;

	wake_flag = 0;
	__asm__ __volatile__("j @first_lines_of_secondary	\n");
}

struct plat_smp_ops plat_smp_ops = {
	.info		= smp_cpuinfo_buf,
	.cpu_kick	= mcip_wakeup_cpu,
	.ipi_send	= mcip_ipi_send,
	.ipi_clear	= mcip_ipi_clear,
};

void mcip_init_early_smp(void)
{
#define IS_AVAIL1(var, str)    ((var) ? str : "")

	struct mcip_bcr {
#ifdef CONFIG_CPU_BIG_ENDIAN
		unsigned int pad3:8,
			     idu:1, llm:1, num_cores:6,
			     iocoh:1,  grtc:1, dbg:1, pad2:1,
			     msg:1, sem:1, ipi:1, pad:1,
			     ver:8;
#else
		unsigned int ver:8,
			     pad:1, ipi:1, sem:1, msg:1,
			     pad2:1, dbg:1, grtc:1, iocoh:1,
			     num_cores:6, llm:1, idu:1,
			     pad3:8;
#endif
	} mp;

	READ_BCR(ARC_REG_MCIP_BCR, mp);

	sprintf(smp_cpuinfo_buf,
		"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
		mp.ver, mp.num_cores,
		IS_AVAIL1(mp.ipi, "IPI "),
		IS_AVAIL1(mp.idu, "IDU "),
		IS_AVAIL1(mp.dbg, "DEBUG "),
		IS_AVAIL1(mp.grtc, "GRTC"));

	idu_detected = mp.idu;

	if (mp.dbg) {
		__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
		__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
	}

	if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
		panic("kernel trying to use non-existent GRTC\n");
}

/***************************************************************************
 * ARCv2 Interrupt Distribution Unit (IDU)
 *
 * Connects external "COMMON" IRQs to core intc, providing:
 *  -dynamic routing (IRQ affinity)
 *  -load balancing (Round Robin interrupt distribution)
 *  -1:N distribution
 *
 * It physically resides in the MCIP hw block
 */

#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_irq.h>

/*
 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
 */
static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
{
	__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
}

static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
			   unsigned int distr)
{
	union {
		unsigned int word;
		struct {
			unsigned int distr:2, pad:2, lvl:1, pad2:27;
		};
	} data;

	data.distr = distr;
	data.lvl = lvl;
	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
}

static void idu_irq_mask(struct irq_data *data)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&mcip_lock, flags);
	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
	raw_spin_unlock_irqrestore(&mcip_lock, flags);
}

static void idu_irq_unmask(struct irq_data *data)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&mcip_lock, flags);
	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
	raw_spin_unlock_irqrestore(&mcip_lock, flags);
}

#ifdef CONFIG_SMP
static int
idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
		     bool force)
{
	unsigned long flags;
	cpumask_t online;

	/* errout if no online cpu per @cpumask */
	if (!cpumask_and(&online, cpumask, cpu_online_mask))
		return -EINVAL;

	raw_spin_lock_irqsave(&mcip_lock, flags);

	idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
	idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);

	raw_spin_unlock_irqrestore(&mcip_lock, flags);

	return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip idu_irq_chip = {
	.name			= "MCIP IDU Intc",
	.irq_mask		= idu_irq_mask,
	.irq_unmask		= idu_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity       = idu_irq_set_affinity,
#endif

};

static int idu_first_irq;

static void idu_cascade_isr(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	unsigned int core_irq = irq_desc_get_irq(desc);
	unsigned int idu_irq;

	idu_irq = core_irq - idu_first_irq;
	generic_handle_irq(irq_find_mapping(domain, idu_irq));
}

static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);

	return 0;
}

static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
			 const u32 *intspec, unsigned int intsize,
			 irq_hw_number_t *out_hwirq, unsigned int *out_type)
{
	irq_hw_number_t hwirq = *out_hwirq = intspec[0];
	int distri = intspec[1];
	unsigned long flags;

	*out_type = IRQ_TYPE_NONE;

	/* XXX: validate distribution scheme again online cpu mask */
	if (distri == 0) {
		/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
		raw_spin_lock_irqsave(&mcip_lock, flags);
		idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
		idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
		raw_spin_unlock_irqrestore(&mcip_lock, flags);
	} else {
		/*
		 * DEST based distribution for Level Triggered intr can only
		 * have 1 CPU, so generalize it to always contain 1 cpu
		 */
		int cpu = ffs(distri);

		if (cpu != fls(distri))
			pr_warn("IDU irq %lx distri mode set to cpu %x\n",
				hwirq, cpu);

		raw_spin_lock_irqsave(&mcip_lock, flags);
		idu_set_dest(hwirq, cpu);
		idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
		raw_spin_unlock_irqrestore(&mcip_lock, flags);
	}

	return 0;
}

static const struct irq_domain_ops idu_irq_ops = {
	.xlate	= idu_irq_xlate,
	.map	= idu_irq_map,
};

/*
 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
 * [24, 23+C]: If C > 0 then "C" common IRQs
 * [24+C, N]: Not statically assigned, private-per-core
 */


static int __init
idu_of_init(struct device_node *intc, struct device_node *parent)
{
	struct irq_domain *domain;
	/* Read IDU BCR to confirm nr_irqs */
	int nr_irqs = of_irq_count(intc);
	int i, irq;

	if (!idu_detected)
		panic("IDU not detected, but DeviceTree using it");

	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);

	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);

	/* Parent interrupts (core-intc) are already mapped */

	for (i = 0; i < nr_irqs; i++) {
		/*
		 * Return parent uplink IRQs (towards core intc) 24,25,.....
		 * this step has been done before already
		 * however we need it to get the parent virq and set IDU handler
		 * as first level isr
		 */
		irq = irq_of_parse_and_map(intc, i);
		if (!i)
			idu_first_irq = irq;

		irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
	}

	__mcip_cmd(CMD_IDU_ENABLE, 0);

	return 0;
}
IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
Commit	Line	Data
82fea5a1 VG	1	/*
	2	* ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
	3	*
	4	* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/smp.h>
	12	#include <linux/irq.h>
	13	#include <linux/spinlock.h>
	14	#include <asm/mcip.h>
	15
	16	static char smp_cpuinfo_buf[128];
eaf0ecc3	17	static int idu_detected;
82fea5a1 VG	18
	19	static DEFINE_RAW_SPINLOCK(mcip_lock);
	20
82fea5a1 VG	21	/*
	22	* Any SMP specific init any CPU does when it comes up.
	23	* Here we setup the CPU to enable Inter-Processor-Interrupts
	24	* Called for each CPU
	25	* -Master : init_IRQ()
	26	* -Other(s) : start_kernel_secondary()
	27	*/
	28	void mcip_init_smp(unsigned int cpu)
	29	{
	30	smp_ipi_irq_setup(cpu, IPI_IRQ);
	31	}
	32
	33	static void mcip_ipi_send(int cpu)
	34	{
	35	unsigned long flags;
aa6083ed VG	36	int ipi_was_pending;
	37
	38	/*
	39	* NOTE: We must spin here if the other cpu hasn't yet
	40	* serviced a previous message. This can burn lots
	41	* of time, but we MUST follows this protocol or
	42	* ipi messages can be lost!!!
	43	* Also, we must release the lock in this loop because
	44	* the other side may get to this same loop and not
	45	* be able to ack -- thus causing deadlock.
	46	*/
	47
	48	do {
	49	raw_spin_lock_irqsave(&mcip_lock, flags);
	50	__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
	51	ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
	52	if (ipi_was_pending == 0)
	53	break; /* break out but keep lock */
	54	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	55	} while (1);
82fea5a1	56
82fea5a1 VG	57	__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
82fea5a1 VG	58	raw_spin_unlock_irqrestore(&mcip_lock, flags);
aa6083ed VG	59
	60	#ifdef CONFIG_ARC_IPI_DBG
	61	if (ipi_was_pending)
	62	pr_info("IPI ACK delayed from cpu %d\n", cpu);
	63	#endif
82fea5a1 VG	64	}
	65
	66	static void mcip_ipi_clear(int irq)
	67	{
aa6083ed	68	unsigned int cpu, c;
82fea5a1	69	unsigned long flags;
aa6083ed	70	unsigned int __maybe_unused copy;
82fea5a1 VG	71
	72	raw_spin_lock_irqsave(&mcip_lock, flags);
	73
	74	/* Who sent the IPI */
	75	__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
	76
aa6083ed	77	copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
82fea5a1	78
aa6083ed VG	79	/*
	80	* In rare case, multiple concurrent IPIs sent to same target can
	81	* possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
	82	* "vectored" (multiple bits sets) as opposed to typical single bit
	83	*/
	84	do {
	85	c = __ffs(cpu); /* 0,1,2,3 */
	86	__mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
	87	cpu &= ~(1U << c);
	88	} while (cpu);
82fea5a1 VG	89
82fea5a1 VG	90	raw_spin_unlock_irqrestore(&mcip_lock, flags);
aa6083ed VG	91
	92	#ifdef CONFIG_ARC_IPI_DBG
	93	if (c != __ffs(copy))
	94	pr_info("IPIs from %x coalesced to %x\n",
	95	copy, raw_smp_processor_id());
	96	#endif
82fea5a1 VG	97	}
	98
	99	volatile int wake_flag;
	100
	101	static void mcip_wakeup_cpu(int cpu, unsigned long pc)
	102	{
	103	BUG_ON(cpu == 0);
	104	wake_flag = cpu;
	105	}
	106
	107	void arc_platform_smp_wait_to_boot(int cpu)
	108	{
	109	while (wake_flag != cpu)
	110	;
	111
	112	wake_flag = 0;
	113	__asm__ __volatile__("j @first_lines_of_secondary \n");
	114	}
	115
	116	struct plat_smp_ops plat_smp_ops = {
	117	.info = smp_cpuinfo_buf,
	118	.cpu_kick = mcip_wakeup_cpu,
	119	.ipi_send = mcip_ipi_send,
	120	.ipi_clear = mcip_ipi_clear,
	121	};
	122
	123	void mcip_init_early_smp(void)
	124	{
	125	#define IS_AVAIL1(var, str) ((var) ? str : "")
	126
	127	struct mcip_bcr {
	128	#ifdef CONFIG_CPU_BIG_ENDIAN
	129	unsigned int pad3:8,
	130	idu:1, llm:1, num_cores:6,
	131	iocoh:1, grtc:1, dbg:1, pad2:1,
	132	msg:1, sem:1, ipi:1, pad:1,
	133	ver:8;
	134	#else
	135	unsigned int ver:8,
	136	pad:1, ipi:1, sem:1, msg:1,
	137	pad2:1, dbg:1, grtc:1, iocoh:1,
	138	num_cores:6, llm:1, idu:1,
	139	pad3:8;
	140	#endif
	141	} mp;
	142
	143	READ_BCR(ARC_REG_MCIP_BCR, mp);
	144
	145	sprintf(smp_cpuinfo_buf,
	146	"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
	147	mp.ver, mp.num_cores,
	148	IS_AVAIL1(mp.ipi, "IPI "),
	149	IS_AVAIL1(mp.idu, "IDU "),
	150	IS_AVAIL1(mp.dbg, "DEBUG "),
	151	IS_AVAIL1(mp.grtc, "GRTC"));
	152
eaf0ecc3 VG	153	idu_detected = mp.idu;
eaf0ecc3 VG	154
82fea5a1 VG	155	if (mp.dbg) {
	156	__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
	157	__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
	158	}
72d72880 VG	159
	160	if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
	161	panic("kernel trying to use non-existent GRTC\n");
82fea5a1	162	}
eaf0ecc3 VG	163
	164	/***************************************************************************
	165	* ARCv2 Interrupt Distribution Unit (IDU)
	166	*
	167	* Connects external "COMMON" IRQs to core intc, providing:
	168	* -dynamic routing (IRQ affinity)
	169	* -load balancing (Round Robin interrupt distribution)
	170	* -1:N distribution
	171	*
	172	* It physically resides in the MCIP hw block
	173	*/
	174
	175	#include <linux/irqchip.h>
	176	#include <linux/of.h>
	177	#include <linux/of_irq.h>
eaf0ecc3 VG	178
	179	/*
	180	* Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
	181	*/
	182	static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
	183	{
	184	__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
	185	}
	186
	187	static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
	188	unsigned int distr)
	189	{
	190	union {
	191	unsigned int word;
	192	struct {
	193	unsigned int distr:2, pad:2, lvl:1, pad2:27;
	194	};
	195	} data;
	196
	197	data.distr = distr;
	198	data.lvl = lvl;
	199	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
	200	}
	201
	202	static void idu_irq_mask(struct irq_data *data)
	203	{
	204	unsigned long flags;
	205
	206	raw_spin_lock_irqsave(&mcip_lock, flags);
	207	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
	208	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	209	}
	210
	211	static void idu_irq_unmask(struct irq_data *data)
	212	{
	213	unsigned long flags;
	214
	215	raw_spin_lock_irqsave(&mcip_lock, flags);
	216	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
	217	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	218	}
	219
83ce3e6f	220	#ifdef CONFIG_SMP
eaf0ecc3	221	static int
83ce3e6f VG	222	idu_irq_set_affinity(struct irq_data data, const struct cpumask cpumask,
83ce3e6f VG	223	bool force)
eaf0ecc3	224	{
83ce3e6f VG	225	unsigned long flags;
	226	cpumask_t online;
	227
	228	/* errout if no online cpu per @cpumask */
	229	if (!cpumask_and(&online, cpumask, cpu_online_mask))
	230	return -EINVAL;
	231
	232	raw_spin_lock_irqsave(&mcip_lock, flags);
	233
	234	idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
	235	idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
	236
	237	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	238
eaf0ecc3 VG	239	return IRQ_SET_MASK_OK;
eaf0ecc3 VG	240	}
83ce3e6f	241	#endif
eaf0ecc3 VG	242
	243	static struct irq_chip idu_irq_chip = {
	244	.name = "MCIP IDU Intc",
	245	.irq_mask = idu_irq_mask,
	246	.irq_unmask = idu_irq_unmask,
	247	#ifdef CONFIG_SMP
	248	.irq_set_affinity = idu_irq_set_affinity,
	249	#endif
	250
	251	};
	252
	253	static int idu_first_irq;
	254
bd0b9ac4	255	static void idu_cascade_isr(struct irq_desc *desc)
eaf0ecc3 VG	256	{
eaf0ecc3 VG	257	struct irq_domain *domain = irq_desc_get_handler_data(desc);
badae6bc	258	unsigned int core_irq = irq_desc_get_irq(desc);
eaf0ecc3 VG	259	unsigned int idu_irq;
	260
	261	idu_irq = core_irq - idu_first_irq;
	262	generic_handle_irq(irq_find_mapping(domain, idu_irq));
	263	}
	264
	265	static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
	266	{
	267	irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
	268	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	269
	270	return 0;
	271	}
	272
	273	static int idu_irq_xlate(struct irq_domain d, struct device_node n,
	274	const u32 *intspec, unsigned int intsize,
	275	irq_hw_number_t out_hwirq, unsigned int out_type)
	276	{
	277	irq_hw_number_t hwirq = *out_hwirq = intspec[0];
	278	int distri = intspec[1];
	279	unsigned long flags;
	280
	281	*out_type = IRQ_TYPE_NONE;
	282
	283	/* XXX: validate distribution scheme again online cpu mask */
	284	if (distri == 0) {
	285	/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
	286	raw_spin_lock_irqsave(&mcip_lock, flags);
	287	idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
	288	idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
	289	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	290	} else {
	291	/*
	292	* DEST based distribution for Level Triggered intr can only
	293	* have 1 CPU, so generalize it to always contain 1 cpu
	294	*/
	295	int cpu = ffs(distri);
	296
	297	if (cpu != fls(distri))
	298	pr_warn("IDU irq %lx distri mode set to cpu %x\n",
	299	hwirq, cpu);
	300
	301	raw_spin_lock_irqsave(&mcip_lock, flags);
	302	idu_set_dest(hwirq, cpu);
	303	idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
	304	raw_spin_unlock_irqrestore(&mcip_lock, flags);
	305	}
	306
	307	return 0;
	308	}
	309
	310	static const struct irq_domain_ops idu_irq_ops = {
	311	.xlate = idu_irq_xlate,
	312	.map = idu_irq_map,
	313	};
	314
	315	/*
	316	* [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
	317	* [24, 23+C]: If C > 0 then "C" common IRQs
	318	* [24+C, N]: Not statically assigned, private-per-core
	319	*/
	320
	321
	322	static int __init
323	idu_of_init(struct device_node intc, struct device_node parent)
324	{
325	struct irq_domain *domain;
326	/* Read IDU BCR to confirm nr_irqs */
327	int nr_irqs = of_irq_count(intc);
328	int i, irq;
329
330	if (!idu_detected)
331	panic("IDU not detected, but DeviceTree using it");
332
333	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
334
335	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
336
337	/* Parent interrupts (core-intc) are already mapped */
338
339	for (i = 0; i < nr_irqs; i++) {
340	/*
341	* Return parent uplink IRQs (towards core intc) 24,25,.....
342	* this step has been done before already
343	* however we need it to get the parent virq and set IDU handler
344	* as first level isr
345	*/
346	irq = irq_of_parse_and_map(intc, i);
347	if (!i)
348	idu_first_irq = irq;
349
6b12ec17	350	irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
eaf0ecc3 VG	351	}
	352
	353	__mcip_cmd(CMD_IDU_ENABLE, 0);
	354
	355	return 0;
	356	}
	357	IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);