Commit | Line | Data |
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82fea5a1 VG |
1 | /* |
2 | * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) | |
3 | * | |
4 | * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/smp.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/spinlock.h> | |
bb143f81 | 14 | #include <asm/irqflags-arcv2.h> |
82fea5a1 | 15 | #include <asm/mcip.h> |
964cf28f | 16 | #include <asm/setup.h> |
82fea5a1 | 17 | |
82fea5a1 VG |
18 | static DEFINE_RAW_SPINLOCK(mcip_lock); |
19 | ||
3ce0fefc VG |
20 | #ifdef CONFIG_SMP |
21 | ||
22 | static char smp_cpuinfo_buf[128]; | |
23 | ||
aa0efcde | 24 | static void mcip_setup_per_cpu(int cpu) |
82fea5a1 VG |
25 | { |
26 | smp_ipi_irq_setup(cpu, IPI_IRQ); | |
bb143f81 | 27 | smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); |
82fea5a1 VG |
28 | } |
29 | ||
30 | static void mcip_ipi_send(int cpu) | |
31 | { | |
32 | unsigned long flags; | |
aa6083ed VG |
33 | int ipi_was_pending; |
34 | ||
bb143f81 VG |
35 | /* ARConnect can only send IPI to others */ |
36 | if (unlikely(cpu == raw_smp_processor_id())) { | |
37 | arc_softirq_trigger(SOFTIRQ_IRQ); | |
38 | return; | |
39 | } | |
40 | ||
3dea30ca VG |
41 | raw_spin_lock_irqsave(&mcip_lock, flags); |
42 | ||
aa6083ed | 43 | /* |
3dea30ca VG |
44 | * If receiver already has a pending interrupt, elide sending this one. |
45 | * Linux cross core calling works well with concurrent IPIs | |
46 | * coalesced into one | |
47 | * see arch/arc/kernel/smp.c: ipi_send_msg_one() | |
aa6083ed | 48 | */ |
3dea30ca VG |
49 | __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); |
50 | ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); | |
51 | if (!ipi_was_pending) | |
52 | __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); | |
aa6083ed | 53 | |
82fea5a1 VG |
54 | raw_spin_unlock_irqrestore(&mcip_lock, flags); |
55 | } | |
56 | ||
57 | static void mcip_ipi_clear(int irq) | |
58 | { | |
aa6083ed | 59 | unsigned int cpu, c; |
82fea5a1 VG |
60 | unsigned long flags; |
61 | ||
bb143f81 VG |
62 | if (unlikely(irq == SOFTIRQ_IRQ)) { |
63 | arc_softirq_clear(irq); | |
64 | return; | |
65 | } | |
66 | ||
82fea5a1 VG |
67 | raw_spin_lock_irqsave(&mcip_lock, flags); |
68 | ||
69 | /* Who sent the IPI */ | |
70 | __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); | |
71 | ||
d73b73f5 | 72 | cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ |
82fea5a1 | 73 | |
aa6083ed VG |
74 | /* |
75 | * In rare case, multiple concurrent IPIs sent to same target can | |
76 | * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be | |
77 | * "vectored" (multiple bits sets) as opposed to typical single bit | |
78 | */ | |
79 | do { | |
80 | c = __ffs(cpu); /* 0,1,2,3 */ | |
81 | __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); | |
82 | cpu &= ~(1U << c); | |
83 | } while (cpu); | |
82fea5a1 VG |
84 | |
85 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
86 | } | |
87 | ||
26b8f996 | 88 | static void mcip_probe_n_setup(void) |
82fea5a1 | 89 | { |
3ce0fefc | 90 | struct mcip_bcr mp; |
82fea5a1 VG |
91 | |
92 | READ_BCR(ARC_REG_MCIP_BCR, mp); | |
93 | ||
94 | sprintf(smp_cpuinfo_buf, | |
98341f7d | 95 | "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n", |
82fea5a1 VG |
96 | mp.ver, mp.num_cores, |
97 | IS_AVAIL1(mp.ipi, "IPI "), | |
98 | IS_AVAIL1(mp.idu, "IDU "), | |
98341f7d | 99 | IS_AVAIL1(mp.llm, "LLM "), |
82fea5a1 | 100 | IS_AVAIL1(mp.dbg, "DEBUG "), |
d584f0fb | 101 | IS_AVAIL1(mp.gfrc, "GFRC")); |
82fea5a1 | 102 | |
e608b53e | 103 | cpuinfo_arc700[0].extn.gfrc = mp.gfrc; |
eaf0ecc3 | 104 | |
82fea5a1 VG |
105 | if (mp.dbg) { |
106 | __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); | |
107 | __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); | |
108 | } | |
109 | } | |
eaf0ecc3 | 110 | |
26b8f996 VG |
111 | struct plat_smp_ops plat_smp_ops = { |
112 | .info = smp_cpuinfo_buf, | |
113 | .init_early_smp = mcip_probe_n_setup, | |
b474a023 | 114 | .init_per_cpu = mcip_setup_per_cpu, |
26b8f996 VG |
115 | .ipi_send = mcip_ipi_send, |
116 | .ipi_clear = mcip_ipi_clear, | |
117 | }; | |
118 | ||
3ce0fefc VG |
119 | #endif |
120 | ||
eaf0ecc3 VG |
121 | /*************************************************************************** |
122 | * ARCv2 Interrupt Distribution Unit (IDU) | |
123 | * | |
124 | * Connects external "COMMON" IRQs to core intc, providing: | |
125 | * -dynamic routing (IRQ affinity) | |
126 | * -load balancing (Round Robin interrupt distribution) | |
127 | * -1:N distribution | |
128 | * | |
129 | * It physically resides in the MCIP hw block | |
130 | */ | |
131 | ||
132 | #include <linux/irqchip.h> | |
133 | #include <linux/of.h> | |
134 | #include <linux/of_irq.h> | |
eaf0ecc3 VG |
135 | |
136 | /* | |
137 | * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) | |
138 | */ | |
139 | static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) | |
140 | { | |
141 | __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); | |
142 | } | |
143 | ||
144 | static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, | |
145 | unsigned int distr) | |
146 | { | |
147 | union { | |
148 | unsigned int word; | |
149 | struct { | |
150 | unsigned int distr:2, pad:2, lvl:1, pad2:27; | |
151 | }; | |
152 | } data; | |
153 | ||
154 | data.distr = distr; | |
155 | data.lvl = lvl; | |
156 | __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); | |
157 | } | |
158 | ||
159 | static void idu_irq_mask(struct irq_data *data) | |
160 | { | |
161 | unsigned long flags; | |
162 | ||
163 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
164 | __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); | |
165 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
166 | } | |
167 | ||
168 | static void idu_irq_unmask(struct irq_data *data) | |
169 | { | |
170 | unsigned long flags; | |
171 | ||
172 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
173 | __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); | |
174 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
175 | } | |
176 | ||
83ce3e6f | 177 | #ifdef CONFIG_SMP |
eaf0ecc3 | 178 | static int |
83ce3e6f VG |
179 | idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, |
180 | bool force) | |
eaf0ecc3 | 181 | { |
83ce3e6f VG |
182 | unsigned long flags; |
183 | cpumask_t online; | |
184 | ||
185 | /* errout if no online cpu per @cpumask */ | |
186 | if (!cpumask_and(&online, cpumask, cpu_online_mask)) | |
187 | return -EINVAL; | |
188 | ||
189 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
190 | ||
191 | idu_set_dest(data->hwirq, cpumask_bits(&online)[0]); | |
192 | idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); | |
193 | ||
194 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
195 | ||
eaf0ecc3 VG |
196 | return IRQ_SET_MASK_OK; |
197 | } | |
83ce3e6f | 198 | #endif |
eaf0ecc3 VG |
199 | |
200 | static struct irq_chip idu_irq_chip = { | |
201 | .name = "MCIP IDU Intc", | |
202 | .irq_mask = idu_irq_mask, | |
203 | .irq_unmask = idu_irq_unmask, | |
204 | #ifdef CONFIG_SMP | |
205 | .irq_set_affinity = idu_irq_set_affinity, | |
206 | #endif | |
207 | ||
208 | }; | |
209 | ||
210 | static int idu_first_irq; | |
211 | ||
bd0b9ac4 | 212 | static void idu_cascade_isr(struct irq_desc *desc) |
eaf0ecc3 VG |
213 | { |
214 | struct irq_domain *domain = irq_desc_get_handler_data(desc); | |
badae6bc | 215 | unsigned int core_irq = irq_desc_get_irq(desc); |
eaf0ecc3 VG |
216 | unsigned int idu_irq; |
217 | ||
218 | idu_irq = core_irq - idu_first_irq; | |
219 | generic_handle_irq(irq_find_mapping(domain, idu_irq)); | |
220 | } | |
221 | ||
222 | static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) | |
223 | { | |
224 | irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); | |
225 | irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, | |
231 | const u32 *intspec, unsigned int intsize, | |
232 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | |
233 | { | |
234 | irq_hw_number_t hwirq = *out_hwirq = intspec[0]; | |
235 | int distri = intspec[1]; | |
236 | unsigned long flags; | |
237 | ||
238 | *out_type = IRQ_TYPE_NONE; | |
239 | ||
240 | /* XXX: validate distribution scheme again online cpu mask */ | |
241 | if (distri == 0) { | |
242 | /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ | |
243 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
244 | idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); | |
245 | idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); | |
246 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
247 | } else { | |
248 | /* | |
249 | * DEST based distribution for Level Triggered intr can only | |
250 | * have 1 CPU, so generalize it to always contain 1 cpu | |
251 | */ | |
252 | int cpu = ffs(distri); | |
253 | ||
254 | if (cpu != fls(distri)) | |
255 | pr_warn("IDU irq %lx distri mode set to cpu %x\n", | |
256 | hwirq, cpu); | |
257 | ||
258 | raw_spin_lock_irqsave(&mcip_lock, flags); | |
259 | idu_set_dest(hwirq, cpu); | |
260 | idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); | |
261 | raw_spin_unlock_irqrestore(&mcip_lock, flags); | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static const struct irq_domain_ops idu_irq_ops = { | |
268 | .xlate = idu_irq_xlate, | |
269 | .map = idu_irq_map, | |
270 | }; | |
271 | ||
272 | /* | |
273 | * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) | |
274 | * [24, 23+C]: If C > 0 then "C" common IRQs | |
275 | * [24+C, N]: Not statically assigned, private-per-core | |
276 | */ | |
277 | ||
278 | ||
279 | static int __init | |
280 | idu_of_init(struct device_node *intc, struct device_node *parent) | |
281 | { | |
282 | struct irq_domain *domain; | |
283 | /* Read IDU BCR to confirm nr_irqs */ | |
284 | int nr_irqs = of_irq_count(intc); | |
285 | int i, irq; | |
3ce0fefc VG |
286 | struct mcip_bcr mp; |
287 | ||
288 | READ_BCR(ARC_REG_MCIP_BCR, mp); | |
eaf0ecc3 | 289 | |
3ce0fefc | 290 | if (!mp.idu) |
eaf0ecc3 VG |
291 | panic("IDU not detected, but DeviceTree using it"); |
292 | ||
293 | pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); | |
294 | ||
295 | domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); | |
296 | ||
297 | /* Parent interrupts (core-intc) are already mapped */ | |
298 | ||
299 | for (i = 0; i < nr_irqs; i++) { | |
300 | /* | |
301 | * Return parent uplink IRQs (towards core intc) 24,25,..... | |
302 | * this step has been done before already | |
303 | * however we need it to get the parent virq and set IDU handler | |
304 | * as first level isr | |
305 | */ | |
306 | irq = irq_of_parse_and_map(intc, i); | |
307 | if (!i) | |
308 | idu_first_irq = irq; | |
309 | ||
6b12ec17 | 310 | irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain); |
eaf0ecc3 VG |
311 | } |
312 | ||
313 | __mcip_cmd(CMD_IDU_ENABLE, 0); | |
314 | ||
315 | return 0; | |
316 | } | |
317 | IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); |