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5793e273 VG |
1 | /* |
2 | * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/interrupt.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/irqdomain.h> | |
14 | #include <linux/irqchip.h> | |
5793e273 VG |
15 | #include <asm/irq.h> |
16 | ||
17 | /* | |
18 | * Early Hardware specific Interrupt setup | |
19 | * -Platform independent, needed for each CPU (not foldable into init_IRQ) | |
20 | * -Called very early (start_kernel -> setup_arch -> setup_processor) | |
21 | * | |
22 | * what it does ? | |
23 | * -Optionally, setup the High priority Interrupts as Level 2 IRQs | |
24 | */ | |
25 | void arc_init_IRQ(void) | |
26 | { | |
27 | int level_mask = 0; | |
28 | ||
29 | /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ | |
30 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; | |
31 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; | |
32 | level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; | |
33 | ||
34 | /* | |
35 | * Write to register, even if no LV2 IRQs configured to reset it | |
36 | * in case bootloader had mucked with it | |
37 | */ | |
38 | write_aux_reg(AUX_IRQ_LEV, level_mask); | |
39 | ||
40 | if (level_mask) | |
41 | pr_info("Level-2 interrupts bitset %x\n", level_mask); | |
42 | } | |
43 | ||
44 | /* | |
45 | * ARC700 core includes a simple on-chip intc supporting | |
46 | * -per IRQ enable/disable | |
47 | * -2 levels of interrupts (high/low) | |
48 | * -all interrupts being level triggered | |
49 | * | |
50 | * To reduce platform code, we assume all IRQs directly hooked-up into intc. | |
51 | * Platforms with external intc, hence cascaded IRQs, are free to over-ride | |
52 | * below, per IRQ. | |
53 | */ | |
54 | ||
55 | static void arc_irq_mask(struct irq_data *data) | |
56 | { | |
57 | unsigned int ienb; | |
58 | ||
59 | ienb = read_aux_reg(AUX_IENABLE); | |
60 | ienb &= ~(1 << data->irq); | |
61 | write_aux_reg(AUX_IENABLE, ienb); | |
62 | } | |
63 | ||
64 | static void arc_irq_unmask(struct irq_data *data) | |
65 | { | |
66 | unsigned int ienb; | |
67 | ||
68 | ienb = read_aux_reg(AUX_IENABLE); | |
69 | ienb |= (1 << data->irq); | |
70 | write_aux_reg(AUX_IENABLE, ienb); | |
71 | } | |
72 | ||
73 | static struct irq_chip onchip_intc = { | |
74 | .name = "ARC In-core Intc", | |
75 | .irq_mask = arc_irq_mask, | |
76 | .irq_unmask = arc_irq_unmask, | |
77 | }; | |
78 | ||
79 | static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, | |
80 | irq_hw_number_t hw) | |
81 | { | |
e0868e6f VG |
82 | switch (irq) { |
83 | case TIMER0_IRQ: | |
5793e273 | 84 | irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); |
e0868e6f VG |
85 | break; |
86 | default: | |
5793e273 | 87 | irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); |
e0868e6f | 88 | } |
5793e273 VG |
89 | return 0; |
90 | } | |
91 | ||
92 | static const struct irq_domain_ops arc_intc_domain_ops = { | |
93 | .xlate = irq_domain_xlate_onecell, | |
94 | .map = arc_intc_domain_map, | |
95 | }; | |
96 | ||
97 | static struct irq_domain *root_domain; | |
98 | ||
99 | static int __init | |
100 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) | |
101 | { | |
102 | if (parent) | |
103 | panic("DeviceTree incore intc not a root irq controller\n"); | |
104 | ||
105 | root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, | |
106 | &arc_intc_domain_ops, NULL); | |
107 | ||
108 | if (!root_domain) | |
109 | panic("root irq domain not avail\n"); | |
110 | ||
111 | /* with this we don't need to export root_domain */ | |
112 | irq_set_default_host(root_domain); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); | |
118 | ||
119 | /* | |
120 | * arch_local_irq_enable - Enable interrupts. | |
121 | * | |
122 | * 1. Explicitly called to re-enable interrupts | |
123 | * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc | |
124 | * which maybe in hard ISR itself | |
125 | * | |
126 | * Semantics of this function change depending on where it is called from: | |
127 | * | |
128 | * -If called from hard-ISR, it must not invert interrupt priorities | |
129 | * e.g. suppose TIMER is high priority (Level 2) IRQ | |
130 | * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. | |
131 | * Here local_irq_enable( ) shd not re-enable lower priority interrupts | |
132 | * -If called from soft-ISR, it must re-enable all interrupts | |
133 | * soft ISR are low prioity jobs which can be very slow, thus all IRQs | |
134 | * must be enabled while they run. | |
135 | * Now hardware context wise we may still be in L2 ISR (not done rtie) | |
136 | * still we must re-enable both L1 and L2 IRQs | |
137 | * Another twist is prev scenario with flow being | |
138 | * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR | |
139 | * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get | |
140 | * over-written (this is deficiency in ARC700 Interrupt mechanism) | |
141 | */ | |
142 | ||
143 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ | |
144 | ||
145 | void arch_local_irq_enable(void) | |
146 | { | |
5793e273 VG |
147 | unsigned long flags = arch_local_save_flags(); |
148 | ||
9dbd3d9b VG |
149 | if (flags & STATUS_A2_MASK) |
150 | flags |= STATUS_E2_MASK; | |
151 | else if (flags & STATUS_A1_MASK) | |
152 | flags |= STATUS_E1_MASK; | |
5793e273 VG |
153 | |
154 | arch_local_irq_restore(flags); | |
155 | } | |
156 | ||
5793e273 | 157 | EXPORT_SYMBOL(arch_local_irq_enable); |
9dbd3d9b | 158 | #endif |