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1 | /* |
2 | * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/interrupt.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/irqdomain.h> | |
14 | #include <linux/irqchip.h> | |
820970a5 VG |
15 | #include <asm/irq.h> |
16 | ||
dec2b284 VG |
17 | static int irq_prio; |
18 | ||
820970a5 VG |
19 | /* |
20 | * Early Hardware specific Interrupt setup | |
21 | * -Called very early (start_kernel -> setup_arch -> setup_processor) | |
22 | * -Platform Independent (must for any ARC Core) | |
23 | * -Needed for each CPU (hence not foldable into init_IRQ) | |
24 | */ | |
25 | void arc_init_IRQ(void) | |
26 | { | |
27 | unsigned int tmp; | |
28 | ||
dec2b284 VG |
29 | struct irq_build { |
30 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
31 | unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; | |
32 | #else | |
33 | unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3; | |
34 | #endif | |
35 | } irq_bcr; | |
36 | ||
820970a5 VG |
37 | struct aux_irq_ctrl { |
38 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
39 | unsigned int res3:18, save_idx_regs:1, res2:1, | |
40 | save_u_to_u:1, save_lp_regs:1, save_blink:1, | |
41 | res:4, save_nr_gpr_pairs:5; | |
42 | #else | |
43 | unsigned int save_nr_gpr_pairs:5, res:4, | |
44 | save_blink:1, save_lp_regs:1, save_u_to_u:1, | |
45 | res2:1, save_idx_regs:1, res3:18; | |
46 | #endif | |
47 | } ictrl; | |
48 | ||
49 | *(unsigned int *)&ictrl = 0; | |
50 | ||
51 | ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ | |
52 | ictrl.save_blink = 1; | |
53 | ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ | |
54 | ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ | |
55 | ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ | |
56 | ||
57 | WRITE_AUX(AUX_IRQ_CTRL, ictrl); | |
58 | ||
820970a5 VG |
59 | /* |
60 | * ARCv2 core intc provides multiple interrupt priorities (upto 16). | |
61 | * Typical builds though have only two levels (0-high, 1-low) | |
62 | * Linux by default uses lower prio 1 for most irqs, reserving 0 for | |
63 | * NMI style interrupts in future (say perf) | |
820970a5 | 64 | */ |
dec2b284 VG |
65 | |
66 | READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); | |
67 | ||
68 | irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ | |
69 | pr_info("archs-intc\t: %d priority levels (default %d)%s\n", | |
70 | irq_prio + 1, irq_prio, | |
71 | irq_bcr.firq ? " FIRQ (not used)":""); | |
72 | ||
73 | /* setup status32, don't enable intr yet as kernel doesn't want */ | |
74 | tmp = read_aux_reg(0xa); | |
75 | tmp |= STATUS_AD_MASK | (irq_prio << 1); | |
76 | tmp &= ~STATUS_IE_MASK; | |
bc0c7ece | 77 | asm volatile("kflag %0 \n"::"r"(tmp)); |
820970a5 VG |
78 | } |
79 | ||
80 | static void arcv2_irq_mask(struct irq_data *data) | |
81 | { | |
82 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
83 | write_aux_reg(AUX_IRQ_ENABLE, 0); | |
84 | } | |
85 | ||
86 | static void arcv2_irq_unmask(struct irq_data *data) | |
87 | { | |
88 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
89 | write_aux_reg(AUX_IRQ_ENABLE, 1); | |
90 | } | |
91 | ||
92 | void arcv2_irq_enable(struct irq_data *data) | |
93 | { | |
94 | /* set default priority */ | |
95 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
dec2b284 | 96 | write_aux_reg(AUX_IRQ_PRIORITY, irq_prio); |
820970a5 VG |
97 | |
98 | /* | |
99 | * hw auto enables (linux unmask) all by default | |
100 | * So no need to do IRQ_ENABLE here | |
101 | * XXX: However OSCI LAN need it | |
102 | */ | |
103 | write_aux_reg(AUX_IRQ_ENABLE, 1); | |
104 | } | |
105 | ||
106 | static struct irq_chip arcv2_irq_chip = { | |
107 | .name = "ARCv2 core Intc", | |
108 | .irq_mask = arcv2_irq_mask, | |
109 | .irq_unmask = arcv2_irq_unmask, | |
110 | .irq_enable = arcv2_irq_enable | |
111 | }; | |
112 | ||
113 | static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, | |
114 | irq_hw_number_t hw) | |
115 | { | |
8eb0984b VG |
116 | /* |
117 | * core intc IRQs [16, 23]: | |
118 | * Statically assigned always private-per-core (Timers, WDT, IPI, PCT) | |
119 | */ | |
120 | if (hw < 24) { | |
121 | /* | |
122 | * A subsequent request_percpu_irq() fails if percpu_devid is | |
123 | * not set. That in turns sets NOAUTOEN, meaning each core needs | |
124 | * to call enable_percpu_irq() | |
125 | */ | |
126 | irq_set_percpu_devid(irq); | |
820970a5 | 127 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); |
8eb0984b | 128 | } else { |
820970a5 | 129 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); |
8eb0984b | 130 | } |
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131 | |
132 | return 0; | |
133 | } | |
134 | ||
135 | static const struct irq_domain_ops arcv2_irq_ops = { | |
136 | .xlate = irq_domain_xlate_onecell, | |
137 | .map = arcv2_irq_map, | |
138 | }; | |
139 | ||
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140 | |
141 | static int __init | |
142 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) | |
143 | { | |
1b0ccb8a VG |
144 | struct irq_domain *root_domain; |
145 | ||
820970a5 VG |
146 | if (parent) |
147 | panic("DeviceTree incore intc not a root irq controller\n"); | |
148 | ||
d21beffb | 149 | root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL); |
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150 | if (!root_domain) |
151 | panic("root irq domain not avail\n"); | |
152 | ||
1b0ccb8a VG |
153 | /* |
154 | * Needed for primary domain lookup to succeed | |
155 | * This is a primary irqchip, and can never have a parent | |
156 | */ | |
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157 | irq_set_default_host(root_domain); |
158 | ||
d21beffb VG |
159 | #ifdef CONFIG_SMP |
160 | irq_create_mapping(root_domain, IPI_IRQ); | |
161 | #endif | |
162 | irq_create_mapping(root_domain, SOFTIRQ_IRQ); | |
163 | ||
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164 | return 0; |
165 | } | |
166 | ||
167 | IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); |