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820970a5 VG |
1 | /* |
2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_IRQFLAGS_ARCV2_H | |
10 | #define __ASM_IRQFLAGS_ARCV2_H | |
11 | ||
12 | #include <asm/arcregs.h> | |
13 | ||
14 | /* status32 Bits */ | |
15 | #define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */ | |
16 | #define STATUS_IE_BIT 31 | |
17 | ||
18 | #define STATUS_AD_MASK (1<<STATUS_AD_BIT) | |
19 | #define STATUS_IE_MASK (1<<STATUS_IE_BIT) | |
20 | ||
d9676fa1 EV |
21 | /* status32 Bits as encoded/expected by CLRI/SETI */ |
22 | #define CLRI_STATUS_IE_BIT 4 | |
23 | ||
24 | #define CLRI_STATUS_E_MASK 0xF | |
25 | #define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT) | |
26 | ||
820970a5 VG |
27 | #define AUX_USER_SP 0x00D |
28 | #define AUX_IRQ_CTRL 0x00E | |
29 | #define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */ | |
30 | #define AUX_IRQ_LVL_PEND 0x200 /* Pending Intr across all levels */ | |
bb143f81 | 31 | #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ |
820970a5 VG |
32 | #define AUX_IRQ_PRIORITY 0x206 |
33 | #define ICAUSE 0x40a | |
34 | #define AUX_IRQ_SELECT 0x40b | |
35 | #define AUX_IRQ_ENABLE 0x40c | |
36 | ||
1f6ccfff VG |
37 | /* Was Intr taken in User Mode */ |
38 | #define AUX_IRQ_ACT_BIT_U 31 | |
39 | ||
dec2b284 | 40 | /* |
107177b1 VG |
41 | * Hardware supports 16 priorities (0 highest, 15 lowest) |
42 | * Linux by default runs at 1, priority 0 reserved for NMI style interrupts | |
dec2b284 | 43 | */ |
107177b1 | 44 | #define ARCV2_IRQ_DEF_PRIO 1 |
820970a5 VG |
45 | |
46 | /* seed value for status register */ | |
76551468 EP |
47 | #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS |
48 | #define __AD_ENB STATUS_AD_MASK | |
49 | #else | |
50 | #define __AD_ENB 0 | |
51 | #endif | |
52 | ||
53 | #define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | __AD_ENB | \ | |
820970a5 VG |
54 | (ARCV2_IRQ_DEF_PRIO << 1)) |
55 | ||
56 | #ifndef __ASSEMBLY__ | |
57 | ||
58 | /* | |
59 | * Save IRQ state and disable IRQs | |
60 | */ | |
61 | static inline long arch_local_irq_save(void) | |
62 | { | |
63 | unsigned long flags; | |
64 | ||
65 | __asm__ __volatile__(" clri %0 \n" : "=r" (flags) : : "memory"); | |
66 | ||
67 | return flags; | |
68 | } | |
69 | ||
70 | /* | |
71 | * restore saved IRQ state | |
72 | */ | |
73 | static inline void arch_local_irq_restore(unsigned long flags) | |
74 | { | |
75 | __asm__ __volatile__(" seti %0 \n" : : "r" (flags) : "memory"); | |
76 | } | |
77 | ||
78 | /* | |
79 | * Unconditionally Enable IRQs | |
80 | */ | |
81 | static inline void arch_local_irq_enable(void) | |
82 | { | |
4de0e528 VG |
83 | unsigned int irqact = read_aux_reg(AUX_IRQ_ACT); |
84 | ||
85 | if (irqact & 0xffff) | |
86 | write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff); | |
87 | ||
820970a5 VG |
88 | __asm__ __volatile__(" seti \n" : : : "memory"); |
89 | } | |
90 | ||
91 | /* | |
92 | * Unconditionally Disable IRQs | |
93 | */ | |
94 | static inline void arch_local_irq_disable(void) | |
95 | { | |
96 | __asm__ __volatile__(" clri \n" : : : "memory"); | |
97 | } | |
98 | ||
99 | /* | |
100 | * save IRQ state | |
101 | */ | |
102 | static inline long arch_local_save_flags(void) | |
103 | { | |
104 | unsigned long temp; | |
105 | ||
106 | __asm__ __volatile__( | |
107 | " lr %0, [status32] \n" | |
108 | : "=&r"(temp) | |
109 | : | |
110 | : "memory"); | |
111 | ||
d9676fa1 EV |
112 | /* To be compatible with irq_save()/irq_restore() |
113 | * encode the irq bits as expected by CLRI/SETI | |
114 | * (this was needed to make CONFIG_TRACE_IRQFLAGS work) | |
115 | */ | |
116 | temp = (1 << 5) | | |
117 | ((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) | | |
cd5d38b0 | 118 | ((temp >> 1) & CLRI_STATUS_E_MASK); |
820970a5 VG |
119 | return temp; |
120 | } | |
121 | ||
122 | /* | |
123 | * Query IRQ state | |
124 | */ | |
125 | static inline int arch_irqs_disabled_flags(unsigned long flags) | |
126 | { | |
d9676fa1 | 127 | return !(flags & CLRI_STATUS_IE_MASK); |
820970a5 VG |
128 | } |
129 | ||
130 | static inline int arch_irqs_disabled(void) | |
131 | { | |
132 | return arch_irqs_disabled_flags(arch_local_save_flags()); | |
133 | } | |
134 | ||
bb143f81 VG |
135 | static inline void arc_softirq_trigger(int irq) |
136 | { | |
137 | write_aux_reg(AUX_IRQ_HINT, irq); | |
138 | } | |
139 | ||
140 | static inline void arc_softirq_clear(int irq) | |
141 | { | |
142 | write_aux_reg(AUX_IRQ_HINT, 0); | |
143 | } | |
144 | ||
820970a5 VG |
145 | #else |
146 | ||
d9676fa1 EV |
147 | #ifdef CONFIG_TRACE_IRQFLAGS |
148 | ||
149 | .macro TRACE_ASM_IRQ_DISABLE | |
150 | bl trace_hardirqs_off | |
151 | .endm | |
152 | ||
153 | .macro TRACE_ASM_IRQ_ENABLE | |
154 | bl trace_hardirqs_on | |
155 | .endm | |
156 | ||
157 | #else | |
158 | ||
159 | .macro TRACE_ASM_IRQ_DISABLE | |
160 | .endm | |
161 | ||
162 | .macro TRACE_ASM_IRQ_ENABLE | |
163 | .endm | |
164 | ||
165 | #endif | |
820970a5 VG |
166 | .macro IRQ_DISABLE scratch |
167 | clri | |
d9676fa1 | 168 | TRACE_ASM_IRQ_DISABLE |
820970a5 VG |
169 | .endm |
170 | ||
171 | .macro IRQ_ENABLE scratch | |
d9676fa1 | 172 | TRACE_ASM_IRQ_ENABLE |
820970a5 VG |
173 | seti |
174 | .endm | |
175 | ||
176 | #endif /* __ASSEMBLY__ */ | |
177 | ||
178 | #endif |