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1 | /* |
2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
3 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Vineetg: March 2009 (Supporting 2 levels of Interrupts) | |
10 | * Stack switching code can no longer reliably rely on the fact that | |
11 | * if we are NOT in user mode, stack is switched to kernel mode. | |
12 | * e.g. L2 IRQ interrupted a L1 ISR which had not yet completed | |
13 | * it's prologue including stack switching from user mode | |
14 | * | |
15 | * Vineetg: Aug 28th 2008: Bug #94984 | |
16 | * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap | |
17 | * Normally CPU does this automatically, however when doing FAKE rtie, | |
18 | * we also need to explicitly do this. The problem in macros | |
19 | * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit | |
20 | * was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context | |
21 | * | |
22 | * Vineetg: May 5th 2008 | |
23 | * -Modified CALLEE_REG save/restore macros to handle the fact that | |
24 | * r25 contains the kernel current task ptr | |
25 | * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs | |
26 | * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the | |
27 | * address Write back load ld.ab instead of seperate ld/add instn | |
28 | * | |
29 | * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 | |
30 | */ | |
31 | ||
32 | #ifndef __ASM_ARC_ENTRY_COMPACT_H | |
33 | #define __ASM_ARC_ENTRY_COMPACT_H | |
34 | ||
35 | #include <asm/asm-offsets.h> | |
5793e273 | 36 | #include <asm/irqflags-compact.h> |
6d1a20b1 VG |
37 | #include <asm/thread_info.h> /* For THREAD_SIZE */ |
38 | ||
86c25466 NC |
39 | #ifdef CONFIG_ARC_PLAT_EZNPS |
40 | #include <plat/ctop.h> | |
41 | #endif | |
42 | ||
6d1a20b1 VG |
43 | /*-------------------------------------------------------------- |
44 | * Switch to Kernel Mode stack if SP points to User Mode stack | |
45 | * | |
46 | * Entry : r9 contains pre-IRQ/exception/trap status32 | |
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47 | * Exit : SP set to K mode stack |
48 | * SP at the time of entry (K/U) saved @ pt_regs->sp | |
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49 | * Clobbers: r9 |
50 | *-------------------------------------------------------------*/ | |
51 | ||
52 | .macro SWITCH_TO_KERNEL_STK | |
53 | ||
54 | /* User Mode when this happened ? Yes: Proceed to switch stack */ | |
55 | bbit1 r9, STATUS_U_BIT, 88f | |
56 | ||
57 | /* OK we were already in kernel mode when this event happened, thus can | |
58 | * assume SP is kernel mode SP. _NO_ need to do any stack switching | |
59 | */ | |
60 | ||
61 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS | |
62 | /* However.... | |
63 | * If Level 2 Interrupts enabled, we may end up with a corner case: | |
64 | * 1. User Task executing | |
65 | * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode) | |
66 | * 3. But before it could switch SP from USER to KERNEL stack | |
67 | * a L2 IRQ "Interrupts" L1 | |
68 | * Thay way although L2 IRQ happened in Kernel mode, stack is still | |
69 | * not switched. | |
70 | * To handle this, we may need to switch stack even if in kernel mode | |
71 | * provided SP has values in range of USER mode stack ( < 0x7000_0000 ) | |
72 | */ | |
73 | brlo sp, VMALLOC_START, 88f | |
74 | ||
75 | /* TODO: vineetg: | |
76 | * We need to be a bit more cautious here. What if a kernel bug in | |
77 | * L1 ISR, caused SP to go whaco (some small value which looks like | |
78 | * USER stk) and then we take L2 ISR. | |
2547476a AG |
79 | * Above brlo alone would treat it as a valid L1-L2 scenario |
80 | * instead of shouting around | |
6d1a20b1 VG |
81 | * The only feasible way is to make sure this L2 happened in |
82 | * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in | |
83 | * L1 ISR before it switches stack | |
84 | */ | |
85 | ||
86 | #endif | |
87 | ||
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88 | /*------Intr/Ecxp happened in kernel mode, SP already setup ------ */ |
89 | /* save it nevertheless @ pt_regs->sp for uniformity */ | |
90 | ||
6d1a20b1 | 91 | b.d 66f |
5a343b9f | 92 | st sp, [sp, PT_sp - SZ_PT_REGS] |
6d1a20b1 VG |
93 | |
94 | 88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */ | |
95 | ||
96 | GET_CURR_TASK_ON_CPU r9 | |
97 | ||
98 | /* With current tsk in r9, get it's kernel mode stack base */ | |
99 | GET_TSK_STACK_BASE r9, r9 | |
100 | ||
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101 | /* save U mode SP @ pt_regs->sp */ |
102 | st sp, [r9, PT_sp - SZ_PT_REGS] | |
6d1a20b1 | 103 | |
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104 | /* final SP switch */ |
105 | mov sp, r9 | |
106 | 66: | |
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107 | .endm |
108 | ||
109 | /*------------------------------------------------------------ | |
110 | * "FAKE" a rtie to return from CPU Exception context | |
111 | * This is to re-enable Exceptions within exception | |
112 | * Look at EV_ProtV to see how this is actually used | |
113 | *-------------------------------------------------------------*/ | |
114 | ||
115 | .macro FAKE_RET_FROM_EXCPN | |
116 | ||
55a2ae77 VG |
117 | lr r9, [status32] |
118 | bclr r9, r9, STATUS_AE_BIT | |
119 | or r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK) | |
120 | sr r9, [erstatus] | |
121 | mov r9, 55f | |
122 | sr r9, [eret] | |
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123 | rtie |
124 | 55: | |
125 | .endm | |
126 | ||
127 | /*-------------------------------------------------------------- | |
128 | * For early Exception/ISR Prologue, a core reg is temporarily needed to | |
129 | * code the rest of prolog (stack switching). This is done by stashing | |
130 | * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP). | |
131 | * | |
132 | * Before saving the full regfile - this reg is restored back, only | |
133 | * to be saved again on kernel mode stack, as part of pt_regs. | |
134 | *-------------------------------------------------------------*/ | |
135 | .macro PROLOG_FREEUP_REG reg, mem | |
136 | #ifdef CONFIG_SMP | |
137 | sr \reg, [ARC_REG_SCRATCH_DATA0] | |
138 | #else | |
139 | st \reg, [\mem] | |
140 | #endif | |
141 | .endm | |
142 | ||
143 | .macro PROLOG_RESTORE_REG reg, mem | |
144 | #ifdef CONFIG_SMP | |
145 | lr \reg, [ARC_REG_SCRATCH_DATA0] | |
146 | #else | |
147 | ld \reg, [\mem] | |
148 | #endif | |
149 | .endm | |
150 | ||
151 | /*-------------------------------------------------------------- | |
152 | * Exception Entry prologue | |
153 | * -Switches stack to K mode (if not already) | |
154 | * -Saves the register file | |
155 | * | |
156 | * After this it is safe to call the "C" handlers | |
157 | *-------------------------------------------------------------*/ | |
158 | .macro EXCEPTION_PROLOGUE | |
159 | ||
160 | /* Need at least 1 reg to code the early exception prologue */ | |
161 | PROLOG_FREEUP_REG r9, @ex_saved_reg1 | |
162 | ||
163 | /* U/K mode at time of exception (stack not switched if already K) */ | |
164 | lr r9, [erstatus] | |
165 | ||
166 | /* ARC700 doesn't provide auto-stack switching */ | |
167 | SWITCH_TO_KERNEL_STK | |
168 | ||
5a343b9f VG |
169 | #ifdef CONFIG_ARC_CURR_IN_REG |
170 | /* Treat r25 as scratch reg (save on stack) and load with "current" */ | |
171 | PUSH r25 | |
172 | GET_CURR_TASK_ON_CPU r25 | |
173 | #else | |
174 | sub sp, sp, 4 | |
175 | #endif | |
176 | ||
177 | st.a r0, [sp, -8] /* orig_r0 needed for syscall (skip ECR slot) */ | |
178 | sub sp, sp, 4 /* skip pt_regs->sp, already saved above */ | |
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179 | |
180 | /* Restore r9 used to code the early prologue */ | |
181 | PROLOG_RESTORE_REG r9, @ex_saved_reg1 | |
182 | ||
5a343b9f | 183 | /* now we are ready to save the regfile */ |
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184 | SAVE_R0_TO_R12 |
185 | PUSH gp | |
186 | PUSH fp | |
187 | PUSH blink | |
188 | PUSHAX eret | |
189 | PUSHAX erstatus | |
190 | PUSH lp_count | |
191 | PUSHAX lp_end | |
192 | PUSHAX lp_start | |
193 | PUSHAX erbta | |
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194 | |
195 | lr r9, [ecr] | |
196 | st r9, [sp, PT_event] /* EV_Trap expects r9 to have ECR */ | |
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197 | .endm |
198 | ||
199 | /*-------------------------------------------------------------- | |
200 | * Restore all registers used by system call or Exceptions | |
201 | * SP should always be pointing to the next free stack element | |
202 | * when entering this macro. | |
203 | * | |
204 | * NOTE: | |
205 | * | |
206 | * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg | |
207 | * for memory load operations. If used in that way interrupts are deffered | |
208 | * by hardware and that is not good. | |
209 | *-------------------------------------------------------------*/ | |
210 | .macro EXCEPTION_EPILOGUE | |
211 | POPAX erbta | |
212 | POPAX lp_start | |
213 | POPAX lp_end | |
214 | ||
215 | POP r9 | |
216 | mov lp_count, r9 ;LD to lp_count is not allowed | |
217 | ||
218 | POPAX erstatus | |
219 | POPAX eret | |
220 | POP blink | |
221 | POP fp | |
222 | POP gp | |
223 | RESTORE_R12_TO_R0 | |
224 | ||
225 | ld sp, [sp] /* restore original sp */ | |
226 | /* orig_r0, ECR, user_r25 skipped automatically */ | |
227 | .endm | |
228 | ||
229 | /* Dummy ECR values for Interrupts */ | |
230 | #define event_IRQ1 0x0031abcd | |
231 | #define event_IRQ2 0x0032abcd | |
232 | ||
233 | .macro INTERRUPT_PROLOGUE LVL | |
234 | ||
235 | /* free up r9 as scratchpad */ | |
236 | PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg | |
237 | ||
7423cc0c | 238 | /* Which mode (user/kernel) was the system in when intr occurred */ |
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239 | lr r9, [status32_l\LVL\()] |
240 | ||
241 | SWITCH_TO_KERNEL_STK | |
242 | ||
5a343b9f VG |
243 | #ifdef CONFIG_ARC_CURR_IN_REG |
244 | /* Treat r25 as scratch reg (save on stack) and load with "current" */ | |
245 | PUSH r25 | |
246 | GET_CURR_TASK_ON_CPU r25 | |
247 | #else | |
248 | sub sp, sp, 4 | |
249 | #endif | |
6d1a20b1 | 250 | |
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251 | PUSH 0x003\LVL\()abcd /* Dummy ECR */ |
252 | sub sp, sp, 8 /* skip orig_r0 (not needed) | |
253 | skip pt_regs->sp, already saved above */ | |
254 | ||
255 | /* Restore r9 used to code the early prologue */ | |
256 | PROLOG_RESTORE_REG r9, @int\LVL\()_saved_reg | |
6d1a20b1 VG |
257 | |
258 | SAVE_R0_TO_R12 | |
259 | PUSH gp | |
260 | PUSH fp | |
261 | PUSH blink | |
262 | PUSH ilink\LVL\() | |
263 | PUSHAX status32_l\LVL\() | |
264 | PUSH lp_count | |
265 | PUSHAX lp_end | |
266 | PUSHAX lp_start | |
267 | PUSHAX bta_l\LVL\() | |
268 | .endm | |
269 | ||
270 | /*-------------------------------------------------------------- | |
271 | * Restore all registers used by interrupt handlers. | |
272 | * | |
273 | * NOTE: | |
274 | * | |
275 | * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg | |
276 | * for memory load operations. If used in that way interrupts are deffered | |
277 | * by hardware and that is not good. | |
278 | *-------------------------------------------------------------*/ | |
279 | .macro INTERRUPT_EPILOGUE LVL | |
280 | POPAX bta_l\LVL\() | |
281 | POPAX lp_start | |
282 | POPAX lp_end | |
283 | ||
284 | POP r9 | |
285 | mov lp_count, r9 ;LD to lp_count is not allowed | |
286 | ||
287 | POPAX status32_l\LVL\() | |
288 | POP ilink\LVL\() | |
289 | POP blink | |
290 | POP fp | |
291 | POP gp | |
292 | RESTORE_R12_TO_R0 | |
293 | ||
294 | ld sp, [sp] /* restore original sp */ | |
295 | /* orig_r0, ECR, user_r25 skipped automatically */ | |
296 | .endm | |
297 | ||
298 | /* Get thread_info of "current" tsk */ | |
299 | .macro GET_CURR_THR_INFO_FROM_SP reg | |
300 | bic \reg, sp, (THREAD_SIZE - 1) | |
301 | .endm | |
302 | ||
86c25466 | 303 | #ifndef CONFIG_ARC_PLAT_EZNPS |
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304 | /* Get CPU-ID of this core */ |
305 | .macro GET_CPU_ID reg | |
306 | lr \reg, [identity] | |
307 | lsr \reg, \reg, 8 | |
308 | bmsk \reg, \reg, 7 | |
309 | .endm | |
86c25466 | 310 | #endif |
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311 | |
312 | #endif /* __ASM_ARC_ENTRY_COMPACT_H */ |