projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| abe11dde VG |
2 | /* |
| 3 | * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) | |
| abe11dde VG |
4 | */ |
| 5 | /dts-v1/; | |
| 6 | ||
| 7 | /include/ "skeleton.dtsi" | |
| 8 | ||
| 9 | / { | |
| 618a9cd0 | 10 | model = "snps,nsim"; |
| fd155792 | 11 | compatible = "snps,nsim"; |
| abe11dde VG |
12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; | |
| 9ba7648c | 14 | interrupt-parent = <&core_intc>; |
| abe11dde VG |
15 | |
| 16 | chosen { | |
| 9c6375f7 | 17 | bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1"; |
| abe11dde VG |
18 | }; |
| 19 | ||
| 20 | aliases { | |
| 9c6375f7 | 21 | serial0 = &uart0; |
| abe11dde VG |
22 | }; |
| 23 | ||
| abe11dde VG |
24 | fpga { |
| 25 | compatible = "simple-bus"; | |
| 26 | #address-cells = <1>; | |
| 27 | #size-cells = <1>; | |
| 28 | ||
| 29 | /* child and parent address space 1:1 mapped */ | |
| 30 | ranges; | |
| 31 | ||
| b3d6aba8 VG |
32 | core_clk: core_clk { |
| 33 | #clock-cells = <0>; | |
| 34 | compatible = "fixed-clock"; | |
| 35 | clock-frequency = <80000000>; | |
| 36 | }; | |
| 37 | ||
| 9ba7648c | 38 | core_intc: interrupt-controller { |
| abe11dde VG |
39 | compatible = "snps,arc700-intc"; |
| 40 | interrupt-controller; | |
| 41 | #interrupt-cells = <1>; | |
| 42 | }; | |
| 43 | ||
| 9c6375f7 EP |
44 | uart0: serial@f0000000 { |
| 45 | compatible = "ns16550a"; | |
| 46 | reg = <0xf0000000 0x2000>; | |
| 47 | interrupts = <24>; | |
| 48 | clock-frequency = <50000000>; | |
| 49 | baud = <115200>; | |
| 50 | reg-shift = <2>; | |
| 51 | reg-io-width = <4>; | |
| 52 | no-loopback-test = <1>; | |
| abe11dde | 53 | }; |
| d0e63ed9 | 54 | |
| 6227e9f0 | 55 | arcpct0: pct { |
| 30fdd373 | 56 | compatible = "snps,arc700-pct"; |
| 0dd450fe | 57 | }; |
| abe11dde VG |
58 | }; |
| 59 | }; |