projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 556cc1c5 AB |
1 | /* |
| 2 | * Support for peripherals on the AXS10x mainboard | |
| 3 | * | |
| 4 | * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | / { | |
| 12 | axs10x_mb { | |
| 13 | compatible = "simple-bus"; | |
| 14 | #address-cells = <1>; | |
| 15 | #size-cells = <1>; | |
| 16 | ranges = <0x00000000 0xe0000000 0x10000000>; | |
| 17 | interrupt-parent = <&mb_intc>; | |
| 18 | ||
| 19 | clocks { | |
| 20 | i2cclk: i2cclk { | |
| 21 | compatible = "fixed-clock"; | |
| 22 | clock-frequency = <50000000>; | |
| 23 | #clock-cells = <0>; | |
| 24 | }; | |
| 25 | ||
| 26 | apbclk: apbclk { | |
| 27 | compatible = "fixed-clock"; | |
| 28 | clock-frequency = <50000000>; | |
| 29 | #clock-cells = <0>; | |
| 30 | }; | |
| 31 | ||
| 32 | mmcclk: mmcclk { | |
| 33 | compatible = "fixed-clock"; | |
| 34 | clock-frequency = <50000000>; | |
| 35 | #clock-cells = <0>; | |
| 36 | }; | |
| b8c1eca1 AB |
37 | |
| 38 | pguclk: pguclk { | |
| 39 | #clock-cells = <0>; | |
| 40 | compatible = "fixed-clock"; | |
| 41 | clock-frequency = <74440000>; | |
| 42 | }; | |
| 556cc1c5 AB |
43 | }; |
| 44 | ||
| 556cc1c5 AB |
45 | ethernet@0x18000 { |
| 46 | #interrupt-cells = <1>; | |
| 47 | compatible = "snps,dwmac"; | |
| 48 | reg = < 0x18000 0x2000 >; | |
| 49 | interrupts = < 4 >; | |
| 50 | interrupt-names = "macirq"; | |
| 51 | phy-mode = "rgmii"; | |
| 52 | snps,pbl = < 32 >; | |
| 53 | clocks = <&apbclk>; | |
| 54 | clock-names = "stmmaceth"; | |
| 6d1a2ade | 55 | max-speed = <100>; |
| 667a490b AB |
56 | mdio0 { |
| 57 | #address-cells = <1>; | |
| 58 | #size-cells = <0>; | |
| 59 | compatible = "snps,dwmac-mdio"; | |
| 60 | phy1: ethernet-phy@1 { | |
| 61 | reg = <1>; | |
| 62 | }; | |
| 63 | }; | |
| 556cc1c5 AB |
64 | }; |
| 65 | ||
| 66 | ehci@0x40000 { | |
| 67 | compatible = "generic-ehci"; | |
| 68 | reg = < 0x40000 0x100 >; | |
| 69 | interrupts = < 8 >; | |
| 70 | }; | |
| 71 | ||
| 72 | ohci@0x60000 { | |
| 73 | compatible = "generic-ohci"; | |
| 74 | reg = < 0x60000 0x100 >; | |
| 75 | interrupts = < 8 >; | |
| 76 | }; | |
| 77 | ||
| 7cacc5bf AB |
78 | /* |
| 79 | * According to DW Mobile Storage databook it is required | |
| 80 | * to use "Hold Register" if card is enumerated in SDR12 or | |
| 81 | * SDR25 modes. | |
| 82 | * | |
| 83 | * Utilization of "Hold Register" is already implemented via | |
| 84 | * dw_mci_pltfm_prepare_command() which in its turn gets | |
| 85 | * used through dw_mci_drv_data->prepare_command call-back. | |
| 86 | * This call-back is used in Altera Socfpga platform and so | |
| 87 | * we may reuse it saying that we're compatible with their | |
| 88 | * "altr,socfpga-dw-mshc". | |
| 89 | * | |
| 90 | * Most probably "Hold Register" utilization is platform- | |
| 91 | * independent requirement which means that single unified | |
| 92 | * "snps,dw-mshc" should be enough for all users of DW MMC once | |
| 93 | * dw_mci_pltfm_prepare_command() is used in generic platform | |
| 94 | * code. | |
| 95 | */ | |
| 556cc1c5 | 96 | mmc@0x15000 { |
| 7cacc5bf | 97 | compatible = "altr,socfpga-dw-mshc"; |
| 556cc1c5 AB |
98 | reg = < 0x15000 0x400 >; |
| 99 | num-slots = < 1 >; | |
| 100 | fifo-depth = < 16 >; | |
| 101 | card-detect-delay = < 200 >; | |
| 102 | clocks = <&apbclk>, <&mmcclk>; | |
| 103 | clock-names = "biu", "ciu"; | |
| 104 | interrupts = < 7 >; | |
| 105 | bus-width = < 4 >; | |
| 106 | }; | |
| 107 | ||
| 108 | uart@0x20000 { | |
| 109 | compatible = "snps,dw-apb-uart"; | |
| 110 | reg = <0x20000 0x100>; | |
| 111 | clock-frequency = <33333333>; | |
| 112 | interrupts = <17>; | |
| 113 | baud = <115200>; | |
| 114 | reg-shift = <2>; | |
| 115 | reg-io-width = <4>; | |
| 116 | }; | |
| 117 | ||
| 118 | uart@0x21000 { | |
| 119 | compatible = "snps,dw-apb-uart"; | |
| 120 | reg = <0x21000 0x100>; | |
| 121 | clock-frequency = <33333333>; | |
| 122 | interrupts = <18>; | |
| 123 | baud = <115200>; | |
| 124 | reg-shift = <2>; | |
| 125 | reg-io-width = <4>; | |
| 126 | }; | |
| 127 | ||
| 128 | /* UART muxed with USB data port (ttyS3) */ | |
| 129 | uart@0x22000 { | |
| 130 | compatible = "snps,dw-apb-uart"; | |
| 131 | reg = <0x22000 0x100>; | |
| 132 | clock-frequency = <33333333>; | |
| 133 | interrupts = <19>; | |
| 134 | baud = <115200>; | |
| 135 | reg-shift = <2>; | |
| 136 | reg-io-width = <4>; | |
| 137 | }; | |
| 138 | ||
| 139 | i2c@0x1d000 { | |
| 140 | compatible = "snps,designware-i2c"; | |
| 141 | reg = <0x1d000 0x100>; | |
| 142 | clock-frequency = <400000>; | |
| 143 | clocks = <&i2cclk>; | |
| 144 | interrupts = <14>; | |
| 145 | }; | |
| 146 | ||
| 147 | i2c@0x1e000 { | |
| 148 | compatible = "snps,designware-i2c"; | |
| 149 | reg = <0x1e000 0x100>; | |
| 150 | clock-frequency = <400000>; | |
| 151 | clocks = <&i2cclk>; | |
| 152 | interrupts = <15>; | |
| 153 | }; | |
| 154 | ||
| 155 | i2c@0x1f000 { | |
| 156 | compatible = "snps,designware-i2c"; | |
| 157 | #address-cells = <1>; | |
| 158 | #size-cells = <0>; | |
| 159 | reg = <0x1f000 0x100>; | |
| 160 | clock-frequency = <400000>; | |
| 161 | clocks = <&i2cclk>; | |
| 162 | interrupts = <16>; | |
| 163 | ||
| b8c1eca1 AB |
164 | adv7511:adv7511@39{ |
| 165 | compatible="adi,adv7511"; | |
| 166 | reg = <0x39>; | |
| 167 | interrupts = <23>; | |
| 168 | adi,input-depth = <8>; | |
| 169 | adi,input-colorspace = "rgb"; | |
| 170 | adi,input-clock = "1x"; | |
| 171 | adi,clock-delay = <0x03>; | |
| 172 | ||
| 173 | ports { | |
| 174 | #address-cells = <1>; | |
| 175 | #size-cells = <0>; | |
| 176 | ||
| 177 | /* RGB/YUV input */ | |
| 178 | port@0 { | |
| 179 | reg = <0>; | |
| 180 | adv7511_input:endpoint { | |
| 181 | remote-endpoint = <&pgu_output>; | |
| 182 | }; | |
| 183 | }; | |
| 184 | ||
| 185 | /* HDMI output */ | |
| 186 | port@1 { | |
| 187 | reg = <1>; | |
| 188 | adv7511_output: endpoint { | |
| 189 | remote-endpoint = <&hdmi_connector_in>; | |
| 190 | }; | |
| 191 | }; | |
| 192 | }; | |
| 193 | }; | |
| 194 | ||
| 556cc1c5 AB |
195 | eeprom@0x54{ |
| 196 | compatible = "24c01"; | |
| 197 | reg = <0x54>; | |
| 198 | pagesize = <0x8>; | |
| 199 | }; | |
| 200 | ||
| 201 | eeprom@0x57{ | |
| 202 | compatible = "24c04"; | |
| 203 | reg = <0x57>; | |
| 204 | pagesize = <0x8>; | |
| 205 | }; | |
| 206 | }; | |
| 207 | ||
| b8c1eca1 AB |
208 | hdmi0: connector { |
| 209 | compatible = "hdmi-connector"; | |
| 210 | type = "a"; | |
| 211 | port { | |
| 212 | hdmi_connector_in: endpoint { | |
| 213 | remote-endpoint = <&adv7511_output>; | |
| 214 | }; | |
| 215 | }; | |
| 216 | }; | |
| 217 | ||
| 556cc1c5 AB |
218 | gpio0:gpio@13000 { |
| 219 | compatible = "snps,dw-apb-gpio"; | |
| 220 | reg = <0x13000 0x1000>; | |
| 221 | #address-cells = <1>; | |
| 222 | #size-cells = <0>; | |
| 223 | ||
| 224 | gpio0_banka: gpio-controller@0 { | |
| 225 | compatible = "snps,dw-apb-gpio-port"; | |
| 226 | gpio-controller; | |
| 227 | #gpio-cells = <2>; | |
| 228 | snps,nr-gpios = <32>; | |
| 229 | reg = <0>; | |
| 230 | }; | |
| 231 | ||
| 232 | gpio0_bankb: gpio-controller@1 { | |
| 233 | compatible = "snps,dw-apb-gpio-port"; | |
| 234 | gpio-controller; | |
| 235 | #gpio-cells = <2>; | |
| 236 | snps,nr-gpios = <8>; | |
| 237 | reg = <1>; | |
| 238 | }; | |
| 239 | ||
| 240 | gpio0_bankc: gpio-controller@2 { | |
| 241 | compatible = "snps,dw-apb-gpio-port"; | |
| 242 | gpio-controller; | |
| 243 | #gpio-cells = <2>; | |
| 244 | snps,nr-gpios = <8>; | |
| 245 | reg = <2>; | |
| 246 | }; | |
| 247 | }; | |
| 248 | ||
| 249 | gpio1:gpio@14000 { | |
| 250 | compatible = "snps,dw-apb-gpio"; | |
| 251 | reg = <0x14000 0x1000>; | |
| 252 | #address-cells = <1>; | |
| 253 | #size-cells = <0>; | |
| 254 | ||
| 255 | gpio1_banka: gpio-controller@0 { | |
| 256 | compatible = "snps,dw-apb-gpio-port"; | |
| 257 | gpio-controller; | |
| 258 | #gpio-cells = <2>; | |
| 259 | snps,nr-gpios = <30>; | |
| 260 | reg = <0>; | |
| 261 | }; | |
| 262 | ||
| 263 | gpio1_bankb: gpio-controller@1 { | |
| 264 | compatible = "snps,dw-apb-gpio-port"; | |
| 265 | gpio-controller; | |
| 266 | #gpio-cells = <2>; | |
| 267 | snps,nr-gpios = <10>; | |
| 268 | reg = <1>; | |
| 269 | }; | |
| 270 | ||
| 271 | gpio1_bankc: gpio-controller@2 { | |
| 272 | compatible = "snps,dw-apb-gpio-port"; | |
| 273 | gpio-controller; | |
| 274 | #gpio-cells = <2>; | |
| 275 | snps,nr-gpios = <8>; | |
| 276 | reg = <2>; | |
| 277 | }; | |
| 278 | }; | |
| b8c1eca1 AB |
279 | |
| 280 | pgu@17000 { | |
| 281 | compatible = "snps,arcpgu"; | |
| 282 | reg = <0x17000 0x400>; | |
| 283 | encoder-slave = <&adv7511>; | |
| 284 | clocks = <&pguclk>; | |
| 285 | clock-names = "pxlclk"; | |
| 286 | ||
| 287 | port { | |
| 288 | pgu_output: endpoint { | |
| 289 | remote-endpoint = <&adv7511_input>; | |
| 290 | }; | |
| 291 | }; | |
| 292 | }; | |
| 556cc1c5 AB |
293 | }; |
| 294 | }; |